KR100793672B1 - Semiconductor device and its manufacturing method - Google Patents

Abstract

It is an object of the present invention to manufacture a plurality of types of transistors having desired characteristics with a small number of processes. The semiconductor device of the present invention is formed in an isolation region reaching a first depth, first and second wells of a first conductivity type, a first insulating well, a gate insulating film of a first thickness, and a source of a second conductivity type. And a second transistor having a drain region and a gate electrode, a gate insulating film having a second thickness formed in the second well and thinner than the first thickness, a source / drain region of a second conductivity type, and a gate electrode. Wherein the first well has a first impurity concentration distribution having a maximum only at a depth equal to or deeper than the first depth, and the second well has a first impurity concentration distribution equal to the first well and shallower than the first depth. The impurity concentration distribution having a maximum value at the second depth is polymerized to have a second impurity concentration distribution having a maximum value at the second depth as a whole.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device operating at a plurality of voltages and a manufacturing method thereof.

With high integration of semiconductor integrated circuit devices (ICs), transistors, which are components of ICs, have been miniaturized. Accompanying the miniaturization of the transistor, the operating voltage decreases. In a system-on-chip, there is also a strong desire to mix heterogeneous circuits such as logic circuits of low voltage operation and flash memory circuits including flash memory driving circuits of high voltage operation. In order to realize this, it is necessary to integrate the logic circuit of the low voltage operation and the flash memory driving circuit of the high voltage operation on the same semiconductor substrate.

In the case of configuring a CMOS circuit, n-channel transistors that operate at high and low voltages and p-channel transistors that operate at high and low voltages are formed.

11A-11F show a typical method of manufacturing such a semiconductor device.

As shown in FIG. 11A, a shallow element isolation groove 102 (STI: Shallow Trench isolation) is formed in the surface of the semiconductor substrate 101 in which an insulating film is filled in a well-known manner. The figure shows four active areas defined as STIs. In the left two active regions, n-channel MOS transistors N-LV and N-HV having a thin gate insulating film for low voltage LV and a thick gate insulating film for high voltage HV are formed.

In the two active regions on the right side of the figure, two p-channel MOS transistors P-LV and P-HV having a thin gate insulating film for low voltage LV and a thick gate insulating film for high voltage HV are formed.

First, a photoresist mask PR51 having an opening is formed in the n-channel M0S transistor region, and a channel stop region CSP is formed below the ion implantation region of the p-type impurity forming the p-type well WP and the device isolation region. Ion implantation of p-type impurity and ion implantation (Vt1) of p-type impurity for setting the threshold Vt of the transistor having a thick insulating film to a desired value. Thereafter, photoresist mask PR51 is removed.

As shown in Fig. 11B, an ion implantation and element of n-type impurity forming a photoresist mask PR52 having an opening in the p-channel MOS transistor region and forming an n-type well WN in the p-channel MOS transistor region. Ion implantation of n-type impurity for forming the channel stop region CSN under the isolation region and ion implantation (Vt2) of n-type impurity for controlling the threshold Vt of the p-channel MOS transistor having a thick insulating film are performed. Thereafter, photoresist mask PR52 is removed.

In the above ion implantation, the threshold control is performed in the transistor regions N-HV and P-HV having a thick gate insulating film, but the threshold control ions are used in the transistor regions N-LV and P-LV having a thin gate insulating film. Infusion is insufficient.

As shown in Fig. 11C, a photoresist mask PR53 having an opening is formed in an n-channel MOS transistor region N-LV having a thin gate insulating film, and an n-channel MOS transistor region forming a thin gate insulating film. Further ion implantation (Vt3) of p-type impurity is performed to adjust the threshold voltage of (N-LV). Thereafter, photoresist mask PR53 is removed.

As shown in FIG. 11D, a photoresist mask PR54 having an opening is formed in the p-channel MOS transistor region P-LV forming the thin gate insulating film, and the p-channel MOS transistor region forming the thin gate insulating film ( P-LV is subjected to additional ion implantation (Vt4) of n-type impurities for controlling the threshold voltage. After that, the photoresist mask PR54 is removed. Next, a thick gate insulating film GI1 is formed over the entire semiconductor substrate.

As shown in Fig. 11E, photoresist mask PR55 is formed over the grown gate insulating film to cover the transistor region having a thick gate insulating film, and the transistor region having a thin gate insulating film is exposed. The gate insulating film GI1 is removed using the photoresist mask PR55 as an etching mask. After that, the photoresist mask PR55 is removed.

When the thin gate insulating film is formed on the semiconductor substrate, the thin gate insulating film GI2 is formed in the region where the thick gate insulating film is removed. In this manner, the thick gate insulating film GI1 and the thin gate insulating film GI2 are formed.

As shown in FIG. 11F, a gate electrode layer of polycrystalline silicon is formed on the gate insulating film, and patterned to form a gate electrode G. As shown in FIG. Ion implantation of the extension portion of the source / drain regions is performed using the gate electrode as a mask. After forming sidewall spacers, such as silicon oxide, ion implantation of a high concentration source / drain region is performed. Ion implantation of the n-channel MOS transistor and the p-channel MOS transistor is selectively performed using a resist mask, respectively.

In this way, a CMOS semiconductor device as shown in Fig. 11F is formed. According to the manufacturing method described above, eight ion implantations are performed using four masks for well and threshold Vt control in addition to the formation of the gate insulating film. Complex manufacturing processes lead to increased manufacturing costs and lower yields. It is desirable to simplify the manufacturing process.

Japanese Patent Laid-Open No. Hei 11-40004 proposes a method of manufacturing a semiconductor device having reduced process water. The manufacturing method of the semiconductor device which reduced this process number is demonstrated below.

As shown in FIG. 12A, four active regions N-LV, N-HV, P-LV, and P-HV are defined in the silicon substrate 101 as the element isolation region 102 as in FIG. 11A. A photoresist mask PR51 having an opening in the n-channel transistor region is formed, and ion implantation is performed three times in the n-channel MOS transistor region to form a p-type well WP, a p-type channel stop region CSP, and a p-type threshold value. The adjustment area VtP is formed.

The concentration of the ion implantation for adjusting the threshold is set to a value suitable for the transistor N-LV having a thin gate insulating film. This concentration is too high for the threshold adjustment impurity ion implantation of the n-channel MOS transistor (N-HV) having a thick gate insulating film. Thereafter, photoresist mask PR51 is removed.

As shown in Fig. 12B, a photoresist mask PR52 having an opening is formed in the p-channel MOS transistor region, and n-type well WN, n-type channel stop region CSN, n in the p-channel MOS transistor region. N-type impurities are ion-implanted to form the type threshold adjustment region VtN.

The concentration of the ion implantation for adjusting the threshold is set to a concentration suitable for the p-channel MOS transistor (P-HV) having a thick gate insulating film. This concentration is insufficient for the p-channel MOS transistor P-LV having a thin gate insulating film. Photoresist mask PR52 is then removed.

As shown in Fig. 12C, the photoresist mask PR56 having openings in the n-channel MOS transistor region N-HV forming the thick gate insulating film and the p-channel MOS transistor region P-LV forming the thin gate insulating film. ) And n-type impurities are additionally ion implanted. In the p-channel MOS transistor region P-LV forming the thin gate insulating film, the desired impurity concentration is obtained by ion implantation of two n-type impurities, and the threshold value is appropriately adjusted.

In the n-channel MOS transistor region (N-HV) having a thick gate insulating film, an excessively high p-type impurity concentration initially ion implanted is compensated by ion implantation of an additionally implanted n-type impurity, resulting in a decrease in impurity concentration. Thereafter, photoresist mask PR56 is removed.

As shown in FIG. 12D, a thick gate insulating film GI1 is formed. Using the photoresist mask PR55 covering the transistor having the thick gate insulating film as an etching mask, the thick gate insulating film in the region forming the thin gate insulating film is removed. After that, the photoresist mask PR55 is removed to form a thin gate insulating film GI2.

As shown in Fig. 12E, a semiconductor device is completed by forming a gate electrode, a source / drain region, or the like in a known manner.

According to this method, except for the selective removal of the gate insulating film, the impurity concentration distribution in the well is formed by three mask processes and seven ion implantations. Compared with the process shown to FIGS. 11A-11D, 1 mask is reduced and ion implantation is reduced once.

Although the manufacturing process is simplified, it is not possible to independently set the threshold Vt of the n-channel MOS transistor N-HV with a thick gate insulating film. A certain amount of compromise is required regarding the setting of the threshold value Vt. In addition, when the threshold setting is changed at the development stage, the threshold setting of other transistors may also need to be changed.

As described above, when a plurality of transistors that handle multiple voltages are to be manufactured, the number of steps is likely to increase. If it is going to adopt the manufacturing method which reduces process water, a new problem will arise easily. There is a need for a semiconductor device that operates at multiple voltages and can also be manufactured with a simplified manufacturing method.

An object of the present invention is to provide a semiconductor device having a plurality of transistors which can be manufactured with a small number of manufacturing steps and which perform desired characteristics.

Another object of the present invention is to provide a method for manufacturing a semiconductor device for manufacturing a plurality of transistors that operate at multiple voltages with a small number of processes.

According to the present invention, the device isolation region formed to reach the first depth position from the surface of the semiconductor substrate, the first and second wells of the first conductivity type formed in the semiconductor substrate, and the first well are formed. And a first transistor having a gate insulating film of a first thickness, a source / drain region of a second conductivity type opposite to the first conductivity type, and a gate electrode, and formed in the second well, wherein the first thickness A second transistor having a thinner second thickness gate insulating film, a source / drain region of a second conductivity type, and a gate electrode, wherein the first well is at a depth position equal to or deeper than the first depth position; Only has a first impurity concentration distribution having a maximum value, and the second well has a first impurity concentration distribution identical to the first well and an impurity concentration having a maximum value at a second depth position shallower than the first depth position. The semiconductor device is provided by polymerizing a capsule, having a second impurity concentration distribution as a whole it represents the maximum value in the second depth position.

According to another aspect of the invention, (a) forming a device isolation region extending from the surface to the first depth position on the semiconductor substrate, and (b) the first and second wells of the first conductivity type in the semiconductor substrate (C) forming a gate insulating film having a first thickness on the surface of the first well, and forming a gate insulating film having a second thickness thinner than the first thickness on the surface of the second well; Forming a gate electrode on the gate insulating film, and (e) forming a source / drain region in the semiconductor substrate on both sides of the gate electrode, wherein step (b) includes (b1) the first and the first Ion implanting a first impurity concentration distribution having a local maximum only at a depth position equal to or greater than the first depth in common to the two wells, and (b2) optionally the first depth with respect to the first and second wells; Approximately equal depth to And implanting a second impurity concentration distribution having a maximum value at the maximum value; and (b3) ion implanting a third impurity concentration distribution having a maximum value at a depth position shallower than the first depth only in the second well. A method for manufacturing a semiconductor device is provided.

1A to 1D are cross-sectional views showing main steps of the manufacturing method of the semiconductor device according to the embodiment of the present invention.

2A to 2D are cross-sectional views showing modifications of the above-described embodiment.

3A to 3E are sectional views showing still another modification of the above-described embodiment.

4A to 4D are sectional views showing still another modification of the above-described embodiment.

5A to 5E are cross-sectional views showing the main steps of the manufacturing method of the semiconductor device in which the above-described embodiment is applied to the manufacturing method of the CMOS semiconductor device.

6A to 6D are plan views, tables, and graphs showing the structure of each transistor manufactured according to the manufacturing method of FIGS. 5A to 5F.

7 is a cross-sectional view schematically showing the configuration of a semiconductor device having more kinds of transistors.

8A to 8ZC are cross-sectional views illustrating the method for manufacturing the semiconductor device shown in FIG. 7.

9A and 9B are cross-sectional views illustrating the creation of the pocket area.

10A to 10J are cross-sectional views illustrating a method for manufacturing a semiconductor device in accordance with another embodiment of the present invention.

11A to 11F are cross-sectional views showing the main steps of the manufacturing method for manufacturing high voltage and low voltage CMOS transistors by standard techniques.

12A to 12E are cross-sectional views showing examples of manufacturing methods for manufacturing high voltage and low voltage CMOS transistors in a simplified process.

Fig. 13 is a sectional view schematically showing a configuration in which a logic circuit of low voltage operation and a high voltage transistor for driving a flash memory cell are integrated.

14A to 14D are sectional views schematically showing an example of a manufacturing method for manufacturing the plurality of types of transistors shown in FIG. 13.

15A to 15C are cross-sectional views showing examples of other manufacturing methods for manufacturing the plurality of types of transistors shown in FIG. 13.

16A to 16C are cross-sectional views showing main steps of still another manufacturing method for manufacturing the plurality of types of transistors shown in FIG. 13.

Consider a case where flash memory cells are mixed in a logic circuit of 1.2 V operation. High voltage is required for program (write) / erase and read of the flash memory. Such high voltage is usually generated by boosting the 1.2 V power supply voltage supplied from the outside in an internal circuit. In order to generate a high voltage from such a low voltage, a transistor that withstands a high voltage is required. It is also desirable to include both high threshold transistors for preventing leakage and low threshold transistors for efficiently boosting voltage.

Fig. 13 shows three kinds of transistors formed reflecting this request. The high voltage low threshold transistor HV-LVt, the high voltage high threshold transistor HV-HVt, and the low voltage transistor LV are formed. The high voltage transistors HV-LVt and HV-HVt have, for example, a gate oxide film having a thickness of 16 nm. The low voltage transistor LV has, for example, a gate oxide film having a thickness of 2 nm.

Note that the high voltage transistor is not limited to a transistor that operates at 5 V, and may include a transistor that operates other driving voltages. For example, even when a high voltage input / output interface is provided, both high threshold transistors for reducing the standby current and low threshold transistors for operating speed are desired.

There is a need for a simplified manufacturing method that can be applied even when integrating various transistors. In particular, when the operating voltage is low, for example, about 1.2 V, the range of acceptable thresholds is also very narrow, and it is difficult to achieve desired performance by a method in which thresholds of individual transistors cannot be set independently. Hereinafter, the manufacturing method which manufactures three types of transistors as shown in FIG. 13 is examined.

14A-14D show examples of the most standard manufacturing methods.

As shown in Fig. 14A, first, a photoresist mask PR61 for exposing an active region forming the high voltage low threshold voltage transistor HV-LVt is formed, and then a p-type impurity or p-type for forming the well WP1 is formed. Ion implantation of the p-type impurity for forming the channel stop region CSP1 and the p-type impurity for the threshold adjustment VtP1 is performed three times in total. Thereafter, photoresist mask PR61 is removed.

As shown in Fig. 14B, the photoresist mask PR62 having an opening is formed in a region where the transistors HV-HVt of high voltage high threshold voltage are formed, and the channel stop region CSP2 for forming the well WP2 is formed. Three types of ion implantation are performed for formation and for threshold adjustment (VtP2). Thereafter, photoresist mask PR62 is removed.

As shown in FIG. 14C, the photoresist mask PR63 exposing the low voltage transistor LV region is formed, for forming the well WP3, for forming the channel stop region CSP3, and for adjusting the threshold value VtP3. Ion implantation of p-type impurities is performed. Thereafter, photoresist mask PR63 is removed. In this manner, three kinds of ion implantation are performed for each transistor region, a thick gate oxide film is formed thereafter, the gate oxide film once formed is removed in the region where the thin gate oxide film is formed, and a new thin gate oxide film is newly formed. . Thereafter, a gate electrode such as polycrystalline silicon is formed in accordance with a conventional method.

Fig. 14D shows three kinds of n-channel MOS transistors formed in this way. In order to form three types of transistors, three masks and nine ion implantations are performed after element isolation and before formation of the gate insulating film. It is desirable to reduce the number of processes.

15A to 15C show an example of a manufacturing method that simplifies the process.

As shown in Fig. 15A, the photoresist mask PR71 exposing the high voltage transistors HV-LVt and HV-HVt regions is formed, and the well WP1 and the channel stop region CSP1 are common to the two transistor regions. And ion implantation three times to form the threshold adjustment region VtP1.

In addition, the ion implantation for adjusting the threshold is a concentration that produces an appropriate threshold in the high voltage transistor HV-LVt having a low threshold. In the high voltage high threshold transistors HV-HVt, an appropriate threshold value is not obtained as it is.

As shown in Fig. 15B, a resist mask PR62 exposing the high threshold, high voltage transistor (HV-HVt) region is formed, and further ion implantation is performed for threshold adjustment VtP2. The added ion implantation raises the threshold to an appropriate value. Thereafter, photoresist mask PR62 is removed.

As shown in Fig. 15C, the photoresist mask PR63 exposing the low voltage transistor LV region is formed, and the well WP2, the channel stop region CSP2, and the threshold adjustment VtP3 are formed in the low voltage transistor region. Ion implantation three times.

According to this method, the mask does not change to three, but the number of ion implantation can be reduced twice to seven times.

16A-16C show another manufacturing method that simplifies the process.

As shown in Fig. 16A, a photoresist mask PR81 for exposing three kinds of transistor regions is formed, and for forming wells WP, channel stop regions CSP, and threshold adjustments VtP1 in common in all regions. Ion implantation. Ion implantation for threshold adjustment is performed on the conditions adjusted so that it may be suitable for the low threshold and high voltage transistor (HV-LVt). Thereafter, photoresist mask PR81 is removed.

As shown in Fig. 16B, photoresist mask PR62 having an opening exposing the high threshold and high voltage transistors HV-HVt is formed, and further ion implantation is performed for threshold adjustment VtP2. The resist mask PR62 is then removed.

As shown in Fig. 16C, photoresist mask PR63 exposing the low voltage transistor region LV is formed, and further ion implantation is performed for threshold adjustment VtP3 of the low voltage transistor.

According to this method, the mask does not change to three sheets, but the number of ion implantation can be further reduced twice in five times.

According to the studies of the present inventors, in the case of using the method of FIGS. 16A to 16C, when the ion implantation concentration for forming the channel stop region is increased in order to increase the threshold of the parasitic transistor for the 1.2 V operation transistor, the concentration of the 5 V transistor portion alone is increased. Too high. As a result, it has been found that low threshold, high voltage transistor (HV-LVt) cannot be realized. Therefore, the manufacturing method of FIGS. 16A-16C with the fewest process number cannot be employ | adopted as it is.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1A to 1D are cross-sectional views showing main steps of the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

As shown in FIG. 1A, the STI 12 is formed on one surface of the semiconductor substrate 11 in a known manner. A plurality of active regions is defined by the STI 12. Hereinafter, the active region and the transistor formed therein are denoted by the same reference numerals. Ion implantation and an ion implanted area are also shown with the same code | symbol.

A high voltage low threshold transistor HV-LVt is formed in the active region on the left side of the figure. In the center active region in the figure, a high voltage high threshold transistor (HV-HVt) is formed. The low voltage transistor LV is formed in the active region on the right side of the drawing.

First, a photoresist mask PR11 having an opening exposing three active regions is formed, and approximately each of the ion implantation 14 and STI forming a well having a maximum at a depth position equal to or deeper than STI in each region. Ion implantation 15 is performed to form a channel stop region having a maximum at an equal depth position. The channel stop region 15 produces a low threshold in the high voltage low threshold transistors HV-LVt. Thereafter, photoresist mask PR11 is removed.

In addition, although the peak part of each impurity concentration was shown by the area in the figure, the actual impurity concentration distribution is expanded to wider area | region. Even if the position of the maximum value changes somewhat, it does not affect the operation | movement of a semiconductor device very much. "Equivalence" and "approximately equivalent" include a range that can be considered to be the same in operation of the semiconductor device.

As shown in FIG. 1B, a photoresist mask PR12 having an opening for exposing the high voltage high threshold transistor HV-HVt and the low voltage transistor LV is formed, and the high voltage high threshold transistor HV-HVt or The larger the dose amount that achieves the threshold value of the field transistor relative to the low voltage transistor LV is further ion implanted to form the channel stop region 15x. When the high voltage high threshold transistor HV-HVt is 0.5 V or more, the dose amount which achieves the former electron is large, and the high voltage high threshold transistor HV-HVt can be set freely. Thereafter, photoresist mask PR12 is removed.

As shown in FIG. 1C, photoresist mask PR13 for opening the low voltage transistor LV is formed, and the threshold value adjusting ion implantation 16 is performed. Thereafter, photoresist mask PR13 is removed.

Through the above steps, well regions for three kinds of transistors can be formed by three masks and four ion implantations. This method can be favorably performed even for a miniaturized transistor such as a low voltage transistor having a gate length of 0.13 mu m and an operating voltage of 1.2 V.

If the impurity to be implanted is p-type, an n-channel MOS transistor can be formed. If the impurity to be implanted is n-type, a p-channel MOS transistor can be formed.

As shown in FIG. 1D, a thick gate oxide film GI1 and a thin gate oxide film GI2 are formed on the surface of the semiconductor substrate, a gate electrode is formed of polysilicon, and ion implantation is performed on the surface of the semiconductor substrate. After that, sidewall spacers are formed, and ion implantation is performed in the high concentration source / drain regions to complete each transistor. The high voltage transistor 17 and the low voltage transistor 18 are formed.

In addition, in the above-described embodiment, common ion implantation and channel stop ion implantation were performed for the three active regions. It is also possible to omit channel stop ion implantation for a high voltage low threshold transistor by increasing the concentration of the well implantation and / or making the implantation depth shallow. 2A to 2D show this modification.

As shown in Fig. 2A, photoresist mask PR11 having an opening exposing three active regions is formed, and ion implantation 14s of a common well region is performed for the three active regions. The well region ion implantation 14s is set to have a shallower depth and a higher concentration than the well region ion implantation 14 of FIG. 1A.

By the ion implantation 14s for wells, the role of the ion implantation for channel stop region formation is almost achieved in the high voltage low threshold transistor HV-LVt. Thereafter, photoresist mask PR11 is removed.

As shown in Fig. 2B, a photoresist mask PR12 having an opening exposing the high voltage high threshold transistors HV-HVt and the low voltage transistor LV is formed, and ion implantation 15y for channel stop region formation is formed. Do it. Thereafter, photoresist mask PR12 is removed.

As shown in Fig. 2C, photoresist mask PR13 having an opening exposing the low voltage transistor LV region is formed, and threshold adjustment ion implantation 16 is performed. Thereafter, photoresist mask PR13 is removed. In this manner, a well region in which three kinds of transistors are formed by three masks and three ion implantations is formed.

As shown in FIG. 2D, the high voltage insulating gate electrode 17 and the low voltage insulating gate electrode 18 are formed in a known manner.

In the case where the flash memory and the logic circuit are mixed, a high voltage (5 V) n-channel MOS transistor may be formed in the triple well to process the negative voltage.

The modification which added the ion implantation which forms a triple well to the process of FIGS. 1A-1C is demonstrated below.

As shown in Fig. 3A, a photoresist mask PR14 having an opening exposing the high voltage transistors HV-LVt and HV-HVt is formed, and n-type impurities are ion implanted to form an n-type well 19 for triple wells. ). Thereafter, photoresist mask PR14 is removed.

As shown in Fig. 3B, a photoresist mask PR11 having an opening for exposing three kinds of transistor regions is formed, and ion implantation 14 of the p-type well and ion in the channel stop region for the three transistor regions. Injection 15 is performed. Thereafter, photoresist mask PR11 is removed.

As shown in Fig. 3C, a photoresist mask PR12 having an opening exposing the high voltage high threshold transistors HV-HVt and the low voltage transistor LV region is formed, and further ion implantation for forming the channel stop region is performed. Do it. The channel stop region 15x has a higher impurity concentration than the original channel stop region 15. Thereafter, photoresist mask PR12 is removed.

As shown in FIG. 3D, photoresist mask PR13 having an opening exposing the low voltage transistor LV is formed, and the threshold value adjusting ion implantation 16 is performed. Thereafter, photoresist mask PR13 is removed.

As shown in Fig. 3E, the photoresist mask PR15 used in the n-type well region forming step of the p-channel MOS transistor is formed around the n-type well 19 formed around the n-channel MOS transistor region. An opening is formed in the continuous area.

With the ion implantation of the n-type well, the n-type region 20 is ion-implanted in the periphery of the n-type well 19 of the p-channel transistor region, and an n-type well for triple well is formed. In this way, a semiconductor device having triple wells is formed.

4A-4D illustrate another variant of forming a triple well.

As shown in Fig. 4A, the photoresist mask PR14 having an opening exposing the high voltage transistors HV-LVt and HV-HVt regions is formed, and the n-type well 19 for the triple well and the p-type well 14H are formed. Ion implantation into the channel stop region 15H. Thereafter, photoresist mask PR14 is removed.

As shown in Fig. 4B, a high voltage high threshold transistor HV-HVt, a photoresist mask PR12 having an opening exposing the low voltage transistor LV region is formed, an ion implantation 14L for the well region, and a channel. Stop ion implantation 15L is performed. Thereafter, photoresist mask PR12 is removed.

In the high voltage high threshold transistor (HV-HVt) region, two well region ion implantations overlap, a p-type well 14M having a high impurity concentration is formed, and two ion implantation regions for the channel stop region overlap, A channel stop region 15M having a high impurity concentration is formed. In the region for the low voltage transistor LV, a well region 14L having a low impurity concentration and a channel stop region 15L having a low impurity concentration are formed only by this on-injection.

As shown in Fig. 4C, photoresist mask PR13 having an opening exposing the low voltage transistor LV is formed, and threshold injection ion implantation 16L is performed. Only in the low voltage transistor LV, ion implantation for threshold adjustment is performed.

As shown in Fig. 4D, in the n-type well forming step, an opening is formed in the photoresist mask PR15 so as to be continuous around the n-type well 19, and ion implantation 20 of n-type impurities is performed. N wells of the triple well are formed.

In this manner, a semiconductor device having a well having a desired configuration can be formed by the number of steps in which one mask is reduced as compared with FIGS. 3A to 3E. In the case of the p-channel MOS device, the same manufacturing process can be adopted by reversing the conductivity type of the impurity.

5A shows three n-channel transistor regions on the left side and three p-channel transistor regions on the right side. Similarly to the manufacturing method shown in FIGS. 1A-1D, photoresist mask PR11 exposing the n-channel transistor region is formed, and ion implantation of p-type well 14 and p-type channel stop 15 is performed.

In the ion implantation of the p-type well 14, for example, B ⁺ ions are implanted at an acceleration energy of 400 keV and a dose amount of 1.5 × 10 ¹³ cm ⁻² . In the ion implantation of the p-type channel stop 15, for example, B ⁺ ions are implanted at an acceleration energy of 100 keV and a dose amount of 2 × 10 ¹² . Thereafter, photoresist mask PR11 is removed.

As shown in Fig. 5B, a photoresist mask PR12 having an opening exposing the high voltage high threshold voltage n-channel transistor (N-HV-HVt) region and the low voltage n-channel transistor (N-LV) region is formed, Additional B ⁺ ion implantation for channel stop region formation is performed at an acceleration energy of 100 keV and a dose of 6 × 10 ¹² cm ⁻² . Further ion implantation is performed, and a channel stop region 15x having an increased impurity concentration is formed. Thereafter, photoresist mask PR12 is removed.

As shown in Fig. 5C, photoresist mask PR21 having an opening exposing the p-channel transistor region is formed, and ion implantation for forming n-type well 24 is performed. P ⁺ ions are implanted with an acceleration energy of 600 keV and a dose of 3.0 x 10 ¹³ cm ^-2 . After that, the photoresist mask PR21 is removed.

As shown in Fig. 5D, a photoresist mask PR22 having an opening exposing the high voltage high threshold voltage p-channel transistor P-HV-HVt and the low voltage P-channel transistor P-LV region is formed, and the channel is formed. P ⁺ ion implantation for forming the stop region 25 is performed at an acceleration energy of 240 keV and a dose of 5 x 10 ¹² cm ^-2 . Thereafter, photoresist mask PR22 is removed.

As shown in Fig. 5E, a photoresist mask PR13 having an opening exposing the n-channel low voltage transistor N-LV is formed, and the B ⁺ ion implantation 16 of the p-type impurity for threshold adjustment is accelerated to 10 keV, the dose is 4 × 10 ¹² cm ^-2 . Thereafter, photoresist mask PR13 is removed.

As shown in FIG. 5F, a photoresist mask PR23 having an opening exposing the low voltage p-channel transistor P-LV is formed, and As ⁺ ion implantation 26 of the threshold adjustment n-type impurity is accelerated to 100 keV, the dose amount is 5 × 10 ¹² cm ^-2 . Thereafter, photoresist mask PR23 is removed.

In this manner, by six masks and seven ion implantations, well regions for three kinds of n-channel MOS transistors and three kinds of p-channel MOS transistors can be formed.

6A to 6D are diagrams for explaining the transistors formed in Figs. 5A to 5F.

6A schematically shows a planar configuration of a transistor. An insulating gate electrode is formed over the rectangular active region of width W. The current direction length (gate length) of the insulated gate electrode G is L. FIG.

6B is a table showing the characteristics of the various transistors formed. The low voltage n-channel MOS transistor N-LV has a ratio L / W of the gate length to the gate width W = 0.11 / 1 탆, and the threshold Vt is 0.2V. The n-channel high voltage high threshold MOS transistor (N-HV-HVt) has a L / W of 0.70 / 1 mu m and a threshold Vt of 0.6 V. The n-channel high voltage low threshold MOS transistor (N-HV-LVt) has an L / W ratio of 0.70 / 1 mu m and a threshold Vt of 0.2V.

The p-channel low voltage MOS transistor P-LV has an L / W of 0.11 / 1 탆 and a threshold Vt of -0.2V. The p-channel high voltage high threshold MOS transistor (P-HV-HVt) has an L / W ratio of 0.70 / 1 mu m and a threshold Vt of -0.6 V. The p-channel high voltage low threshold MOS transistor (P-HV-LVt) has an L / W ratio of 0.70 / 1 mu m and a threshold Vt of -0.2V.

6C shows the impurity concentration distribution in the n-channel MOS transistor region. The abscissa shows the depth from the substrate surface, and the ordinate shows the boron concentration. Curves N-LV, N-HV-HVt, and N-HV-LVt represent impurity concentration distributions in the n-channel low voltage transistor region, the n-channel high voltage high threshold transistor region, and the n-channel high voltage low threshold transistor region, respectively.

Ion implantation of the wells is common for the three types of transistor regions. The ion implantation in the channel stop region of approximately the same depth as the device isolation region is low in response to only one ion implantation in the n-channel high voltage low threshold transistor region and twice in the n-channel, high voltage high threshold transistor region and n-channel low voltage transistor region. High in response to ion implantation.

In the shallower region of the substrate, a high p-type concentration peak is formed corresponding to the threshold ion implantation in the low voltage transistor (N-LV) region.

6D is a graph showing impurity concentration distribution in the p-channel MOS transistor region. The horizontal axis represents depth from the substrate surface, and the vertical axis represents n-type impurity concentration. Curves P-LV, P-HV-HVt, and P-HV-LVt show impurity concentration distributions in the p-channel low voltage transistor, the p-channel high voltage high threshold transistor, and the p-channel high voltage low threshold transistor region, respectively. Ion implantation of the wells is common.

Ion implantation at a channel stop of approximately the same depth as the device isolation region is performed only in the high voltage high threshold transistor region and the low voltage transistor region to increase the impurity concentration at the left side of the peak. In the shallow region, the peak of the n-type impurity is formed in the low voltage transistor region by ion implantation for threshold adjustment.

Next, a 0.13 mu m logic process in which flash memory cells are mixed is described in more detail.

Fig. 7 lists 11 types of transistors integrated in this semiconductor device. Transistor FM represents a flash memory cell. The high voltage low threshold transistor (N-HV-LVt) is an n-channel MOS transistor having a high breakdown voltage and a low threshold. The high voltage high threshold transistor (N-HV-HVt) is an n-channel MOS transistor of high breakdown voltage high threshold. The high voltage low threshold transistor (P-HV-LVt) is a high breakdown voltage low threshold p-channel MOS transistor. The high voltage high threshold transistor (P-HV-HVt) is a high breakdown voltage high threshold p-channel MOS transistor.

The medium breakdown voltage transistor (N-MV) is an n-channel MOS transistor of, for example, 2.5V operation used for an input / output interface. The medium voltage transistor (P-MV) is a p-channel MOS transistor of, for example, 2.5V operation used for an input / output interface.

The low voltage high threshold transistor N-LV-HVt is a low breakdown voltage high threshold n-channel MOS transistor. The low voltage low threshold transistor N-LV-LVt is an n-channel MOS transistor having a low breakdown voltage low threshold. The low voltage high threshold transistor P-LV-HVt is a low breakdown voltage high threshold p-channel MOS transistor. The low voltage low threshold transistor (P-LV-LVt) is a low breakdown voltage low threshold p-channel MOS transistor.

The n-channel high voltage transistor and the flash memory cell are formed in the p-type well 14 in the n-type well 19. The n-channel transistor is formed in the p-type well 14, and the p-channel MOS transistor is formed in the n-type well 24. Channel stop regions 15 and 25 are formed in transistors other than the high breakdown voltage low threshold p-channel MOS transistor (P-HV-LVt).

In the low voltage high threshold transistors N-LV-HVt and P-LV-HVt, ion implantation 16 and 26 for threshold adjustment are formed. Threshold adjustment ion implants 37 and 38 are formed in the medium voltage transistors N-MV and P-MV. In the flash memory FM, an ion implantation 36 for adjusting the threshold is formed. The threshold injection ion implantation and the channel stop region cooperate to adjust the threshold of the transistor.

Hereinafter, the manufacturing process of manufacturing the semiconductor device shown in FIG. 7 is demonstrated.

As shown in Fig. 8A, the STI 12 is formed on the semiconductor substrate 11, and then the surface of the silicon substrate is thermally oxidized to form, for example, a silicon oxide film 13 having a thickness of 10 nm.

As shown in Fig. 8B, a photoresist mask PR14 exposing the flash memory cell FM and the high voltage n-channel MOS transistor (N-HV) region is formed to accelerate P ⁺ ions for n-type well formation. Ions are implanted with energy 2 MeV and dose 2 × 10 ¹³ cm ⁻² . Thereafter, resist mask PR14 is removed.

As shown in Fig. 8C, a photoresist mask PR11 having an opening exposing the flash memory FM and the n-channel MOS transistor region is formed, and B ⁺ ions for p-type well formation are accelerated to 400 keV, Ion implantation is carried out at a dose amount of 1.5 × 10 ¹³ cm ⁻² , and B ⁺ ions for channel stop region formation are implanted at an acceleration energy of 100 keV and a dose amount of 2 × 10 ¹² cm ⁻² . Thereafter, resist mask PR11 is removed. In this way, the p-type well 14 and the channel stop region 15 are formed.

As shown in Fig. 8D, a resist mask PR12 for exposing the n-channel MOS transistors excluding the flash memory FM and the high voltage low threshold n-channel transistor N-HV-LVt is formed, and a channel stop region is formed. Dragon B ⁺ ions are additionally implanted with an acceleration energy of 100 keV and a dose of 6 × 10 ¹² . The channel stop region 15x is formed with additional ion implantation. Thereafter, resist mask PR12 is removed.

As shown in Fig. 8E, a resist mask PR21 for exposing the p-channel MOS transistor is formed, and P ⁺ ions for forming the n-type well 24 are accelerated to 600 keV and the dose amount is 3.0 x 10 ¹³ cm- ^. Ion implanted at ² . Thereafter, resist mask PR21 is removed.

As shown in Fig. 8F, a resist mask PR22 for exposing the p-channel MOS transistors excluding the high voltage low threshold transistor is formed, and P ⁺ ions for forming the channel stop region 25 are accelerated to 240 keV and dose. Ion implantation at a quantity of 5.0 × 10 ¹² cm ⁻² . Thereafter, resist mask PR22 is removed.

As shown in Fig. 8G, a resist mask PR31 for exposing the flash memory cell FM is formed, and B ⁺ ions for forming the threshold adjustment region 36 are accelerated to 40 keV, the dose amount 6 x 10 ¹³ Ion implantation in cm ^-2 . Thereafter, resist mask PR31 is removed.

As shown in Fig. 8H, the silicon oxide film 13 on the surface of the semiconductor substrate is removed by HF solution. The silicon surface of the active region is then exposed.

As shown in Fig. 8I, the surface of the semiconductor substrate is thermally oxidized to grow a tunnel oxide film having a thickness of about 10 nm. An amorphous silicon film doped with phosphorus (P) having a thickness of about 90 nm on the tunnel oxide film is deposited by CVD and patterned into the shape of the floating gate 31. In addition, the amorphous silicon film is converted into a polysilicon film by subsequent heat treatment.

A silicon oxide film and a silicon nitride film are deposited by CVD at 5 nm and 10 nm, respectively, to cover the floating gate 31. The surface of the silicon nitride film is thermally oxidized by about 5 nm to a silicon oxide film having a thickness of about 10 nm, and the ONO film 32 having a thickness of about 20 nm is grown as a whole.

As shown in Fig. 8J, a resist mask PR32 exposing the medium voltage n-channel MOS transistor N-MV is formed, and B ⁺ ions forming the threshold adjustment region 37 are subjected to acceleration energy of 30 keV and dose. Ion implantation at a quantity of 5 × 10 ¹² cm ⁻² . Thereafter, resist mask PR32 is removed.

As shown in FIG. 8K, as ⁺ ions forming a resist mask PR33 exposing the medium voltage p-channel MOS transistor P-MV and forming the threshold adjustment region 38 are accelerated to 150 keV. And ion implantation at a dose of 3 × 10 ¹² cm ⁻² . Thereafter, resist mask PR33 is removed.

As shown in FIG. 8L, a resist mask PR13 for exposing the low voltage high threshold n-channel transistor (N-LV-HVt) region is formed, and B ⁺ ions for forming the threshold adjustment region 16 are accelerated energy 10 Ion is implanted by keV and dose amount 5 * 10 <^12> cm <^-2> . Thereafter, resist mask PR13 is removed.

As shown in Fig. 8M, As ⁺ ions forming the photoresist mask PR23 exposing the low voltage high threshold p-channel MOS transistor P-LV-HVt and forming the threshold adjustment region 26 are accelerated energy. Ion implantation is carried out at 100 keV and a dose of 5 x 10 ¹² cm ^-2 . Thereafter, resist mask PR23 is removed.

The low voltage transistor is also subjected to pocket implantation ion implantation using an extension forming mask. The threshold is also controlled by this condition. Here, although the threshold voltage control ion implantation is not performed in the low voltage low threshold transistor, it becomes a threshold value of about 0.1V by pocket implantation. Similarly, the threshold of the low voltage high threshold transistor is about 0.2V.

As shown in FIG. 8N, a resist mask PR34 covering the flash memory cell FM is formed, and the ONO film 32 in regions other than FM is removed. Thereafter, the resist mask PR34 is removed.

As shown in Fig. 8O, the surface of the substrate is thermally oxidized to form a silicon oxide film 41 having a thickness of 13 nm.

As shown in Fig. 8P, a resist mask PR41 covering the flash memory cell and the high voltage transistor is formed to remove the silicon oxide film 41 on the exposed region. Thereafter, resist mask PR41 is removed.

As shown in Fig. 8Q, a silicon oxide film 42 having a thickness of 4.5 nm, for example, is formed on the exposed substrate surface by a thermal oxidation method, and the thermal oxidation film 42 in the low voltage transistor region is formed using a resist mask PR42. Remove it.

As shown in Fig. 8R, a silicon oxide film 43 having a thickness of 2.2 nm, for example, is formed on the exposed substrate surface by a thermal oxidation method.

As shown in Fig. 8S, a polysilicon film having a thickness of 180 nm is formed by CVD on the substrate surface on which three types of gate insulating films are formed, and a silicon nitride film having a thickness of 30 nm is formed by plasma CVD thereon. The silicon nitride film functions as an antireflection film and can be used as an etching mask. The gate electrode 44F of the flash memory cell is patterned by photolithography and patterning.

As shown in Fig. 8T, the gate electrode side of the flash memory cell is thermally oxidized, and ion implantation of the source / drain regions is performed. An insulating film such as a silicon nitride film covering the gate electrode of the flash memory cell is formed by thermal CVD, and reactive ion etching (RIE) is performed to form the side wall spacers 46 of the silicon nitride film on the gate electrode side wall. The silicon nitride film on the polysilicon film is removed at the same time as the RIE. Thereafter, the gate electrode 44L is patterned for the transistor in the logic circuit region.

As shown in Fig. 8u, low-voltage p-channel form a resist mask (PR43) exposing a MOS transistor, and accelerate the B ⁺ ions for forming the extension of the source / drain energy 0.5 keV, a dose of 3.6 × 10 ¹⁴ cm ^- Ion implanted at ² . In addition, using the same mask, As ⁺ ions forming a pocket are ion implanted at an acceleration energy of 80 keV and a dose amount of 6.5 × 10 ¹² cm ⁻² in four directions of 28 degrees in the normal line.

An extension 47 with a pocket is formed. The extension and the pocket may be formed first. After that, the resist mask PR43 is removed.

9A and 9B, the pocket region forming process will be described in more detail. The resist mask PR43 has an opening in the low voltage transistor region. Impurity ions are implanted into the surface of the substrate from a normal angle tilt direction in the normal direction. In this way, the pocket area 47P is formed. The pocket region 47P is a reverse conductivity type region from the source / drain region.

As shown in FIG. 9B, ion implantation is performed along the substrate normal direction to form a conductive extension 47E such as a high concentration source / drain. The extension part K47E has a shape at least whose tip is surrounded by the pocket area 47P. By forming the pocket region of the reverse conductivity type, punch through is prevented and the threshold voltage of the transistor is also adjusted.

As shown in Fig. 8V, a resist mask PR44 for exposing the low voltage n-channel MOS transistor is formed, and ion implantation is performed in the low voltage n-channel MOS transistor region to form an extension region and a pocket region.

For example, to form an extension region, As ⁺ ions are implanted with an acceleration energy of 3 keV and a dose of 1.1 × 10 ¹⁵ cm ⁻² , and BF ₂ ⁺ ions are injected with an acceleration energy of 35 keV and a dose amount of 9.5 for pocket region formation. Ion implantation is carried out in 4 directions with 28 ° in the normal direction at 10 × 10 ¹² cm ⁻² . In this way, an extension 48 having a pocket area is formed. Thereafter, resist mask PR44 is removed.

As shown in Fig. 8w, medium-voltage p-channel MOS transistor (P-MV) for which the resist mask (PR45) to, and extension (49) BF ₂ ⁺ an acceleration energy of 10 keV, a dose of 7.0 to form a forming impression Ion implantation at x10 ¹³ cm ^-2 . After that, the resist mask PR45 is removed.

As shown in Fig. 8X, a resist mask PR46 exposing the medium voltage n-channel MOS transistor (N-MV) is formed, and P ⁺ ions for forming the extension 50 are accelerated to 10 keV and dose 3 Ion implantation at .0x10 <^13> cm <^-2> . Further, As ⁺ ions are implanted with an acceleration energy of 10 keV and a dose amount of 2.0 × 10 ¹³ cm ⁻² . As is further injected to increase the source drain current (Ids). P also has a function of increasing hot carrier resistance. With the exception of As ion implantation, parasitic resistance increases and Ids decreases by 10%. Thereafter, resist mask PR46 is removed.

Also, the high-voltage p-channel MOS transistor (P-HV), BF ₂ ⁺ ions at an acceleration energy of 80 keV, a dose amount to form a resist mask (PR47), and forms the extension section (51) for exposing, as shown in 8y Ion implantation at 4.5 x 10 ¹³ cm ^-2 . Thereafter, resist mask PR47 is removed.

As shown in Fig. 8Z, a resist mask PR48 for exposing the high voltage n-channel MOS transistor N-HV is formed, and P ⁺ ions for forming the extension 52 are accelerated to 35 keV and the dose amount is 4.0 x. 10 ¹³ cm ^-2 ion implantation. Thereafter, resist mask PR48 is removed.

As shown in Fig. 8za, a silicon oxide film is formed over the entire surface of the substrate and reactive ion etching is performed to form the sidewall spacers 54. A resist mask PR49 for exposing the n-channel MOS transistor is formed, and P ⁺ ions for forming the source / drain regions 55 are implanted with an acceleration energy of 10 keV and a dose amount of 6.0 x 10 ¹⁵ cm ^-2 . In addition, while the n-type source / drain region 55 is formed, the gate electrode is doped to n-type. Thereafter, resist mask PR49 is removed.

As shown in Fig. 8ZB, a resist mask PR50 for exposing the p-channel MOS transistor is formed, and B ⁺ ions for forming the source / drain region 56 are accelerated energy 5 keV, dose amount 4.0 x 10 ¹⁵ cm. Ion implanted at ^-2 . While the p-type source / drain region 56 is formed, the gate electrode is doped to the p-type. Thereafter, the resist mask PR50 is removed.

As shown in Fig. 8ZC, an interlayer insulating film 60 covering the gate electrode is formed, and a contact hole is formed. The conductive plug 61 filling the contact hole is formed, and the wiring 62 is formed on the surface. Thereafter, an insulating film and wirings are formed as necessary, and multilayer wirings are formed to complete a semiconductor device.

10A to 10J show a method of manufacturing a CMOS semiconductor device that can further reduce the number of processes.

As shown in Fig. 10A, a resist mask PR11 exposing the n-channel transistor region is formed, and B ⁺ ions forming the well region 14 are accelerated energy 400 keV, dose amount 1.5 x 10 ¹³ cm ^-2. Ion is implanted, and B ⁺ ions forming the channel stop region 15 are ion implanted at an acceleration energy of 100 keV and a dose of 8 x 10 ¹² cm ^-2 . Thereafter, resist mask PR11 is removed.

The dose amount 8 × 10 ¹² cm ⁻² is equal to the sum of the dose amounts of the two ion implantations in FIGS. 5A and 5B. Since the channel stop region is formed in all n-channel transistor regions with the same dose amount, the threshold value in the high voltage low threshold n-channel MOS transistor (N-HV-LVt) becomes larger than the desired value.

As shown in Fig. 10B, a resist mask PR21 exposing the p-channel MOS transistor region is formed, and P ⁺ ions forming the n-type well region 24 are accelerated with an energy of 600 keV and a dose amount of 3.0 x 10 ¹³ Ion implantation in cm ^-2 . Thereafter, resist mask PR21 is removed.

As shown in Fig. 10C, a resist mask PR22 for exposing the high voltage high threshold p-channel transistor P-HV-HVt and the low voltage p-channel transistor P-LV is formed, and the n-type channel stop region 25 is formed. ) the ions are implanted into the P ⁺ ion to form an acceleration energy of 240 keV, a dose of 5.0 × 10 ¹² cm ^-2. Thereafter, resist mask PR22 is removed.

As shown in Fig. 10D, a resist mask PR51 for exposing the low voltage and high voltage low threshold n-channel transistors N-LV and N-HV-LVt is formed, and B ⁺ for forming the threshold adjustment region 16 is formed. Ions are implanted with an acceleration energy of 10 keV and a dose of 2.5 × 10 ¹² cm ⁻² . This dose is, for example, less than the dose amount 4 × 10 ¹² cm ⁻² of the ion implantation of FIG. 5E. Thereafter, resist mask PR51 is removed.

As shown in Fig. 10E, a resist mask PR52 for exposing the high voltage low threshold n-channel transistor N-HV-LVt and the low voltage p-channel transistor P-LV is formed, and the threshold of the low voltage p-channel MOS transistor is formed. As ⁺ ions forming the adjustment region 26 are ion implanted at an acceleration energy of 100 keV and a dose of 5 x 10 ¹² cm ^-2 . This dose is equal to the dose of ion implantation in FIG. 5F.

In the high voltage low threshold n-channel transistor (N-HV-LVt), boron (B) and arsenic (As) are ion-implanted for the threshold adjustment, but the threshold is 0.2 V because the distribution is different. Thereafter, the resist mask PR52 is removed.

Thereafter, a gate insulating film having two kinds of thicknesses is grown according to a known method, and a gate electrode is formed thereon. In addition, in the low voltage n-channel transistor N-LV, the dose amount of the threshold adjustment region 16 is insufficient and the threshold value is lowered.

As shown in Fig. 10F, a resist mask PR23 exposing the low voltage p-channel transistor P-LV is formed, and an extension and pocket implantation are performed. The extension injects B ⁺ ions with an acceleration energy of 0.5 keV and a dose of 3.6 × 10 ¹⁴ cm ⁻² . The pocket injects As ⁺ ions in an acceleration energy of 80 keV and a dose amount of 6.5 × 10 ¹² cm ⁻² in four directions of 28 degrees in the normal direction. This ion implantation condition is the same as the ion implantation condition of FIG. 8U. Thereafter, resist mask PR23 is removed.

As shown in FIG. 10G, a resist mask PR13 exposing the low voltage n-channel transistor N-LV is formed, and As ⁺ ions are implanted with an acceleration energy of 3 keV and a dose amount of 1 × 10 ¹⁵ cm ⁻² . To form an extension. BF ₂ ⁺ ions are implanted from the 4 directions, which are energized by 28 degrees in the normal direction with an acceleration energy of 35 keV and a dose amount of 1.2 × 10 ¹³ cm ⁻² , to form pockets. The dose amount 1.2 × 10 ¹³ cm ⁻² of the pocket is larger than the dose amount 9.5 × 10 ¹² cm ⁻² of BF ₂ forming the pocket in the above-described embodiment FIG. 8V, and consequently has an effect of raising the threshold value. In this way, the threshold of the low voltage n-channel transistor is adjusted to an appropriate value. Thereafter, resist mask PR13 is removed.

As shown in Fig. 10H, a resist mask PR24 for exposing the high voltage p-channel transistor region is formed, and ion implantation for forming an extension is performed. For example, ion implantation of BF ₂ ⁺ ions at an acceleration energy of 80 keV, a dose of 4. 5 × 10 ¹³ cm _-2. It is the same condition as the ion implantation of FIG. 8Y. Thereafter, resist mask PR24 is removed.

As shown in Fig. 10I, a resist mask PR14 for exposing the high voltage n-channel MOS transistor is formed, and ion implantation for forming an extension is performed. For example, P ⁺ ions are implanted with an acceleration energy of 35 keV and a dose of 4.0 × 10 ¹³ cm ⁻² . It is the same condition as the ion implantation condition of FIG. 8Z. Thereafter, sidewall spacers are formed and ion implantation of a high concentration source / drain region is performed.

Fig. 10J schematically shows the configuration of the semiconductor device thus formed. In a transistor having a pocket, the threshold value can also be adjusted by the impurity concentration of the pocket.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto. For example, the acceleration energy, the dose, and the like of the impurities to be ion implanted can be changed depending on the design. Various insulators can be used as the hard mask layer. It will be apparent to those skilled in the art that various other changes, improvements, and combinations are possible.

INDUSTRIAL APPLICABILITY The present invention can be widely used for semiconductor devices in which a plurality of types of semiconductor circuits are mixed, such as a system on chip.

Claims (10)

A device isolation region formed to reach a first depth position from the surface of the semiconductor substrate; First and second wells of a first conductivity type formed in the semiconductor substrate; A first transistor formed in the first well and having a gate insulating film having a first thickness, a source / drain region of a second conductivity type opposite to the first conductivity type, and a gate electrode; And A second transistor formed in the second well and having a gate insulating film of a second thickness thinner than the first thickness, a source / drain region of a second conductivity type, and a gate electrode; The first well has a first impurity concentration distribution having a maximum at a depth position that is equal to or deeper than the first depth position, the second well has a first impurity concentration distribution equal to the first well, A semiconductor device which polymerizes an impurity concentration distribution having a maximum value at a second depth position that is shallower than the one depth position, and has a second impurity concentration distribution which exhibits a maximum value even at the second depth position as a whole. The method of claim 1, The first impurity concentration distribution may include a third impurity concentration distribution having a maximum at a depth position that is equal to or greater than the first depth position, and a fourth impurity concentration distribution having a maximum at a depth position equal to the first depth position. A semiconductor device which is polymerized. The method of claim 2, A third well of the first conductivity type formed in the semiconductor substrate; A third transistor formed in the third well and having a gate insulating film of the first thickness, a source / drain region of the second conductivity type, and a gate electrode; The third well is an impurity concentration distribution obtained by polymerizing a fifth impurity concentration distribution having a third impurity concentration distribution and a maximum value smaller than the maximum value of the fourth impurity concentration distribution at a depth position equal to the maximum value of the fourth impurity concentration distribution. A semiconductor device having a. The method of claim 1, Fourth and fifth wells of the second conductivity type formed in the semiconductor substrate; A fourth transistor formed in the fourth well and having a gate insulating film of the first thickness, a source / drain region of the first conductivity type, and a gate electrode; A fifth transistor formed in the fifth well and having a gate insulating film of the second thickness, a source / drain region of the first conductivity type, and a gate electrode; The fourth well has a sixth impurity concentration distribution having a maximum at a depth position equal to or deeper than the first depth position, And the fifth well has a sixth impurity concentration distribution identical to the fourth well and a seventh impurity concentration distribution obtained by polymerizing an impurity concentration distribution having a maximum at a depth shallower than the first depth position. The method of claim 4, wherein The sixth impurity concentration distribution may include an eighth impurity concentration distribution having a maximum at a depth position equal to or greater than the first depth position, and a ninth impurity concentration distribution having a maximum at a depth position equal to the first depth position. A semiconductor device which is polymerized. The method of claim 5, A sixth well of the second conductivity type formed in the semiconductor substrate; A sixth transistor formed in the sixth well and having a gate insulating film of the first thickness, a source / drain region of the first conductivity type, and a gate electrode; The sixth well is an impurity concentration distribution obtained by polymerizing the eighth impurity concentration distribution having a maximum value smaller than the maximum value of the ninth impurity concentration distribution at a depth position equal to that of the ninth impurity concentration distribution. A semiconductor device having a. (a) forming an isolation region in the semiconductor substrate from the surface to the first depth position; (b) forming first and second wells of a first conductivity type in the semiconductor substrate; (c) forming a gate insulating film of a first thickness on the surface of the first well and a gate insulating film of a second thickness thinner than the first thickness on the surface of the second well; (d) forming a gate electrode on the gate insulating film; And (e) forming a source / drain region in the semiconductor substrate on both sides of the gate electrode, The step (b), (b1) ion implanting a first impurity concentration distribution having a local maximum at a depth position equal to or greater than the first depth in common to the first and second wells; (b2) ion implanting a second impurity concentration distribution having a maximum value at a depth position equal to the first depth, selectively with respect to the first and second wells; And and (b3) ion implanting a third impurity concentration distribution having a maximum at a position shallower than the first depth only in the second well. The method of claim 7, wherein And said step (b2) comprises ion implanting said second impurity concentration distribution into said second well. The method of claim 7, wherein The step (b2), (b2-1) ion implanting impurity concentration distributions having maximum values into the first and second wells at a depth position equal to the first depth, (bl-2) A method of manufacturing a semiconductor device comprising the step of ion implanting an impurity concentration distribution having a maximum value at a depth position equal to the first depth position into the second well except the first well. The method of claim 7, wherein The step (b) further includes a step of forming a third well of the first conductivity type, and the step (c) includes forming a gate insulating film of the first thickness in the third well. (b1) is a step of ion implanting a first impurity concentration distribution into the third well, and the step (b2) is a step of ion implanting the second impurity concentration distribution into second and third wells Semiconductor device manufacturing method.

Images