KR100785781B1 - Single platform structure for packet and ethernet over synchronous digital hierarchySDH and frame format method of the same structure - Google Patents

Abstract

The present invention provides a single platform structure for EoS and POS and a frame format method of the platform structure that can configure POS technology and EoS technology as a single hardware platform, so that POS or EoS can be selected according to a user's needs. Its single platform architecture includes an SDH connection and an EoS and POS processor that can selectively handle Packet Over Synchronous Digital Hierarchy (SDH): POS or Ethernet over SDH: EoS. Processing unit; And a frame processing unit connected to the EoS and the POS processor and selectively processing a frame of the POS or the EoS. The single platform structure of the present invention has the advantage that the user can freely select either POS or EoS technology according to the network configuration of the backbone network as well as the access network.

Description

Single platform structure for packet and ethernet over synchronous digital hierarchy (SDH) and frame format method of the same structure}

1 is a structural diagram showing a single platform structure for EoS and POS according to an embodiment of the present invention.

2A and 2B are structural diagrams showing a line transfer and non-line transfer structures applicable to the EoS and POS processor of FIG. 1.

3A and 3B are block diagrams illustrating input / output frame formats in the EoS mode in the EoS / POS single platform structure of FIG. 1.

FIG. 4 is a block diagram illustrating an input / output frame format in a POS mode in the EoS / POS single platform structure of FIG. 1.

5 is a block diagram illustrating an input / output frame format in an EoS / RPR mode in a single platform structure according to another embodiment of the present invention.

<Description of main parts in the drawing>

100: SDH connection and processing unit 110: optical module

120: Transceiver 130: EoS and POS handler

132: SDH processing means 134: Selective processing means

134-1: EoS processing means 134-2: POS processing means

140: SDRAM 150: SPI 4.2

200: frame processing unit 210: ingress frame processor

210-1: Ingress Ethernet Frame Processor 210-2: Egress PPP Frame Processor

220: egress frame drooping

220-1: Egress Ethernet Frame Processor 220-2: Egress PPP Frame Processor

250: SPI 4.1 300: QoS control and Packet I / O processing unit

400: frame switch unit 500: local processor unit

600: CPU IF 700: CLK IF

The present invention relates to IP / Ethernet transmission technology, and more particularly, to a packet over SDH (POS) based device and an Ethernet over SDH (EoS) based device.

In the field of IP / Ethernet transmission technology, a method of delivering data packets includes data in the form of Point-to-Point (PPP) based on a high level Data Link Controller (HDL) in an SDH frame. POS encapsulation method and Asynchronous Transfer Mode (ATM) cell delivery in the form of ATM adaptation layer 5: (ATM5), or Synchronous Digital Hierarchy (SDH) ), Or to deliver Frame Relay (FR) / HDLC to the Plesiochronous Digital Hierarchy (PDH) format.

POS technology uses the above PPP over HDL between the Internet Protocol (IP) layer and SDH to build an Internet backbone network over an existing SDH transport network. It mainly uses 155Mbps or 2.5Gbps link.

EoS technology is also a technology that establishes the Internet backbone network on the SDH transmission network for the purpose of speeding up the leased line of enterprise subscribers on the access network side. Currently, 155Mbps or 622Mbps EoS technology is applied, and the backbone network has high speed of 2.5Gbps or more. EoS technology is being used.

Currently, it is possible to secure and easily manage the network's recovery capability, reliability, and the like, rather than delivering data packets directly to an Ethernet format such as Fast Ethernet (FE) or Gigabit Ethernet (GE). In order to have a scheme, packet transmission using the SDH transport network is preferred. Therefore, as described above, POS is currently used a lot for IP transmission between routers. However, a delivery method such as POS has an uneconomical problem in data transmission because the level of bandwidth to be controlled is large.

POS technology using SDH transmission path and EoS technology have been developed and applied with time difference, and POS technology has been applied to routers so far, and EoS technology has recently been standardized by the International Telecommunication Union (ITU-T). It is applied to new equipment (MSPP) such as multi-service provisioning platform (MSPP), and there is a movement to apply to pure packet equipment to take advantage of technology inherent.

These POS-based devices and EoS-based devices both have the economic advantages of utilizing the SDH transport base from the backbone network to the data packet transport network, and can provide excellent reliability using the SDH protection switching capability.

However, until now, since each platform platform is independent, there are many limitations in terms of economics and network construction. In the case of POS, there is a problem in that the control bandwidth level as described above is large. Therefore, there is an urgent need for a technology that can be selected and used according to a user's needs by configuring a POS technology and an EoS technology as a single hardware platform.

Accordingly, the technical problem to be achieved by the present invention is a single platform structure for EoS and POS that can select POS or EoS according to the user's needs by configuring POS technology and EoS technology that are currently applied separately as a single hardware platform. It is to provide a frame format method of the platform structure.

In order to achieve the above technical problem, the present invention provides an EoS and POS processor capable of selectively processing Packet Over Synchronous Digital Hierarchy (SDH) or Ethernet over SDH (EoS). SDH connection and processing unit comprising a; And a frame processing unit connected to the EoS and the POS processor and selectively processing the frame of the POS or the EoS.

According to the present invention, the single platform structure includes a Quality of Service (QoS) control and Packet I / O processing unit connected to the frame processing unit through a synchronous physical interface (SPI); And a frame switch unit connected to the QoS control and packet input / output processing unit, wherein each port of the frame switch unit is connected to the QoS control and packet input / output processing unit through eight ports and has 16 backplanes and 16 ports. Can be connected to.

The QoS control and packet input / output processing unit includes at least one of a packet receiving function, a switch output port determination, a QoS determination for a corresponding flow, a memory storage function of a packet, a packet scheduling function, and a packet forwarding function to the frame switch unit. Function can be performed.

Eight of the sixteen ports of the backplane may be connected to a Switch Fabric Card (SFC) in the shelf and the other eight may be connected to a flat cable for extended connection between the shelves.

In the present invention, the SDH connection and processing unit, an optical module that functions as an optical interface with an external optical fiber; And a transceiver configured to transmit and receive data between the optical module and the EoS and the POS processor. In addition, the EoS and POS processor, SDH processing means for processing a common part of the EoS and POS; And selection processing means having a POS processing means which is processing means in the POS mode and an EoS processing means which is processing means in the EoS mode.

The SDH processing means may sequentially perform SDH interval overhead processing, higher order pointer processing, time slot exchange (TSI), and path overhead processing, and the time slot exchange is performed by a 2: 1 selector. And a line transfer structure including a 1: 2 bridge or a non-line transfer structure not including the selector and the bridge.

The POS processing means performs Point-to-Point Protocol (PPP) processing based on High Level Data Link Controller (HDLC) and Contiguous Concatenation (CCAT), and the EoS Processing means includes a Generic Framing Procedure (GFP) for mapping the byte signal of the packet to the SDH; Virtual Concatenation (VCAT) for logically grouping physical SDH signals of a link for carrying traffic of Ethernet; And a Link Capacity Adjustment Scheme (LCAS) that dynamically limits the bandwidth in-band on the virtual chain structure. Meanwhile, the EoS processing unit may use synchronous dynamic RAM (SDRAM) for differential delay compensation of a virtual concatenated group (VCG).

The frame processing unit includes an ingress frame processor in a receiving direction and an egress frame processor in a transmitting direction, each of the ingress and egress frame processors includes a PPP frame processor and an Ethernet frame processor, The POS processing means may be connected to a PPP frame processor of each of the ingress and egress frame processors and the EoS processing means may be connected to the Ethernet frame processor of each of the ingress and egress frame processors.

The PPP frame processor or the Ethernet frame processor of the ingress frame processor is connected to the POS or EoS processing means via a first synchronous physical interface (SPI) and to the QoS control and packet I / O processing unit. It is connected via the second SPI to perform a mutual conversion function between interfaces.

The POS processor function is implemented in the POS of the channelized synchronous transmission method (STM-1c), and is connected to the SPI-4.2 standardized as the POS processing means and the standardized SPI- as the QoS control and packet I / O processing unit. When connected to 4.1, the POS frame processor may perform a virtual back pressure function for mapping from 64 logical ports on the SPI-4.2 to a logical port on the SPI-4.1.

When the Ethernet frame processor is connected to the standardized SPI-4.2 by the EoS processing means and the standardized SPI-4.1 to the QoS control and packet I / O processing unit, the Ethernet frame processor is connected to the EoS VCG channel on the SPI-4.2. PPP with a virtual back pressure to map from 64 logical ports to 4 logical ports on SPI-4.1, and a PPP head that can recognize Ethernet frames in QoS control and packet I / O processing A function of converting to a frame and removing a frame check sequence (FCS) on an Ethernet frame on the SPI-4.2 may be performed.

The PPP frame processor or the Ethernet frame processor of the egress frame processor may perform the function of the PPP frame processor or the Ethernet frame processor of the ingress frame processor in reverse.

According to another aspect of the present invention, there is provided a method of processing a frame using the single platform structure, the method comprising: selecting whether the POS mode or the EoS mode; Processing the frame by the EoS and the POS processor according to the selection; And processing a frame of the selected POS or EoS through a frame processor connected to the EoS and the POS processor.

In the present invention, the EoS and POS processor, SDH processing means for processing a common portion of the EoS and POS; And a processing means unit having a POS processing means which is a processing means in the POS mode and an EoS processing means which is a processing means in the EoS mode, wherein the SDH processing means includes SDH section overhead processing; Higher Order Pointer Processing, Time Slot Interchange (TSI), and Path Overhead Processing are sequentially performed, and the time slot exchange includes a 2: 1 selector and a 1: 2 bridge. It may be made of a non-line transfer structure that does not include the structure or the selector and the bridge.

When the mode is the POS mode and the input direction, the format of the frame input to the EoS and the POS processor is a form in which SDH and HDLD overhead are encapsulated in a PPP frame, and the SDH over the SDH processing means. Head off, the HDLC overhead is separated through the POS processing means and input to the PPP frame processor in the form of a PPP frame, and when the mode is the POS mode and the output direction, the PPP output from the PPP frame processor In the frame format, HDLC overhead is encapsulated through the POS processing means, and an HDLC frame formed through the SDH processing means is mapped to STM-16 and added with SDH overhead.

The HDLC frame structure includes address, control and protocol fields, and data packets, and a FCS that protects the entire frame and a flag indicating the end of the frame and the start of the next frame may be used.

When the mode is the EoS mode and the input direction, the format of the frame input to the EoS and POS processor is input in the form of encapsulation of SDH and GFP overhead in Ethernet and the SDH overhead through the SDH processing means. When the GFP is separated through the EoS processing means and input to the Ethernet frame processor in the form of an Ethernet frame, and the mode is the EoS mode and the output direction, the Ethernet frame format output from the Ethernet frame processor is The GFP is encapsulated through the EoS processing means, and the formed GFP frame is mapped to the STM-16 through the SDH processing means so that SDH overhead is added and output.

The GFP frame includes a data packet after the GFP header field, and protects the entire frame with an FCS, and the mode may be an Ethernet mode based on Multi-Protocol Level Switching (MPLS).

The mode is an EoS mode using Resilient Packet Ring (RPR), the single platform includes an RPR MAC processing unit for processing the packet ring of the RPR between the EoS and POS processor and the frame processing unit, When the signal is in the input direction, the format of the frame input to the EoS and POS processor is a form in which SDH and GFP overhead are encapsulated in a frame in which an RPR MAC is added to an Ethernet frame, and through the SDH processing means. The overhead is separated, the GFP is separated through the EoS processing means and input to the RPR MAC processing unit, the RPR related protocol is processed through the RPR MAC processing unit and the RPR MAC is removed, and the Ethernet frame is in the form of an Ethernet frame. Ethernet inputted to the processor and in the case of the EoS mode and the output direction, the Ethernet outputted from the Ethernet frame processor In the frame format, after the RPR related protocol is processed and the RPR MAC is added while the RPR MAC processing unit is processed, the GFP is encapsulated through the EoS processing unit, and the GFP frame formed through the SDH processing unit is transferred to the STM-16. It can be mapped and outputted with the SDH overhead added.

The single platform structure and frame format method for EoS and POS of the present invention can be utilized not only for access network but also for backbone network transmission technology, and provide advantages of freely selecting POS or EoS according to the mode required for the device. do.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention; In the following drawings, each component is exaggerated or schematically represented for convenience and clarity of description, and parts irrelevant to the description are omitted. Like numbers refer to like elements in the figures. On the other hand, the terms used are used only for the purpose of illustrating the present invention and are not used to limit the scope of the invention described in the meaning or claims.

Currently, EoS technology, a new method for efficiently delivering data packets using Ethernet standardized in ITU-T, is being proposed. While EoS technology can utilize existing SDH network as it is, the core technology of EoS, ie, Generic Framing Procedure (GFP) that maps byte signal of packet to SDH, and physical SDH of link to deliver traffic of Ethernet Virtual Concatenation (VCAT) for logically grouping signals, and Link Capacity Adjustment Scheme (LCAS) for dynamically confining bandwidth on the virtual chain in-band. Can be used to adjust the effective bandwidth level. Hereinafter, a single platform structure for EoS and POS that can use such EoS with a conventional POS will be described.

1 is a structural diagram showing a single platform structure for EoS and POS (POS / EoS) according to an embodiment of the present invention.

POS / EoS single platform structure of the present invention is the SDH access and processing unit 100, the frame processing unit 200, Quality of Service (QoS) control and packet I / O processing unit 300 and frame The switch unit 400 is included.

The SDH connection and processing unit 100 includes an optical module 110, a transceiver 120, and an EoS and POS (Eos / POS) processor 130, wherein four 2.5 Gbps optical modules 110 are single-mode optical fibers (Single). It is connected to Mode Fiber and functions as an external and optical interface. In terms of the optical reception direction, the 2.5G transceiver 120 reproduces a clock from the optical reception data, recovers data corresponding to the clock, and transmits the clock to the Eos / POS processor 130.

The EoS / POS processor 130 internally includes an SDH processing means 132 and a selection processing means 134, and the selection processing means 134 includes a POS processing means and an EoS processing means, in the case of an EoS processing means. It is connected to the synchronous dynamic RAM (SDRAM). The SDH processing unit 132 performs the frame processing of the common part of both the EoS and the POS. As can be seen from the description of FIG. 2 below, the SDH section overhead processing, the high point pointer (HO) processing, and the time slot exchange are performed. (Time Slot Interchange (TSI)), a path overhead processing function, and the like, and select different paths according to the selection of the POS function and the EoS function, and are connected to the selection processing means 134.

The frame processing unit 200 includes an ingress frame processor 210 in a reception direction and an egress frame processor 220 in a transmission direction, each of which has an internal and ingress frame processor 210 and 220. It includes a PPP frame processor and an Ethernet frame processor. The PPP frame processor is connected to the POS processing means of the selection processing means 134, and the Ethernet frame processor is connected to the EoS processing means of the selection processing means 134.

The QoS control and Packet I / O processing unit 300 is connected to the frame processing unit 200 and also to the frame switch unit 400, which is a switch fabric card in the shelves. Fabric Card (SFC) or flat cable for extended connection between shelves.

For reference, the frame processing unit 200 is connected to the selection processing unit 134 and the QoS control and Packet I / O processing unit 300 through a synchronous physical interface (SPI), which is selected in this embodiment. The means 134 is connected to the standardized SPI-4.2 150, and the QoS control and Packet I / O processing unit 300 is connected to the standardized SPI-4.1 250. Meanwhile, each port of the frame switch unit 400 is connected to eight ports of the QoS control and Packet I / O processing unit 300, and is connected to the backplane by 16 ports. Of the 16 connection ports, ports 5-12 are connected to the SFCs in the shelves, and ports 1-4 and ports 13-16 are connected to flat cables for expansion connections between the shelves.

The QoS control and packet I / O processing unit 300 includes a packet reception function, a switch output port determination and a QoS determination function for a corresponding flow, a memory storage function of a packet, a packet scheduling function, and a frame through the SPI-4.1 250. The switch unit 400 performs a packet transmission function.

Meanwhile, in order to facilitate operation and operation of the POS / EoS single platform structure of the present invention, a clock interface 700 (CLK IF), in which the POS / EoS single platform structure provides a clock to each function unit, controls each function unit. Of course, the local processor 500, and the CPU interface 600 to perform the function is included.

The following briefly describes how the EoS / POS single platform structure performs functions in each of the POS mode or the EoS mode.

First, in terms of receiving, when the POS mode is selected, the POS processing unit of the selection processing unit 134 performs the PPP / HDLC / CCAT function and is connected to the PPP frame processor of the ingress frame processor 210. As described above, the PPP frame processor is connected to the POS processing unit by SPI-4.2 (150), and the QoS control and packet I / O processing unit 300 by SPI-4.1 (250), thereby providing these interfaces 150,250. ) Performs a mutual conversion function. On the other hand, when the function of the POS processing means is implemented as a POS of channelized synchronous transmission method (channelized STM-1c), it maps from 64 logical ports on SPI-4.2 (150) to 4 logical ports on SPI-4.1 (250). It can provide a virtual back pressure (Virtual Back Pressure) function. Here, 'c' of STM-1c is an initial of 'concatenation'.

When selecting the EoS function, SDRAM 140 is used for differential delay compensation of the Virtual Concatenated Group (VCG) (not used in POS mode), and the output after performing the GFP / VCAT / LCAS function The Ethernet frame processor of the ingress frame processor 210 is connected. The Ethernet frame processor is connected to the EoS processor and the SPI-4.2 (150), and the QoS control and packet I / O processing unit (300) is connected to the SPI-4.1 (250), thereby converting the mutual conversion function between these interfaces (150, 250). To perform. In addition, the virtual backpressure function for mapping from the EoS VCG channel 64 logical port on the SPI-4.2 (150) to the four logical ports on the SPI-4.1 (250), QoS control and packet I / O processing unit 300 to the ingress Ethernet frame Converts to a PPP frame having a PPP head that can be recognized by the CPC), and removes a frame check sequence (FCS) on an ingress Ethernet frame on the SPI-4.2 150.

Each of the EoS or POS mode frames that have passed through the frame processor 200 performs the above-described functions in the QoS control and packet I / O processor 300 and the frame switch unit 400.

In terms of transmitting, the QoS control and packet I / O processing unit 300 receives the data from the frame switch unit 400, the lookup function of the switch fabric routing information, the packet reassembly function, the packet memory storage function, and the packet. A scheduling function and a packet transmission function are performed to the egress frame processor 220 through the SPI-4.1 250.

When the POS function is selected, the egress PPP frame processor converts SPI-4.1 (250) to SPI-4.2 (150) of the POS processing means. It also performs a back pressure processing function for generating flow control. The POS processing means wraps the PPP frame into an HDLC frame and places it in an STM-16 payload, and the SDH processing means 132 generates a path overhead and a section overhead, and finally, the transceiver 120 and A function of optically transmitting with the outside through the 2.5Gbps optical module 110 is performed.

When the EoS function is selected, the egress Ethernet frame processor converts SPI-4.1 (250) to SPI-4.2 (150) of the EoS processing means. And a layer 2 level header processing function and a function of adding an FCS on an egress Ethernet frame on the SPI-4.2 (150). The EoS processor packs the Ethernet frame into a GFP frame and loads it into the STM-16 payload, and then the functions of the SDH processor 132, the transceiver 120, and the 2.5Gbps optical module 110 are in the POS mode. Same as in

Figures 2a and 2b is a structural diagram showing the line transfer and non-line transfer structure that can be applied to the EoS and POS processor of Figure 1, Figure 2a shows a line transfer structure, Figure 2b shows a non-line transfer structure.

POS / EoS single platform structure of the present embodiment has a structure that accommodates 2.5G x 4 optical links to accommodate the 2.5H x 4 capacity SDH connection and processing unit 100. The POS structure applied in the existing routers often has a non-line transfer structure, but in EoS, it should basically have a line transfer structure. Therefore, the POS / EoS single platform structure of the present invention should have a line transfer structure and a non-line transfer structure to the SDH connection and processing unit 100.

In the track switching structure of FIG. 2A, the SDH processing unit 132 receives the 2.5G x 4 signals to perform the section overhead processing and the higher-order pointer processing, respectively, and selects the operation and the selection of the preliminary line through time slot mapping. At this time, the signal is processed as much as 2.5G x 2 signal capacity. Meanwhile, the TSI includes a 2: 1 selector and a 1: 2 bridge for the line transfer structure.

In the non-line transfer structure of FIG. 2B, the 2.5H x 4 signals are accommodated, and the SDH processing unit 132 receives a total of 2.5G x 4 signal capacities through section overhead processing, higher order pointer processing, and timeslot mapping. The signal is processed without switching.

On the other hand, the frame passing through the SDH processing means 132 is input to the POS processing means 134-1 or the EoS processing means 134-2 of the selection processing means 134 according to the POS mode or the EoS mode selection.

3A and 3B are block diagrams illustrating an input / output frame format in an EoS mode in the EoS / POS single platform structure of FIG. 1, and an EoS processor portion of the Eos / POS processor 130 (hereinafter, referred to as an 'EoS processor 130'). And a frame format input / output around the frame processing unit 200.

Frame formats processed by the EoS processor 130 are classified into two types. One is a pure Ethernet frame, and the other is the Ethernet over MPLS format. Here, MPLS means multi-protocol level switching. 3A shows the format of a pure Ethernet frame, and FIG. 3B shows the format of Ethernet over MPLS.

Referring to FIG. 3A, first, in the reception direction, a format input to the EoS processor 130 is input in a form in which SDH and GFP overhead are encapsulated in a pure Ethernet frame. While passing through the EoS processor 130, the SDH overhead is deviated from the SDH processing unit 132 and the GFP overhead is deviated from the EoS processing unit 134-1, so that the Ethernet of the ingress frame processor 210 in the form of a pure Ethernet frame. It is output to the frame processor 210-1.

Looking at the transmission direction, the EoS processing unit 134-1 encapsulates the GFP using the Ethernet frame format output from the Ethernet frame processor 220-1 of the egress frame processor 220 as an input. GFP frames contain data packets after the GFP header field and protect the entire frame with a 32-bit FCS. The formed GFP frame is mapped to the STM-16 frame through the SDH processing unit 132, and the SDH overhead is added and output.

In the case of the format of Ethernet over MPLS of FIG. 3B, only the frame structure is different, and it can be seen that the input / output frame format is performed through the same process as that of FIG. 3A.

FIG. 4 is a block diagram illustrating an input / output frame format in the POS mode in the EoS / POS single platform structure of FIG. 1. The POS processor portion of the Eos / POS processor 130 is hereinafter referred to as a 'POS processor 130'. ) And a frame format input and output around the frame processing unit 200.

Referring to FIG. 4, first, in the reception direction, a format input to the POS processor 130 is input in a form in which SDH and HDLC overhead are encapsulated in a PPP frame. While passing through the POS processor 130, the SDH overhead is deviated from the SDH processing unit 132, and the HDLC overhead is deviated from the POS processing unit 134-2, so that the PPP of the ingress frame processor 210 is in the form of a pure PPP frame. It is output to the frame processor 210-2.

As seen from the transmission direction, the HD processing is encapsulated by the POS processing unit 134-2 using the PPP frame format output from the PPP frame processor 220-2 of the egress frame processor 220 as an input. HDLC frames contain data packets following the address, control / protocol fields and protect the entire frame with a 32-bit FCS, and a flag 7E is used between frames to indicate the end of the frame and the beginning of the next frame. The formed HDLC frame is mapped to the STM-16 frame through the SDH processing unit 132 and the SDH overhead is added and output.

5 is a block diagram illustrating an input / output frame format in an EoS / RPR mode in a single platform structure according to another embodiment of the present invention.

The single platform structure of this embodiment is a structure for EoS mode using Resilient Packet Ring (RPR) technology, and an RPR MAC for processing an RPR between the Eos / POS processor 130 and the frame processor 200. It includes a processing unit 800. The RPR technique is a technique applied when configuring a packet ring, and a frame further includes a MAC field for configuring an RPR. Thus, similar to FIG. 3A or 3B, the frame formats that can be processed by the EoS processor 130 are the Ethernet frame plus the RPR MAC and the Ethernet over MPLS format.

Referring to FIG. 5, in the receiving direction, a format input to the EoS processor 130 is input in a form in which SDH and GFP overhead are encapsulated in a frame in which an RPR MAC is added to an Ethernet frame. While passing through the EoS processor 130, the SDH and GFP overheads are separated and applied to the RPR MAC processor 800 in the form of an Ethernet frame in which an RPR MAC is added. The RPR MAC processing unit 800 processes the RPR related protocol and removes the RPR MAC, and then outputs the Ethernet frame to the Ethernet frame processor 210-2 of the ingress frame processor 210.

In the transmission direction, the Ethernet frame format output from the egress Ethernet frame processor 220-2 is used as an input, and the RPR MAC processing unit 800 processes an RPR related protocol, adds an RPR MAC, and then EoS the RPR MAC frame. Output to the processor 130. The EoS processor 130 encapsulates the RPR MAC frame with the GFP, and the formed GFP frame is mapped to the STM-16 frame, and the SDH overhead is added and output.

According to the EoS / POS single platform structure of the present invention, the POS technology and the EoS technology, which are applied separately, are configured as a single hardware platform, so that a user can freely select either POS or EoS technology according to the network configuration of the backbone network as well as the access network. Can have advantages. In addition, there is a sufficient possibility to be applied to the Packet over WDM technology, which is a part of the recently emerging IP over Fiber technology, has the advantage that it can be easily applied to high-capacity system environment.

So far, the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. will be. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described in detail above, the EoS / POS single platform structure of the present invention comprises a POS hardware and an EoS technology, which are applied separately, as a single hardware platform, so that a user may not have a POS or EoS technology has the advantage of freely choosing one.

In addition, the present invention can be applied to Packet over WDM technology, which is a part of IP over Fiber technology, which is recently emerging, and can be easily applied to a high capacity system environment.

Claims (23)

An SDH connection and processing unit including an EoS and a POS processor capable of selectively processing Packet Over Synchronous Digital Hierarchy (POS) or Ethernet over SDH (EoS); And A frame processing unit connected to the EoS and the POS processor and selectively processing a frame of the POS or the EoS; A Quality of Service (QoS) control and Packet I / O processing unit connected to the frame processing unit through a synchronous physical interface (SPI); And And a frame switch unit coupled to the QoS control and packet input / output processing unit. According to claim 1, Each port of the frame switch unit is connected to the QoS control and packet input / output processing unit by eight ports, and is connected to a backplane (16) ports by a single platform structure for EoS and POS. According to claim 1, The QoS control and packet input and output processing unit, EoS performing a processing function including at least one of a packet reception function, a switch output port determination, a QoS determination for a corresponding flow, a memory storage function of a packet, a packet scheduling function, and a packet forwarding function to the frame switch unit. And single platform architecture for POS. The method of claim 2, EoS and POS are characterized in that eight of the 16 ports on the backplane are connected to a Switch Fabric Card (SFC) in the shelf and the other eight are connected to a flat cable for extended connection between the shelves. Single platform architecture. According to claim 1, The SDH connection and processing unit, An optical module functioning as an optical interface with an external optical fiber; And And a transceiver for transmitting and receiving data between the optical module and the EoS and the POS processor. According to claim 1, The EoS and POS processor, SDH processing means for processing a common part of the EoS and POS; And And a selection processing means having a processing means for processing in the POS mode and an processing means for processing in the EoS mode. The method of claim 6, Wherein said SDH processing means sequentially performs SDH interval overhead processing, higher order pointer processing, time slot exchange (TSI), and path overhead processing. The method of claim 7, wherein The timeslot exchange is performed through a line switching structure including a 2: 1 selector and a 1: 2 bridge, or through a non-line switching structure including no selector and a bridge. Single platform structure for. The method of claim 6, The POS processing means performs Point-to-Point Protocol (PPP) processing based on High Level Data Link Controller (HDLC) and Contiguous Concatenation (CCAT). The EoS processing means, Generic Framing Procedure (GFP) for mapping the byte signal of the packet to SDH; Virtual Concatenation (VCAT) for logically grouping physical SDH signals of a link for carrying traffic of Ethernet; And A single platform for EoS and POS, characterized in that the protocol processing by utilizing the virtual chain structure in the in-band (Link Capacity Adjustment Scheme (LCAS)) to dynamically limit the bandwidth; rescue. The method of claim 9, The EoS processing unit is a single platform structure for EoS and POS, characterized in that the use of Synchronous Dynamic RAM (SDRAM) for the differential delay compensation of the Virtual Concatenated Group (VCG). The method of claim 6, The frame processing unit includes an ingress frame processor in a receiving direction and an egress frame processor in a transmitting direction, Each of the ingress and egress frame processors includes a PPP frame processor and an Ethernet frame processor. The POS processing means is connected to the PPP frame processor of each of the ingress and egress frame processors and the EoS processing means is connected to the Ethernet frame processor of each of the ingress and egress frame processors. Single platform architecture. The method of claim 11, wherein The PPP frame processor or the Ethernet frame processor of the ingress frame processor, The POS or EoS processing means is connected through a first Synchronous Physical Interface (SPI) and the QoS control and packet I / O processing unit is connected through a second SPI to perform a mutual conversion function between interfaces. Platform architecture for EoS and POS. The method of claim 12, The PPP frame processor function is implemented as a POS of a channelized synchronous transmission method (STM-1c), and is connected to the SPI-4.2 standardized as the POS processing means and a standardized SPI to the QoS control and packet I / O processing unit. If connected with -4.1, And the PPP frame processor performs a virtual back pressure function for mapping from 64 logical ports on the SPI-4.2 to a logical port on the SPI-4.1. The method of claim 12, The Ethernet frame processor, When the EoS processing means is connected to the standardized SPI-4.2 and the QoS control and packet I / O processing unit is connected to the standardized SPI-4.1, from the 64 logical ports of the EoS VCG channel on the SPI-4.2 Performs a virtual back pressure function to map to four logical ports on the SPI-4.1, Converts Ethernet frames into PPP frames with PPP heads that are recognizable by the QoS control and packet I / O processing units and removes a Frame Check Sequence (FCS) from the Ethernet frames on SPI-4.2 A single platform architecture for EoS and POS. The method according to claim 13 or 14, The PPP frame processor or the Ethernet frame processor of the egress frame processor, Single platform architecture for EoS and POS, characterized in that it performs the function of the PPP frame processor or Ethernet frame processor of the ingress frame processor in reverse. A method of processing a frame using the single platform structure of claim 1, comprising: Selecting whether the POS mode or the EoS mode; Processing the frame by the EoS and the POS processor according to the selection; And Processing a frame of the selected POS or EoS through a frame processing unit connected to the EoS and the POS processor. The method of claim 16, The EoS and POS processor, SDH processing means for processing a common portion of the EoS and POS; And And a selection processing means having a POS processing means which is processing means in the POS mode and an EoS processing means which is processing means in the EoS mode. The SDH processing means sequentially performs SDH interval overhead processing, higher order pointer processing, time slot exchange (TSI), and path overhead processing, The time slot exchange may be performed through a line transfer structure including a 2: 1 selector and a 1: 2 bridge, or through a non-line transfer structure including no selector and a bridge. How to format a frame. The method of claim 17, When the mode is the POS mode and the input direction The format of the frame input to the EoS and POS processor is a form in which SDH and HDLD overhead are encapsulated in a PPP frame, the SDH overhead is deviated through the SDH processing means, and the HDLC over the POS processing means. The head is separated and input to the PPP frame processor of the frame processor in the form of a PPP frame, When the mode is the POS mode and the output direction In the PPP frame format output from the PPP frame processor, HDLC overhead is encapsulated through the POS processing means, and SDH overhead extracted by mapping the HDLC overhead frame to STM-16 through the SDH processing means Frame format method of a single platform structure, characterized in that the addition and output. The method of claim 18, The HDLC overhead frame structure includes address, control and protocol fields, and data packets, A frame format method of a single platform structure, characterized in that an FCS for protecting an entire frame and a flag indicating an end of a frame and a start of a next frame are used. The method of claim 17, If the mode is EoS mode and the input direction, The format of a frame input to the EoS and POS processor is input in the form of encapsulation of SDH and GFP overhead on Ethernet, and the SDH overhead is deviated through the SDH processing means, and the GFP is transmitted through the EoS processing means. Departure is input to the Ethernet frame processor of the frame processor in the form of an Ethernet frame, When the mode is the EoS mode and the output direction In the Ethernet frame format output from the Ethernet frame processor, GFP overhead is encapsulated through the EoS processing means, and SDH overhead extracted by mapping the GFP overhead frame to STM-16 through the SDH processing means is obtained. Frame format method of a single platform structure, characterized in that the addition and output. The method of claim 20, The GFP overhead frame structure includes a data packet after a GFP header field, and protects the entire frame with the FCS. The method of claim 20, The method of claim 1, wherein the mode is a multi-protocol level switching (MPLS) based Ethernet mode. The method of claim 17, The mode is an EoS mode using Resilient Packet Ring (RPR), the single platform includes an RPR MAC processing unit for processing the RPR between the EoS and POS processor and the frame processing unit, When the mode is the Eos mode and the input direction, The format of a frame input to the EoS and POS processor is a form in which SDH and GFP overhead are encapsulated in a frame in which an RPR MAC is added to an Ethernet frame, and the SDH overhead is separated through the SDH processing means, and the EoS GFP is separated through the processing means and input to the RPR MAC processing unit, an RPR related protocol is processed while the RPR MAC processing unit is removed, and an RPR MAC is removed, and then is input to the Ethernet frame processor in the form of an Ethernet frame. When the mode is the EoS mode and the output direction The Ethernet frame format outputted from the Ethernet frame processor is processed through the RPR MAC processing unit, the RPR related protocol is processed, and after the RPR MAC is added, the EFP is encapsulated by the GFP through the SDH processing means. The formed GFP frame is mapped to the STM-16, SDH overhead is added to the frame format method characterized in that the output.

Images