KR100785288B1 - PBUS stabilization circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PBUS stabilization circuit for preventing long asserts in which a chip is broken and occupies a bus for a long time during data communication between processors. The present invention relates to a frame synchronization signal and a reference clock signal output from a bus master. In a switch of a fibus structure which is input through a driving unit, and is implemented as a buses control unit for outputting an assert signal, a bit rate clock signal, and a data signal through the driving unit, a pull-up resistor is provided at an output terminal of an assert (AST) pin of the buses control unit. Unexpected device itself is composed of a long assert timeout generator that connects a pull-up and generates a timeout exceeding an allowable occupancy time of an assert signal at an assert pin output terminal of the Bus occupancy signal AST is not occupied by the bus even if active low Not because it is handled not have any effect on the other processor has the effect that the system is operating stably.

 PBUS, Bus, Fibus, Occupation, Assert

Description

PBUS stabilization circuit

1 is a block diagram of signal processing between processors of a general SDX-100S exchanger PBUS;

FIG. 2 is a circuit diagram of a PCB pattern of a conventional bus controller. FIG.

3 is a circuit diagram of a PCB pattern of the bus controller for PBUS stabilization according to the present invention.

Explanation of symbols on the main parts of the drawings

20: PBUS control unit R1: pullup resistor

21: FRS, ASTCLK driver R: register

22: AST, BRCLK, DATA drive part C: counter

30: Long assert timeout generator INV1, INV2: Inverter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the stabilization of a peripheral bus (PBUS) in an interprocessor communication (IPC) communication type exchange, and in particular, a PBUS for preventing a long assertion in which a chip is broken for a long time due to various reasons during data communication between processors. It relates to a stabilization circuit.

The IPC communication system uses a multi-drop connection between a master processor and a slave processor to communicate by occupying a round robin PBUS by mutual arbitration. Is done in a way,

The signal configuration of PBUS is based on the frame synchronization signal (FRame Synchronous: FRS) output from the bus master (1) and the assert clock (ASserT CLocK: ASTCLK) that generates the reference clock required for the processor operation and the frame synchronization signal. When it comes to the order (ASserT) which is a signal to occupy the data bus, the bit rate clock (Bit rate CLocK: BRCLK) indicating the bit rate of the data to be transmitted and the data (DATA).

The data processing of a general PBUS structure will be described in more detail with reference to FIG. 1 as follows.

When the message is sent from the processor 1 (3) to the processor 2 (4), the bus master (1) board outputs the frame sync signal (FRS) and the assert clock (ASTCLK), and the processor 1 (3) becomes the source. If PBUS (2) is available when it is ordered by the robin method, it asserts the occupancy signal to active low and only the processor whose header of the message matches its ID continues to receive the message. It is made to structure.

In general, when implementing a PBUS controller, when there is a lot of traffic, it is necessary to minimize unnecessary occupancy time to improve data transmission speed. In this case, the PBUS occupancy time of the AST signal may be an important factor. However, bus occupancy and release control of the AST signal will be more important.

As described above, the AST signal is generally connected to a printed circuit board (PCB) pattern directly on a back plane as shown in FIG. 2 for communication with various processors.

In this case, if the device in which the PBUS controller is implemented is damaged, there is a high possibility that the AST signal may malfunction. In other words, if the chip is damaged due to lightning or unstable power supply voltage, the AST signal will remain in the long assert state that continues to occupy the PBUS, causing data collisions on the PBUS or other processors stuck in the P-BUS. There is a problem.

Therefore, an object of the present invention is to provide a PBUS stabilization circuit for implementing a stable system that does not affect other processors by preventing the AST signal from long asserting the PBUS even if the device in which the PBUS controller is implemented is damaged.

As a technical means for achieving the above object, the present invention receives a frame synchronizing signal and a reference clock signal output from the bus master through the driver, and a bus that outputs the assert signal, the bit rate clock signal and the data signal through the driver In an exchanger having a fibus structure implemented as a control unit, a pull-up resistor is connected to an output terminal of an assert (AST) pin of the fibus control unit, and an allowable occupation of an assert signal is applied to an output (asser) pin output terminal of the fibus control unit. A long assert time out generating unit for generating a time out exceeding time is featured.

In this case, the long assert timeout generating unit includes a system clock or a separate reference clock generating unit serving as a reference clock, a counter operating from the time when the assert pin is activated low, an inverter for inverting the low signal of the assert pin; And a register for adjusting the frequency division by outputting the output signals of the inverter and the counter, and an inverter for inverting and outputting the signal of the register.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A circuit related to the PBV controller PCB pattern for implementing PBV stabilization according to an exemplary embodiment of the present invention is illustrated in FIG. 3.

Referring to FIG. 3, the circuit according to the present invention includes an FRS and ASTCLK driver 21 for inputting a frame synchronization signal FRS and a reference clock signal ASTCLK output from the bus master 1; Receives the signals input from the FRS and ASTCLK driver 21, determines whether the bus occupies their own order, and outputs a signal corresponding thereto, that is, an assert signal AST, a bit rate clock signal BRCLK, and a PBUS for outputting a data signal DATA. Control unit 20; An AST, BRCLK, and DATA driver 22 for processing signals for AST, BRCLK, and DATA output from the PBUS controller 20; A pull-up resistor R1 connected to an output terminal of an assert pin of the PBUS control unit 20 in case of an AST low by opening an AST pin; In order to generate a time-out exceeding the allowable occupancy time of the assert signal at the assert pin output terminal of the PBUS controller 20 in case of an AST low due to a short circuit of the AST pin. It consists of a long assert time out generator 30 provided.

The long assert timeout generator 30 operates from the time when the reference clock generator REF_CLK serving as the reference clock and the assert pin are low, and is cleared on the other terminal of the pull-up resistor R1. The counter C connected to the (CLR) stage, the inverter INV1 for inverting the low signal of the assert pin, and the output signal of the inverter INV1 are inputted to the clear (CLR) stage, and the counter C Register R is inputted to the clock CLK stage to adjust and divide the output signal, and an inverter for inverting the signal of the register R and outputting the signal to the AST, BRCLK, and DATA driver 22. INV2).

The reference clock generator REF_CLK may be used instead of a clock in the system itself.

At this time, the timeout allowance time is shown in Equation 1.

Referring to the operation of the present invention configured as described above in more detail.

First, the case where the AST is low due to the opening of the AST pin will be described.

In this case, even if the AST pin is opened, since a predetermined current is applied to the AST, BRCLK, and DATA driver 22 by the pull-up resistor R1, the low is prevented.

On the other hand, when the AST pin is shorted and the AST becomes low, the high signal is first applied to the clear (CLR) terminal of the counter C to operate the counter. The inverter INV1 also inverts the high signal to a low signal and outputs the low signal.

The low signal is inverted high in front of the clear (CLR) end of the register (R) so that the register (R) is operated. At this time, the output signal of the counter (C) is received and adjusted according to the frequency division, and then the AST through the inverter (INV2). The low signal is output to the BRCLK and the DATA driver 22, thereby forcibly inverting the PBUS occupancy, that is, the AST signal.

Therefore, the bus occupancy (AST) becomes high in the AST, BRCLK, and DATA driver 22 in both low states due to the opening and shorting of the AST pin, so that the bus is not continuously occupied and thus does not affect other processors.

The present invention is not limited to the above-described specific preferred embodiments, and various modifications can be made by those skilled in the art without departing from the gist of the present invention described in the claims. Of course, such a change is of course within the scope of the present invention.

As described above, according to the present invention, even when the bus occupancy signal AST is activated low due to an unexpected fault of the device itself (lightning, power voltage instability, etc.), the bus occupancy signal is made high so as not to occupy the bus. Because it does not have any effect on other processors, the system operates stably.

Claims (4)

In a switch of a busverse structure implemented by a bus controller which receives a frame synchronizing signal and a reference clock signal output from a bus master and outputs an assert signal, a bit rate clock signal and a data signal through the driver, And a pull-up resistor connected to an output terminal of an assert (AST) pin of the Pverse controller. In a switch of a busverse structure implemented by a bus controller which receives a frame synchronizing signal and a reference clock signal output from a bus master and outputs an assert signal, a bit rate clock signal and a data signal through the driver, And a long assert timeout generator for generating a timeout exceeding an allowable occupancy time of an assert signal to an assert (AST) pin output terminal of the busverse control unit. The method of claim 2, wherein the long assert timeout generating unit A reference clock generator serving as a reference clock, A counter that operates from the time the assert pin is activated low, An inverter that inverts the low signal of the assert pin, A register for controlling the frequency division by outputting the output signals of the inverter and the counter; And an inverter for inverting and outputting the signal of the register. The method of claim 3, wherein the reference clock generator A fibus stabilization circuit, which is used in place of a clock in the system itself.

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