KR100784740B1 - Error detecting code calculation circuit, error detecting code calculation method, and recording apparatus - Google Patents

Abstract

The recording apparatus adds the EDC to the user data and sends the EDC-added data to the scrambler in a sequence different from the coding direction Q. Although the processing data is added at the end of the direction Q, it is inserted in the middle of the different sequence. Thus, in order to send the EDC-added data in a different sequence, the EDC generator calculates the EDC median from the expected value of the second half of the even sector. The EDC generator then receives a different sequence of user data and calculates an EDC from the first half of the even sector and the expected value of the odd sector and the median EDC. The expected value is the error detection value of the code string having the same number of bits as the EDC-addition data, the corresponding bit of the sequence of direction Q is 1 and the other bits are 0.

Error detection code calculation circuit, error detection code calculation method, recording apparatus

Description

ERROR DETECTING CODE CALCULATION CIRCUIT, ERROR DETECTING CODE CALCULATION METHOD, AND RECORDING APPARATUS}

1 shows a data sequence of a data block of a Blu-ray disc.

2 is an enlarged view of an area having sectors Sec 0 and Sec 1;

Fig. 3 is a diagram showing an error detection code calculating section of the recording device disclosed in US patent application Ser. No. 11 / 366,629.

4 is a schematic diagram of a disc encoding device according to the first exemplary embodiment of the present invention.

5 shows user data used for path S1 and path S2 in accordance with an exemplary embodiment of the present invention.

6 illustrates a transport block of a data block.

7 shows data processing timing of paths S1 and S2.

8 shows an expected value used when calculating an EDC in a recording apparatus according to an exemplary embodiment of the present invention.

9 illustrates the concept of EDC calculation.

10 is a flowchart illustrating a method of generating an expected value.

11 shows processing of path 1 of a recording apparatus according to an exemplary embodiment of the present invention.

12 illustrates a detailed example of an EDC generator that performs the processing of path 1 of a recording apparatus according to an exemplary embodiment of the present invention.

13 is a diagram illustrating an example of an EDC expected value generator of an EDC generator.

14 is a schematic diagram showing a relationship between an EDC table referenced by an EDC generator and an initial expected value.

15 shows processing of path 2 of a recording apparatus according to an exemplary embodiment of the present invention.

FIG. 16 shows a detailed example of an EDC generator for performing the processing of path 2 of a recording apparatus according to an exemplary embodiment of the present invention. FIG.

FIG. 17 is a flowchart illustrating an EDC generation process of path 1. FIG.

18 is a flowchart illustrating an EDC generation process of path 2. FIG.

19 illustrates an EDC flag and an EDC area flag.

20 is a flowchart showing details of step S31 of FIG. 18;

FIG. 21 is a flowchart showing details of step S35 of FIG. 18;

FIG. 22 is a flowchart showing details of step S41 of FIG. 18;

FIG. 23 is a flowchart showing details of step S41 of FIG. 18;

24 illustrates a method of updating an EDC table.

FIG. 25 is a flowchart showing details of step S42 of FIG. 18;

26 illustrates a method of updating a sector counter.

27 illustrates the advantages of one embodiment of the present invention.

28 is a schematic diagram illustrating a disk encoding device according to a second exemplary embodiment of the present invention.

29 shows the data structure of a Blu-ray disc;

30 is a schematic diagram showing the format of an ECC cluster.

31 is a schematic diagram showing an LDC block.

32 is a diagram showing an encoding process of respective data for forming a RUB from user data and address information;

33 is a block diagram showing a playback apparatus described in Japanese Unexamined Patent Publication No. 2004-192749.

* Description of the symbols for the main parts of the drawings *

1: recording device 2: data buffer

3: buffer controller 4: encoder

13: EDC Generator 14: EDC Buffer

15: Integration Section 61: Column Counter

62: selector 63: EDC estimate generator

65: XOR circuit 67: sector counter

98: scrambler 99: replacement buffer

The disclosure of US patent application Ser. No. 11 / 366,629, filed March 3, 2006, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety.

The present invention relates to an error detection code calculation unit, an error detection code calculation method, and a recording apparatus for increasing the speed of recording data on an optical disc.

Following the so-called first generation optical discs such as CD, CD-R / RW and CD-ROM and the second generation optical discs such as Digital Versatile Disc (DVD), a shorter wavelength light source (blue-violet light) of 405 nm is A so-called third-generation optical disc has been developed which is a Blu-ray disc. Blu-ray discs increase the NA (numerical aperture) of the objective lens to 0.85, reducing the beam spot area to about 1/5 of the DVD, and shortening the wavelength of the light source, thereby about 5 times that of DVD. It is possible to read and write record marks with a recording density of a degree. In addition, the Blu-ray disc has a phase change recording layer covered with a 0.1 mm thick transparent covering layer, located on the disc substrate, thereby reducing the light travel due to the relative inclination of the disc and the laser light ( "Next generation optical disc", Nikkei Electronics Book, Oct. 7, 2003).

The data structure of a Blu-ray disc is detailed as follows by the standard. 29 is a diagram showing a data structure of a Blu-ray disc. In the Blu-ray standard, recording data is recorded onto disk 301 in units of recording unit blocks (RUBs) 302, also called clusters. RUB 302 consists of a run-in 303 and run-out 305 which are gap fields or buffer fields for data overwriting, and a physical cluster 304 located between these fields. Run-in 303 consists of 2760 channel bits (cbs) and run-out 305 consists of 1104 cbs. The physical cluster consists of 1932cbs * 496 frames = 958272cbs. Run-in 303 and run-out 305 are combined with the channel bit length of two frames or recording frames, which will be described later. Physical cluster 304 is comprised of a burst indicator subcode (BIS) that contains user data, disk address information, and the like.

Physical cluster 304 consists of 496 recording frames 306. Frame sync is located at the beginning of each recording frame 306. Accordingly, 496 frames (recording frame 306) constituting physical cluster 304 and 498 frames, which is the sum of two frames of run-in 303 and run-out 305, form one RUB 302.

The recording frame 306 is made up of 1932cbs and is modulated by a 1-7PP (parity preserve / prohibit RMTR) code. This is then demodulated, and the DSV (Digital sum value) control (dc-control) bit is erased from this demodulated data, thereby forming an ECC cluster.

30 is a diagram illustrating an ECC cluster. The ECC cluster 401 consists of 496 frames, which includes user data 402, ECC parity 404, and BIS 403. Extraction of the user data 402 and the EC parity 404 form a long distance code (LDC) cluster, with 64 of the 496 frames forming an ECC parity 404. Extraction of the BIS 403 forms a BIS cluster.

The BIS cluster contains the address information of the disk. The address information (9 bytes) of the BIS cluster is distributed to each address having 31 frames formed by dividing an ECC cluster of 496 frames into 16 segments. The BIS consists of three bytes per frame, nine bytes of three frames, and an address is contained in the first four bytes. Thus, acquisition of two frames in front of each address unit makes it possible to obtain address information (address unit number) of each address unit. When deinterleaved, the BIS cluster is changed into a format called a BIS block. In addition, the LDC cluster is changed to a format called an LDC block when deinterleaved.

31 is a diagram illustrating an LDC block 501. The LDC block is formed by deinterleaving data having 152 bytes in the horizontal direction (1 frame) and 496 frames in the vertical direction, obtained by extracting the user data 402 and the ECC parity 404 from the ECC cluster shown in FIG. do. The deinterleaving process is performed in two stages. First, the process increases the shift amount by three bytes every two frames and rotates in the right direction on the drawing. Then, the process inserts each byte of the even frame between each byte of the odd frame, so that the data having 248 frames half the vertical direction and 304 bytes, which is twice the data before deinterleaving in the horizontal direction (1 frame). To form.

In FIG. 31, the portion of the LCD block 501 other than the ECC parity 503 is the data block 502. One data block is composed of 32 sectors of Sec 0 to Sec 31. One sector has 2052 bytes, which has 2048 bytes of user data 504 and 4 bytes of error detection code (EDC) 505. If the direction of the data recording sequence is the recording frame direction P, and the direction of the user data is the user data direction Q, the recording frame direction P is the horizontal direction (low direction) on the drawing, and the user data direction Q is the vertical direction (column) on the drawing. Direction). Therefore, the data recording sequence and the user data sequence are different.

One sector has a user data sequence in which each sequence has 216 bytes, which are arranged in the user data direction Q in a folded configuration. Thus, in the user data 504, each sequence (216 bytes) is arranged in the recording frame direction P. Thus, one sector Sec of 2052 bytes has a 9.5 sequence in the user data direction Q. Since the 4-byte EDC 505 is located at the end of the 2048-byte user data 504 of each sector Sec, if the sector number of the first sector is 0 (Sec 0), the EDC 505 of the even sector is It is located at the center of one sequence of user data direction Q.

32 is a diagram illustrating an encoding sequence of respective data for generating a RUB from user data and address information. The LDC cluster and the BIS cluster are created separately. The LDC cluster D6 is generated as follows. First, in step SP1, the EDC is added to the user data D1 to form a data frame D2. The addition of the EDC is performed for each sector Sec, and the 2052 byte sector to which the EDC is added performs a predetermined operation sequentially in the user data direction Q for a sector having 2048 bytes of user data and 4 bytes of 0 data. Is obtained.

Then, in step SP2, scrambling is performed on the EDC appended data (data frame) D2 to which the EDC is added to form scrambled data (scrambled data frame; D3). Scrambling performs a predetermined algebraic operation on data in one sector having 2052 bytes appended with an EDC in the user data direction Q. Then, in step SP3, the rows and columns of the scrambled data D3 are rearranged to form the data block D4. Next, in step SP4, the ECC parity is added to the data block D4 to form the LDC block D5. Finally, in step SP5, interleaving is performed on the LDC block D5 as described above, thereby forming the LDC cluster D6.

On the other hand, the BIS cluster D11 is generated as follows. First, in step SP6, the user control data D8 is interleaved. In step SP7, the ECC is added to the address unit number D7, and the data is interleaved to form an access block D9 from these data. Next, in step SP8, the BIS ECC is added to the access block D9 and added to the BIS block D10. Finally, in step SP9, the BIS block D10 is interleaved, thereby forming the BIS cluster D11.

Thereafter, in step SP10, the LDC cluster D6 and the BIS cluster D11 are combined to form an ECC cluster D12. In step SP11, a synchronization signal (frame sync) and a DSV control bit are added to the ECC cluster D12 to form a physical cluster D13. Then, in step SP12, run-in and run-out are added to the physical cluster D13, 17PP modulation is performed, whereby run-in D14 ₁ located at the beginning and the end of the recording frame and Together with run-out D14 ₂ , a RUB D14 is formed that includes 495 recording frames D14 ₃ .

A reproducing apparatus for a Blu-ray disc formatted as described above is disclosed in Japanese Unexamined Patent Publication No. 2004-192749. 33 is a diagram showing a conventional playback apparatus described therein. The disc 701 is driven by the spindle motor 752 to rotate at a constant linear velocity (CLV) during recording and playback operations. Then, an optical pickup 751 (optical head) performs recording or reproduction of data on the disc 701.

The pickup 751 has a laser diode functioning as a laser light source, a photo-detector for detecting reflected light, and an objective lens functioning as an output end of the laser light, so that the laser light is transmitted through the objective lens. It is applied to the disc recording surface and forms an optical system (not shown) that directs the reflected light to the photo-detector. The pickup 751 is movable in the radial direction of the disk by a thread mechanism 753. The laser diode outputs a blue laser with a wavelength of 405 nm. The NA of the optical system is 0.85 and the laser radiation is controlled by the drive signal (drive current) from the laser driver 763. Reflected light information from the disk 701 is detected by the photo-detector, converted into an electrical signal in accordance with the detected light intensity, and provided to the matrix circuit 754.

The matrix circuit 754 has a matrix operation / amplification circuit corresponding to the output current from the plurality of light receiving devices as the current-voltage converter and the photo-detector, and generates the necessary signal by the matrix operation. For example, this is a high-frequency signal corresponding to the reproduction data (reproduction data signal), a focus error signal for servo control, a tracking error signal, a push-pull associated with a wobbling groove. -pull) signal, etc.

The reproduction data signal output from the matrix circuit 754 is provided to the reader / writer circuit 755, the focus error signal and the tracking error signal are provided to the servo circuit 761, and the detection information of the wobbling groove is provided. Indicative push-pull signal is provided to a wobble circuit 758.

If the disk 701 is a rewritable disk, the push-pull signal associated with the wobbling groove output from the matrix circuit 754 is processed by the wobble circuit 758. The wobble circuit 758 performs minimum shift keying (MSK) and harmonic modulated wave (HMW) demodulation on the push-pull signal representing the ADIP information, and demodulates the signal into a data stream constituting an ADIP address. Provide the stream to the address decoder 759. The address decoder 759 generates a clock by PLL processing using the wobble signal provided from the wobble circuit 758 and provides it to each component, for example, as an encoded clock for recording.

In recording, recording data is sent from the AV system 720 and sent to the memory of the ECC / scrambling circuit 757 for buffering. In this case, the ECC / scrambling circuit 757 performs processing such as adding error correction code, scrambling and adding sub-code to encode the buffered recorded data. ECC encoding and ECC decoding is a process corresponding to an ECC format using RS (248, 216, 33), code length 248, data 216, and reed Solomon (RS) codes of distance 33. The data after ECC encoding and scrambling is then modulated in the RLL 1-7 PP system by the modulation / demodulation circuit 756 and provided to the reader / writer circuit 755. The encode clock, which serves as a reference clock for the encoding process during recording, is a clock generated from the wobble signal described above.

The reader / writer circuit 755 may be used to adjust the laser drive pulse waveform for the recording data generated by the encoding process and fine adjustment of the optimal recording power for the characteristics of the recording layer, the spot shape of the laser light, the recording linear speed, and the like. Perform recording compensation processing. The recording data is then sent to the laser driver 763 as a laser drive pulse. The laser driver 763 applies a laser drive pulse to the laser diode of the pickup 751 to drive laser radiation. A pit (phase change mark) corresponding to the recording data is thereby formed on the disc 701.

Spindle servo circuit 762 controls the spindle motor 752 to form a CLV rotation. Spindle servo 762 obtains the clock generated by the PLL processing on the wobble signal as the current rotational speed information of the spindle motor 752, compares it with some CLV reference speed information, thereby forming a spindle error signal. do.

The operation of the recording and reproducing system and the servo system as described above is controlled by the system controller 760 configured by the microcomputer. System controller 760 performs various operations in accordance with commands from AV system 720. For example, when AV system 720 outputs a writing command, system controller 760 first moves pickup 751 to the address at which data is to be written. The system controller 760 then controls the ECC / scrambling circuit 757 and the modulation / demodulation circuit 756 to, for example, the AV system 720, which is video data and audio data in various formats such as MPEG2, for example. Perform the encoding processing as described above on the data transmitted from the. Then, a laser drive pulse from the reader / writer circuit 755 is provided to the laser driver 763, thereby performing recording. In recording or reproducing data, the system controller 760 controls access or recording and reproducing operations by using an ADIP address detected by the address decoder 759 or an address included in the BIS.

The above-described technique disclosed in Japanese Unexamined Patent Publication No. 2004-192749 has an object of providing a ROM medium having excellent RAM compatibility and the like, and linking data (run-in and run-out) of a Blu-ray disc. Has the advantage of servo tracking by scrambling the same process as the main data (user data).

In a Blu-ray disc of the above-described format, the direction of the recording data on the disc is the recording frame direction P, and therefore, it is necessary to modulate the data in the order of the direction P. Therefore, it is necessary to rearrange the data sequence from the user data direction Q to the recording frame direction P at least before modulation.

The EDC 505 described above is added to the distal end of each sector as shown in FIG. Thus, in the even sector, the EDC 505 is located in the center of one data line with 216 bytes of the user data direction Q. Thus, for example, when transmitting the data to which the EDC in the recording frame direction P is added, the EDC is transmitted before all the used data is transmitted to the even sector. Specifically, the EDC 505 needs to be added before the user data of the row located after the row including the EDC 505 such as D431 and D107 is transmitted. However, since the EDC 505 is obtained as a result of performing a predetermined operation on all user data of one sector, it is usually impossible to calculate the EDC 505 when there is a defect in the user data of one sector. Do.

As a result, it is necessary to read all the data in the user data direction Q once to determine the EDC in advance. However, this process needs to read the user data again when outputting the data in the recording sequence, which prevents high speed recording.

The above process requires accessing the data buffer at least twice, once for EDC calculation, once for data rearrangement into the recording sequence. Access to the data buffer to generate an error detection code reduces the throughput of memory access to the data buffer.

According to one aspect of the present invention, an error detection code calculation circuit for calculating an error detection code for detecting an error of a user data code string having a first sequence is provided. This circuit processes data in units of a data group comprising two or more sectors containing user data code strings. Each data group has a structure in which an error detection code appears at the end of the user data code string when reading in the first sequence and an error detection code appears in the center of the user data code string when reading in a sequence different from the first sequence. It includes an operation target sector having a. The error detection code calculating circuit includes a first operation section for calculating an error detection code intermediate value from a part of user data of an operation target sector, and an error detection code from the remaining portion of the user data of an operation target sector and an error detection code intermediate value. And a second operation section for calculating a, wherein the second operation section calculates an error detection code added to a user data code string included in an operation target sector read in a different sequence from the first sequence.

In general, when adding an EDC to data in a different sequence for transmission, the data to be encoded has an operation target section with an error detection code (EDC) inserted at an intermediate point of the leading data in a sequence different from the first sequence. If so, in the operation target section it is necessary to complete the calculation of the error detection code before sending all the user data code strings. Thus, the process in this case calculates an error detection code from all user data code strings, and then adds the calculated error detection code to the user data when the data is transmitted in a different sequence.

On the other hand, in the exemplary embodiment of the present invention, the first operation section and the second operation section perform an operation on each of the operation target sector and the remaining portions thereof. The first operation does not need to perform an operation on the entire code string because the second operation section performs an operation on a portion of the error detection code when reading data in a different order. Thus, the first operating section accesses only a portion of the code string, thereby reducing access to the data buffer.

As a result, the present invention provides an error detection code calculation circuit, an error detection code calculation method, and a recording apparatus that enable a reduction in access to a data buffer when calculating an error detection code for detecting an error of user data. Can be.

The present invention provides an error detection code calculation circuit, an error detection code calculation method, and a recording apparatus that enable a reduction in access to a data buffer at the time of calculation of an error detection code for detecting an error of user data.

Description of the Preferred Embodiments

The foregoing and other objects, advantages and features of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings.

Hereinafter, the present invention will be described with reference to exemplary embodiments. Those skilled in the art will recognize that many other embodiments may be achieved using the teachings of the present invention, and that the present invention is not limited to the embodiments shown herein for illustrative purposes.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings. An exemplary embodiment applies the present invention to a recording apparatus and an encoding device capable of fast recording to an optical disc. The following description is for the case of using a Blu-ray disc as an example of an optical disc and performing encoding according to a Blu-ray physical specification if necessary. However, the present invention is not limited thereto, but may also be applied to recording apparatuses and the like for other types of discs of different encoding order and recording order.

1 is a diagram illustrating an array sequence of data in units of bytes included in each data block of a Blu-ray disc. 2 is an enlarged view of two sectors Sec 0 and Sec 1. 1 and 2 indicate the sequence of the user data direction Q in bytes. Data block 41 includes 304 columns and 216 rows. Data block 41 includes 32 sectors. One sector consists of 2048-byte user data and 4-52 EDC with 2052-byte data.

Each sector has 304 columns of block data in which 216-bytes of data are arranged in columns. Row indicates row number (0≤Row≤215) and Column indicates column number (0≤Column≤303). For example, in sector 0, a column with Column = 9 means Q = 1994 to 2051 bytes of data. And occupies a row of Row = 0 to 107. Rows of Row = 108 to 215 of the column having Column = 9 are occupied by the 0 th through 107 th byte data of the next sector Sec 1. In this way, the data block 41 is configured such that the even sector and the odd sector form one unit (hereafter referred to as an "area"). Thus, data is repeatedly arranged in the same sequence in each region having a pair of sectors of 19 columns.

In the sectors Sec 0 to Sec 31, a predetermined operation is performed on the user data in the user data direction Q shown in Figs. 1 and 2 to add the EDC. The data is scrambled, then modulated and recorded on the disc. When recorded, the data blocks are recorded in the sequence of the recording frame direction P indicated by the arrows in Fig. 1, which is perpendicular to the column direction or the user data direction Q. The user data direction Q coincides with the processing sequence for the addition of the error detection code and the processing sequence for scrambling and encoding on the Blu-ray disc. As will be explained later, it is possible to scramble user data and EDC separately and integrate them together.

As described above, data is recorded on the Blu-ray disc in the recording frame direction P. Therefore, it is necessary to rearrange the data sequence from the user data direction Q, which is the processing sequence for encoding, to the recording frame direction P, at least before modulation. If encoding is performed in the recording frame direction P, the EDC cannot be calculated. While the EDC is determined based on all user data of the sector shown in Fig. 1, since the EDC is added before reading all user data of all sectors of the even sector, in this case, the EDC cannot generate the added data. .

As a result, if the user data direction Q (normal encoding sequence) as a sequence of user data and the recording frame direction P as a sequence for recording data on the disc are different, some algebraic calculation is performed to calculate an EDC or the like, It is generally necessary to add the obtained EDC in advance, and then rearrange the EDC-additional data in preparation for recording. In this case, data rearrangement is typically possible by temporarily storing the data with the EDC added to the data buffer. However, in order to achieve high speed operation, the data buffers must be made of expensive SRAMs and, therefore, are not practical.

In order to address this concern, according to US patent application Ser. No. 11 / 366,629 (Japanese Patent Application No. 2005-060364) (hereinafter referred to as "reference"), the recording apparatus transmits each burst transfer or the like. Substitution buffer with memory size of 2 planes (for writing and reading) m x 304 bytes x ECC buffer (9728 bytes x 2 planes) for temporarily storing ECC parity, temporarily storing EDC code An EDC buffer (4 bytes x 32 x 2 planes) for storage, and a scramble buffer (38 bytes x 2 planes). The invention disclosed in the above reference provides processing for temporarily storing the EDC, the scramble median, and the ECC obtained by encoding in the user data direction Q, while repeatedly burst-transmitting and scrambled user data from the data buffer (path S1 '). ) And the processing of adding EDC to the user data (path S2 ') to enable high-speed data transfer to the replacement buffer.

In the invention disclosed in the above-mentioned reference, the replacement buffer is composed of a memory which is randomly accessible without requiring refreshing, whereby the continuous data obtained from the data buffer by burst transfer is a high speed sequence of recording frame direction P. Makes it possible to rearrange them. In this case, even if the replacement buffer has a smaller capacity than the memory capacity of the data buffer, scramble for data rearranged in the recording frame direction P from the calculation result using the EDC, the scramble median and the ECC calculated and stored in the path S1 ' It is possible to carry out.

Therefore, although fast encoding could not be achieved without using a temporary memory capable of fast random access such as expensive SRAM as a data buffer, the invention disclosed in the reference is accompanied by the use of SDRAM or the like which is not suitable for fast random access as a data buffer. Only adding a relatively small size of circuit allows for high speed encoding at low cost.

It is necessary to read data from two clusters into a data buffer for encoding and rearranging one cluster. In order to record data in the recording frame direction P, data of one cluster (2048 bytes x 32 sectors) of the user data direction Q only needs to be read ahead for EDC encoding, which increases the absolute access to the data buffer and This leads to an increase in power consumption.

Achieving high speed encoding requires a costly data buffer that operates with a high frequency clock and further increases power consumption. In order to solve this concern, an exemplary embodiment of the present invention is that the EDC is inserted in the middle of leading data of a sector different from the user data direction Q, for example, the sector in the recording frame direction P, and the user data direction Q. When reading the data of, the following operation is performed on the data of the even sector added to the end of the sector. Specifically, the recording apparatus according to the exemplary embodiment of the present invention is configured to calculate, from a portion of the even sector, a first calculation section for calculating an EDC median which will be described later, and for calculating an EDC from the remainder and the EDC median. A second calculation section is included, and the two calculation sections determine the EDC. This reduces data access to the data buffers, enabling further improvements in encoding specifications, and in reducing power and cost. The sequence of the user data direction Q corresponds to the first sequence, the sequence of the recording frame direction P corresponds to the second sequence, and the even sector corresponds to the calculation target sector.

The following illustrative description describes at least a recording apparatus characterized by the process of generating an EDC from the above-described user data and in particular adding it to the user data in the encoding of the user data on a Blu-ray disc, and recording It is also possible to combine the device with the playback device to form a recording and playback device.

For easier understanding of the present invention, the calculation and error detection methods disclosed in the foregoing references are described herein.

3 is a diagram showing a part for calculating an error detection code of the recording apparatus disclosed in the reference.

In this reference, there is a step of determining an error detection code in the process (path 1 ') and inserting the error detection code and outputting data (path 2') in accordance with the Blu-ray specification. In the process of the path 2 ', burst-transmission of the data having the burst transfer size m and sequentially arranged in the user data direction Q in the recording frame direction P, and adding the EDC calculated in the path 1' to output the EDC additional data. do.

Specifically, according to the invention disclosed in the reference, the recording apparatus comprises a data buffer 11, a buffer controller 12, an EDC generator 13, an EDC buffer 14, and an integration section for storing user data; 15). In the following example, the user data is arranged in ascending order of addresses in the user data direction Q, and is temporarily stored in the data buffer 11 from the head data of the user data. The data buffer 11 is a memory for storing user data transferred from the host, which is formed of SDRAM or the like capable of burst transfer. Buffer controller 12 includes channel CH1 for reading user data to be used in path 1 'and channel CH2 for reading user data to be used in path 2'.

The user data read from the data buffer 11 in the sequence of the user data direction Q by the channel CH1 is transmitted to the EDC generator 13. The EDC generator 13 is constituted by a shift register which generates a 4-byte EDC simultaneously with the input of 2048-byte user data and 4-byte 0 data, which is data corresponding to one sector, in the user data direction Q. . The generated EDC is stored in the EDC buffer 14.

In the path 2 ', the user data read out from the data buffer 11 of the user data direction Q is sequentially transmitted by the channel CH2 to the consolidation section 15 in the recording frame direction P in the burst transfer size of the sequence of the user data direction Q. do. Specifically, user data (data block 41) consisting of 32 sectors is repeatedly transmitted 304 times in the recording frame direction P with a burst transfer size of the sequence of the user data direction Q. In this embodiment, the portion having 304 bytes x burst transfer size m in the user data direction Q is called a transport block. If the burst transmission size m is 6, the transmission of the data block 41 ends after repeating the transmission of the transport block 36 times.

When transmitting the transport block, the integration section 15 reads the EDC from the EDC buffer 14 at a predetermined timing, adds the EDC to the user data to be burst-transmitted, and outputs the data with the EDC added. .

The EDC-added data is then scrambled and output as recorded data. Details of this process are described in the foregoing references. In simple terms, the process stores the EDC-addition data into a buffer (substitution buffer) having a memory capacity equal to or larger than the transport block size, and then reads the data in the recording frame direction P and outputs it. Then, the EDC-addition arranged in the recording frame direction P scrambles the data, and outputs the scrambled data as the recording data. The scrambling uses the median scrambling value calculated with the EDC of path 1 '.

In path 1 ', the data to which the EDC has been added by the consolidation section 15 is then sequentially input to the scrambler one byte in the user data direction Q. In the scrambler, the scrambling value Sk is output from the scramble shift register at the input timing of the input data Dk, and the exclusive OR of the scrambling value Sk and the input data Dk is calculated to obtain scrambled Dk '. In path 1 ', the recording device stores the stored value (16 bits) of the scramble shift register as a scrambled intermediate value in the scramble buffer. The 16-bit scrambled intermediate value is used in the path S2 to calculate the scrambled value of the recording frame direction P, but not the user data direction Q, thereby enabling scrambling.

In addition, the invention disclosed in the reference calculates the scramble median value, and then calculates the ECC based on this data. Specifically, in path 1 ', ECC is calculated for use in path 2' in addition to the EDC and scramble median. As will be described later, it is possible to scramble the EDC-additional data output from the integration section 15, store the scrambled data in the substitution buffer, and output the data in the recording frame direction P as recording data.

According to the invention disclosed in the reference, the buffer controller 12, when calculating the EDC on the path 1 'and when the EDC-addition outputs the data on the path 2', one cluster (2048 bytes x 32 sectors of user data) It is necessary to read the user data of the data block) from the data buffer 11. Therefore, it is necessary to read a total of two data blocks in path 1 'and path 2'. On the other hand, in the exemplary embodiment of the invention described below, it is possible to reduce the total amount of user data readings, and thus reduce access to the data buffer even when performing the two steps as shown. Specifically, in the process of the embodiment, the user data used in the first step is reduced to about 1/4. The EDC median value is calculated based on about 1/4 user data, and then the EDC is calculated based on the remaining user data (of about 3/4) and the EDC median value. This makes it possible to reduce the access to the data buffer in the first stage by about a quarter. The present embodiment thereby reduces data access to the data buffer, allowing further improvements in the encoding specification and the reduction of power consumption and cost.

1st Embodiment

4 is a schematic diagram of a recording apparatus according to a first exemplary embodiment of the present invention. As shown in FIG. 4, the recording apparatus 1 includes a data buffer 2, a buffer controller 3, and an encoder 4. The data buffer 2 buffers user data sent from a host (not shown). The host may be an AV (audio-visual) system, a personal computer (PC), or the like, which instructs the recording device 1 to record user data or read data from a disc.

The buffer controller 3 controls reading of user data from the data buffer 2. The buffer controller 3 reads user data as needed, and transmits the reading data to the encoder 4. In order to calculate the EDC, the recording apparatus of the present embodiment is a process for calculating an EDC median value (here referred to as path 1) from data in the latter half of the even sector which is about one quarter of the user data of the entire data block, And a process of calculating EDC from the remaining 3/4 user data and the EDC median (here called path 2) in parallel. The buffer controller 3 has a channel CH1 for reading user data for use in the processing of path 1 and a channel CH2 for reading user data for use in the processing of path 2, both of which are data buffers. From (2).

Encoder 4 adds the EDC to the user data, and the EDC-addition scrambles the user data. The encoder 4 then outputs scrambled data (hereinafter referred to as recording data) and an ECC obtained from the recording data. The ECC and recorded data are then combined into a BIS code, modulated by 1-7PP, and recorded on the disc.

Encoder 4 includes an EDC generator 31, an EDC table 32, and an EDC buffer 33 for performing the processing of path 1. Also included is an EDC generator 34 to calculate an EDC in path two. EDC generator 31 functions as a first operation section, and EDC generator 34 functions as a second operation section. In the processing of path 1, the EDC generator 31 refers to the EDC table 32 and the EDC buffer 33 to perform the operation. The result of the operation performed in EDC generator 1 of path 1 is the EDC median, which is described later. The obtained EDC median is written back to the EDC buffer 33. In the processing of path 2, the EDC generator 34 refers to the EDC table 32 and the EDC buffer 33 to calculate an EDC, and writes the obtained EDC back to the EDC buffer 33.

The encoder 4 further includes an integration section 35 for adding the EDC stored in the EDC buffer 33 to the user data read out from the channel CH2 and outputting the EDC-added data. It further includes a scrambler 36 which scrambles the EDC-added data output from the integration section 35 and a scrambler value generator 37 which calculates the scrambler value necessary for the scrambler 36 to scramble the data. In addition, the encoder 4 further includes a substitution buffer 38 for rearranging the scrambled data into a sequence in the recording frame direction P by the scrambler 36. The integration section 35, the scrambler 36, the scramble value generator 37, and the substitution buffer 38 constitute a scramble processor that calculates recording data from the user data and the EDC and outputs the obtained recording data.

Encoder 4 also includes an ECC generator 39 for generating ECC from scrambled data and an ECC buffer 40 for buffering the ECC generated by ECC generator 39. Data read from the substitution buffer 38 in the sequence of the recording frame direction P is output as recording data. The data in the ECC buffer 40 is output as an ECC parity. The recording data and the ECC parity are output to an integrated section (not shown), where the recording data is rearranged into rows and columns, ECC is added, then interleaved, thereby forming an ECC cluster (Fig. 32). See D12).

Further, another encoding device for generating a BIS (BIS encoding device) generates an access block (see D9 in FIG. 32) from user control data and an address unit number (see D7 and D8 in FIG. 32), and furthermore, BISECC ( Refer to D10 in FIG. 32). The BIS encoding device then provides an access block and a BISECC to the integration section, thereby forming a BIS block (see D10 in FIG. 32). The BIS block is interleaved into the BIS cluster (see D11 in FIG. 32). The BIS cluster is then combined with the LDC cluster to form an ECC cluster (see D12 in FIG. 32). The frame sync and DSV control bits are added to the ECC cluster to form a physical cluster (see D13 in FIG. 32). Then, 17PP modulation is performed for the recording frame, and run-in and run-out are added thereto to form a recording unit block (RUB) (see D14 in FIG. 32). Thereafter, data is recorded onto the disc by the disc controller of the recording unit of the RUB.

This exemplary embodiment is described in more detail below. In this embodiment, after reading the user data of one sector, the EDC is calculated from about 1/4 of the user data of the path 1 without calculating the EDC, and then based on the remaining user data of the path 2 EDC is calculated by correcting the EDC median, thereby reducing access to the data buffer 2 occurring in path 1 by about a quarter.

FIG. 5 is a diagram illustrating user data used in the path 1 and the path 2 according to the present embodiment. FIG. The data block 41, which is a processing unit of the encoder 4, is inserted in the middle of reading data of one sector in a sequence different from the user data direction Q, and when the data is read in the user data direction Q, It has an even sector to which EDC is added at the distal end. In path 1 of this embodiment, the data block is read in the user data direction Q as the first sequence. On the other hand, in the path 2, user data each having a burst transfer size m arranged in the user data direction Q is read in the recording frame direction P as a sequence different from the first sequence. In this case, the even sector is a code string (operation target sector) into which the EDC is inserted before transmitting all data of one sector, as shown in FIG. Thus, in the process of path 1, the EDC median value is calculated by performing an operation on a part of the even sector serving as the calculation target sector of path 2, which is the latter part of the even sector read after the EDC is added. Then, in the process of path 2, the EDC is calculated by performing an operation on the remaining part of the even sector and the whole part of the odd sector. The odd sector is to read the user data having the burst transfer size m arranged in the sequence of the user data direction Q when reading data in the user data direction Q and in the recording frame direction P as a sequence different from the above sequence. When both are code strings (non-operation target sectors) to which the EDC is added at the end of the sector, therefore, it is not necessary to calculate the EDC median in path 1.

In this embodiment, six bytes of user data are burst-transmitted, but one byte of user data can be transmitted in a different sequence, for example, in the recording frame direction P, respectively. Since the EDC is 4 bytes in this embodiment, the EDC of the even sector is located at a row number Row = 104 to 107 and a column number Column = 9. Therefore, before calculating the head byte of the EDC located at row Row = 104 and column Column = 9 in path 2, the following operation (exclusive OR operation using expected values) needs to be completed for all user data of the even sector. have. For this reason, in the processing of path 1, it is necessary to perform processing for user data located in rows Row = 105 to 215 and columns Column = 0 to 8. This is the same when the burst transmission size is smaller than 4 bytes or when the burst transmission size is 4 bytes or more, and data is transmitted continuously for 2 transport blocks. Specifically, the present embodiment includes the exclusion of the expected value of all user data of the sector before the operation on the head byte of the EDC located at the position of Row = 104 and Column = 8 or Row = 212 and Column = 18. Perform the processing of path 1 so that a sieve OR is calculated. The method of calculating and specifying the head address of the data buffer 2 to perform a burst transfer is described later.

In the path 1, the channel CH1 of the buffer controller 3 stores the data located in rows Row = 108 to 215 of the even sector included in the data block 41 as part of the calculation target sector as shown in FIG. It reads in the direction Q and outputs the reading data to the EDC generator 31. Specifically, user data of Column = 0 and row Rows = 108 to 215 are sequentially transmitted, and then user data of Column = 1 and row Rows = 108 to 215 are transmitted. The transfer is repeated in this manner until column = 8 is reached. Since channel CH1 transmits user data of even sectors, after completion of the data transfer of Column = 8, sector 1 is skipped and transmits user data of sector 2 with Columns = 19 to 27 and Row = 108 to 215. To start. This transfer process is repeated until sector 30, the last good sector, is reached. The EDC generator 31 performs an operation on the second half of the even sector.

On the other hand, in the path 2, the channel CH2 of the buffer controller 3 reads all the data of the data block 41 in a reading order different from that of the channel CH1. Specifically, channel CH2 burst-transmits data of the burst transmission size m of path 2. Although the burst transfer size m is 6 in this embodiment, it may be larger or smaller than 6 bytes. Burst transmission size m is preferably equal to or larger than the size of the EDC.

First, 6-byte data arranged in the user data direction Q (column direction) is repeatedly transmitted 304 times for one data block in the recording frame direction P (row direction). In this embodiment, the data obtained as a result of transmitting 6 bytes of the user data direction Q 304 times is called a transport block (C). 6 is a diagram illustrating a transport block of the data block 41. In the case of performing a burst-transmission of each of 6 bytes, 36 transport blocks are transmitted to transmit one data block 41. Channel CH2 provides the user data of each of the 6 bytes to the aggregation section 35 by burst transfer, and also to the EDC generator 34. The EDC generator 34 stores data of the remaining part of the user data other than the latter part of the even sector performed by the EDC generator 31 in path 1 (this is the data of the first half of the even sector) and the whole part of the odd sector. Perform the operation on.

An overview of the calculation of the recording apparatus 1 according to the exemplary embodiment is described below. 7 is a diagram illustrating data processing timings of a path S1 and a path S2. As shown in Fig. 7, data is recorded on the disc in recording units of 1 RUB. User data contained in the t-th RUB is processed in the path S1, while user data (data block) contained in the (t-1) th RUB is processed in the path S2. Since the processing of the path S2 is performed based on the result of the processing of the path S1, the recording device 1 processes the user data included in parallel in the t-th RUB and the (t-1) th RUB, thereby being included in the RUB. User data can be encoded into the pipeline. The processing of the path S1 transfers the user data in the user data direction Q, and the processing of the path S2 outputs the scrambled user data in the recording frame direction P as the recording data.

While processing the user data included in the (t-1) th RUB in the path S2, the user data included in the t-th RUB is performed in the path S1. Therefore, before the start of the processing in the path S2 for the user data included in the (t-1) th RUB, the processing in the path S1 for the user data included in the t-th RUB is completed. Thus, in path S1, processing is performed on data that is at least 1 RUB earlier than the data processed by path S2.

The EDC calculation performed on Path 1 and Path 2 is described below. The operation in both path 1 and path 2 uses the predetermined value corresponding to the sequence of user data direction Q to calculate the EDC median value or EDC. The principle of the calculation method is explained first.

In a Blu-ray disc, 4 bytes (32 bits) of error detection code are added to 2048 bytes (16384 bits) of user data. Code string D (x) with 2048-byte user data appended with 4-byte zero data

G (x) = X ³² + X ³¹ + X ⁴ +1

By dividing by the generated polynomial of, a 32-bit error detection code can be obtained.

If 2048-byte user data is I (x), the error detection code EDC (x) is

EDC (x) = ∑b _t * X ^t = I (x) modG (x) (∑: t = 31 to 0)

Where I (x) = ∑b _t * X ^t (∑: t = 16415-32)

It is expressed as

As a result, the code string D (x) to which the error detection code EDC (x) has been added is

D (x) = I (x) + EDC (x)

Where the symbol "+" represents an exclusive OR operation

It can be expressed as

The error detection code EDC (x) can be obtained by inputting the code string D (x) into the 32-bit shift register shown in FIG. The value of the 32-bit shift register after entering all the codes of the code string D (x) is the error detection code EDC (x) (= 0). In this embodiment, the bit sequence of the user data direction Q is q, which is represented by q = b00000, b00001, ..., b16415, t = 16415-q and the like.

The error detection code EDC (x) may be obtained by calculating the exclusive OR of X ^t modG (x) corresponding to the bit of “1” of the input code string D (x). X ^t modG (x) is a code string d (x) whose code is set to 0 except for the bits of the (16415-q) (= t) th order in the code string D (x) with k = 16416. The remainder after dividing by) is shown.

9 is a view for explaining the above-described concept. The k-bit code string D (x) with k-bits all "1" ({111 ... 1}) is the base code string D '(x). The 32-bit shift register obtained by inputting the code string D '(x) into the shift register 50 shown in Fig. 8 is the error detection code E' (x) of the code string D '(x). In this embodiment, the code string D '(x) includes k = 2052 * 8 = 16416 bits.

The basic code string D '(x) is set as the code string d (x) _t of the k number referred to herein as the expected value calculating code, as shown in FIG. Each expected value calculating code string d (x) _{16415 to 0} has a bit corresponding to q being "1" and all other bits being "0". Specifically, q = b00000 corresponds to code string d (x) ₁₆₄₁₅ = {100 ... 0} with only the most significant bit "1", and q = b00001 corresponds to code string d with only the second bit "1". (x) ₁₆₄₁₄ = {010 ... 0}. Similarly, q = b16415 corresponds to code string d (x) ₀ = {000 ... 1} where only the least significant bit is "1". By inputting the expected value calculating code string d (x) t into the shift register 50, a 32-bit shift register value X ^t modG (x) is obtained.

Therefore, the remainder after dividing the expected value calculation code string d (x) by the error detection value G (x) is X ^t modG (x). X ^t modG (x) is referred to herein as an expected value. The expected value X ^t modG (x) represents a syndrome value when only bit data corresponding to the bit sequence q of the original code string D (x) is false.

The 32-bit shift register value (error detection string E '(x)) obtained by inputting the code string D' (x) into the shift register is obtained by inputting the expected value calculating code string d (x) _t into the shift register. It is equivalent to the value obtained by performing an exclusive OR on all 32-bit shift register values (expected value X ^t modG (x) = R _t ).

Thus, the error detection code E (x) may be obtained as an exclusive-OR of all expected values X ^t modG (x) corresponding to the bit sequence q of the code “1” in the code string D (x). Thus, the process of the present embodiment forms an expected value calculating code string d (x) that includes the same number of bits as the code string, and has the same bit sequence as the code string, wherein the bits corresponding to each bit sequence Is "1" and the other bit is "0". Then, the process is obtained by inputting the expected value calculating code string d (x) into the shift register 50 for the same number as the number of bits of the code string D (x) in this embodiment k = 16416. Maintain or calculate the expected value (the syndrome value). Use of these expected values makes it possible to obtain an exclusive OR (= EDC) of all expected values of bit "1" in the input code string D (x). Therefore, there is no need to input the code string D (x) into the shift register 50. In this way, if the expected value corresponding to each bit of the code string is known, even if the operation is performed in a sequence different from the user data direction Q, the error detection code E (x) of the code string D (x) will be obtained. Can be.

Data is processed in data block units. The data block 41 has 32 sectors (code string D (x)), and the error detection value E (x) is calculated for each code string D (x). Thus, 32 error detection value E (x) is obtained from one data block 41.

The expected value is described in detail below. As shown in FIG. 8, the code string D (x) input to the shift register 50 is, for example, data into the most significant bit (q = b00864) of the 109th byte (Q = D00108) of the user data direction Q. The input is "1" and the data of all other bits are X with "0". Thus, the code string X has 16416 bits in which the data of the ₁₅₅₅₂ th order is "1" (B ₀₀₈₆₄ = 1) and all other values are "0".

In this case, the result of inputting the code string X into the 32-bit shift register 50 is obtained by initializing the value of the shift register 50 to "00000001h" and shifting this value 15552 times.

In order to calculate the EDC, it is only necessary to calculate the exclusive OR of X ^t modG (x) with a bit data of the code string "1". If an exclusive OR of X ^t modG (x) is obtained, then the error detection value E (x), which is the 32-bit shift register value of the code string D (x), can be calculated.

10 is a flowchart illustrating a process of generating an expected value. As shown in Fig. 10, the process first initializes the shift register 50 to 0 (step S1). Next, an expected value calculating code string d (x) of 16415 bits is prepared, and the code string d (x) is input to the shift register 50. The process then rotates the shift register 50 repeatedly for 16416 bits (S3 and S4) until the 32-bit register value reaches a predetermined expected value (32 bits).

This exemplary embodiment is not valid for all expected values corresponding to bit data, but only for a total of 19 expected values corresponding to Row = 0 of an area 0 consisting of sectors 0 and 1. In a Blu-ray disc, the data block has a regular structure of 16 data sets, when viewed in the sequence of user data direction Q, each set having pairs of sectors 0 and 1 and containing 19 columns. Therefore, all the regions have the same bit sequence in the user data direction Q. In path 1, the operation starts with Row = 108. Because the expected value of Row = 108 is equivalent to the value of Column + 10 on the expected value of Row = 0, it is possible to calculate all the expected values from the 19 expected values of Row = 0 without storing all the expected values. . Thus, the predicted value is calculated from the 19 predicted value calculating code strings in which the MSB of Row = 0 is " 1 " and the others are " 0 " In this embodiment, the 19 expected values are called initial expected values. The column number of the region having a pair of even and odd sectors is M (0 ≦ M ≦ 18).

11 is a diagram for describing the processing of path 1. In path 1, the EDC generator 31 refers to only 19 expected values (initial expected values) corresponding to the most significant bit (MSB) of row Row = 0. Thus, EDC table 32 reads the expected values (initial expected values) corresponding to the most significant bits b00000, ..., b14688 of row Row = 0 and columns M = 0-18. The initial expected value is stored in advance in, for example, a memory or the like (not shown). The expected value of each column direction (user data direction Q) can be obtained simply by inputting the initial expected value into a shift register (rotation circuit), which will be described later, and shifting the data once.

EDC generator 31 generates an expected value of row Row = 108-215. The expected value of each column number M of Row = 108 corresponds to the expected value of each column number M + 10 of Row = 0. Thus, the EDC generator 31 refers to the EDC table 32 and reads an initial expected value corresponding to M + 10 of the input user data. The initial expected value is then shift-operated by the predictive value generator (which will be described later) to become the predicted value corresponding to the sequence q of each bit of the input user data. Then, the expected value and the user data obtained are Exclusive-OR, whereby the data of the rows Row = 108 to 215 and the columns M = 0 to 8 (data 42 indicated by the shade of Figure 11) All exclusive ORs are obtained as the EDC median.

12 is a diagram illustrating a detailed example of the EDC generator 31. The EDC generator 31 selects and reads an initial expected value from the EDC table 32 according to the column counter 61 that counts the column number M of one area of the input user data, and the count value of the column counter 61. And a selector 62. Further, the EDC generator 31 outputs the user data when the user data is "1", the EDC predictive value generator 63 which generates an expected value corresponding to the bit sequence q of the input user data from the initial predicted value. A selector 64 for outputting an expected value corresponding to the bit sequence q of data, and an XOR circuit 65 for calculating an exclusive-OR. In addition, the EDC generator 31 calculates the result of the calculation of the sector counter 67 for counting sectors of user data and the XOR circuit 65 for each sector according to the count value of the sector counter 67. And a selector 68 to transmit to.

13 is a diagram illustrating an example of the EDC expected value generator 63. 14 is a schematic diagram illustrating a relationship between an EDC table and an initial expected value. EDC expected value generator 63 has a structure in which a 32-bit shift register is rotated as shown in FIG. When the 32-bit initial expected value of column number M corresponding to the user data provided from the channel CH1 of the buffer controller 3 is input from the selector 62, the EDC expected value generator 63 shifts the value sequentially. Rotation, thereby generating an expected value corresponding to the bit sequence q in the user data direction Q.

The initial expected value is a value corresponding to the most significant bit of row Row = 0, and the initial expected value corresponding to the most significant bit of row Row = 108 is a value obtained by adding 10 to the column number M of row number Row = 0. Therefore, the initial expected value corresponding to the column number M which added 10 to the count value of the column counter 61 is read by the selector 62 and is provided to the EDC predicted value generator 63.

The EDC median is obtained as an exclusive OR of the expected value corresponding to the bit where the user data is "1". The selector 64 outputs an expected value corresponding to the bit sequence q of the user data generated by the EDC expected value generator 63 only when the user data provided from the channel CH1 is "1", and the user data is "0". , "000h" is selected and output.

In path 1, the EDC buffer 33 stores the operation result updated by the EDC generator 31. Therefore, upon completion of the processing of path 1, the EDC buffer 33 maintains the EDC median. In path 2, the EDC buffer 33 stores the result of the operation updated by the EDC generator 34, thus finally maintaining the EDC. The EDC buffer 33 has a storage area for storing the operation result for each sector. The data block 41 is made up of 32 sectors, and each operation result has 32 bits, and thus the EDC buffer 33 has 32 sectors of a 32-bit storage area. The value stored in each storage area corresponding to the odd sector of the EDC buffer 33 of path 1 is zero.

The selector 68 reads the value corresponding to the sector selected from the EDC buffer 33 by the sector counter 67 and provides the value to the XOR circuit 65. The XOR circuit 65 calculates the Exclusive-OR of the output of the selector 64 and the selected value of the selector 68, and provides the result to the selector 68. The selector 68 writes this result to the storage area of the corresponding sector of the EDC buffer 33.

As a result, upon completion of the user data input of sector 0, the EDC buffer 33 corresponds to the user data of the latter half of sector 0 (Row = 108 to 215 and M = 0 to 8) indicated by the shade of FIG. It stores the median EDC obtained by Exclusive OR for the expected value.

The processing of path 2 is described here. 15 is a diagram for describing the processing of path 2. As shown in Fig. 15, in path 2, channel CH2 of the buffer controller 3 is row data 0 through 107 and column M = 0 to 18 and user row and row Row = unprocessed user data in path 1; User data with 108 to 215 and columns M = 9 to 18 are sequentially provided to the EDC generator 34.

The channel CH2 sequentially provides a transport block having a burst transfer size m bytes in the user data direction Q x 304 bytes in the recording frame direction P as described above. 32 sectors of user data are transmitted to the consolidation section 35. EDC generator 34 may provide only the data needed for the operation. For example, when the transport block is a good sector (M = 0 to 9), data of row Row = 0 to 107 may be provided, and when the transport block is an odd sector (Row = 9 to 18), all users Data may be provided. Alternatively, all user data of the data block may be provided, and only necessary user data may be selected for the operation.

The EDC generator 34 basically has the same structure as the EDC generator 31. 16 is a diagram illustrating a detailed example of the EDC generator 34. As shown in Fig. 16, the EDC generator 34 stores the column counter 71 for counting the column number M of one area of the input user data, and from the EDC table 32 in accordance with the count value of the column counter 71. A selector 72 for selecting and reading the initial expected value. In addition, the EDC generator 34 outputs the user data when the user data is "1", the EDC predictive value generator 73 which generates the predicted value corresponding to the bit sequence q of the input user data from the initial predicted value. A selector 74 for outputting an expected value corresponding to the bit sequence q of the user data, and an XOR circuit 75 for calculating an exclusive-OR. In addition, the EDC generator 34 stores the calculation result of the sector counter 77 for counting sectors of user data and the XOR circuit 75 for each sector according to the count value of the sector counter 77. And a selector 78 to transmit to.

The EDC generator 34 or the recording device 1 refers to a counter for counting the row number row of user data (hereinafter referred to as a base row counter) and a counter for counting the row number of the burst transfer size m (hereinafter referred to as a burst transfer low counter). ) In the following description, the row number (count value) counted by the base row counter is Row (0≤Row≤215), and the row number (count value) counted by the burst transfer low counter is N (0≤N≤ m-1). In addition, the EDC generator 34 detects an input timing of the 2049th data of the user data direction Q in accordance with the count value of each counter, and an EDC detecting the input timing of 4 bytes of the 2049th to 2052th bytes. It further has an area flag, both of which are not shown.

In path 2, after completion of transmission of one transport block, the transport blocks are transmitted sequentially until the final block is reached. For example, user data of a transport block transmitted immediately after the first transport block starts at Row = N + first row. Thus, when the next transport block is sent, EDC table 32 maintains the expected value corresponding to the most significant bit of Row = N + first row. While generating an expected value corresponding to the last bit of each column of the last area of the transport block, the value is sequentially overwritten in the EDC table 32. Thus, when the operation for one transport block is completed, EDC table 32 maintains an expected value corresponding to the most significant bit of the first row of the next transport block. The selector 72 provides the value generator 73 with a value corresponding to the column number of the input user data, thereby enabling generation of the expected value of the next transport block.

Then, the XOR circuit 75 is inclusive with respect to the EDC intermediate value stored in the EDC buffer 33 by the processing of the path 1 and the expected value generated in the manner described above and selected and output by the selector 74. Perform an -OR operation and write the result back to the EDC buffer. Thereby, the EDC corresponding to each sector is calculated simultaneously with the completion of the Exclusive-OR for all user data of each sector. Thus, the EDC of the even sector is calculated first, and then the EDC of the odd sector is then calculated. The EDC is calculated at the timing when the EDC flag becomes "1". In the present embodiment, since the burst transfer size m is 6, with respect to user data input in the 2047th to 2052th bytes, up to the 2048th byte, if the data is "1", the value stored in the EDC buffer 33 is described above. It is updated by the XOR circuit 75 as one did. While the EDC area flag is "1", which is the timing at which the 2049th to 2052th data are sequentially input in the user data direction Q, the process does not use the 2049th to 2052th byte of user data, and 4- as the input data. Performs operation using byte 0 data. Since the data in this period are all zero data, the selector 74 simply provides 0000h to the XOR circuit 75 without updating the value of the EDC buffer 33. Thus, when the 2049 th byte of data is input, the predictor generator 73 simply rotates this value sequentially, and the data of the corresponding sector stored in the EDC buffer 33 is output to the integration section 35 as an EDC. .

The 2049th byte data corresponds to the position of the head data of the EDC of the data block. Thus, after 2048 byte user data has been transmitted, the aggregation section 35 shown in FIG. 4 adds the EDC according to the transmission sequence of the channel CH2. Therefore, in order to enable the output of the EDC, the Exclusive-OR of the expected value with each bit equal to "1" for all user data of 2048 bytes simultaneously with the data input of the 2049th byte corresponding to the EDC head data. = EDC) or EDC before adding EDC head data.

The EDC generation process of path 1 and path 2 is described in detail below. First, the processing of path 1 will be described with reference to FIGS. 11, 12, and 17. 17 is a flowchart illustrating EDC generation processing of path 1. FIG. As described above, the EDC buffer 33 holds the operation result of each sector. In the following description, the operation result of each sector is referred to as EDCValue [0 to 31].

The process first initializes the EDC buffer 33, each counter, and the EDCValue [0 to 31] of the EDC table 32. Specifically, all the EDCValues [0 to 31] of the EDC buffer 33 are set to 0 (step S11). In addition, the count values of the sector counter 67 and the column counter 61 are set to 0 (steps S12 and S13). In addition, the table value of the EDC table 32 is set to an initial expected value (see * 1 in FIG. 17). The value shown in * 1 represents the initial expected value set in the 19 storage areas of the EDC table 32. Next, the 19 expected values stored in the EDC table 32 are represented by EDCTable [M], respectively. "M" represents a column number of one region and is 0-18. For example, as shown in * 1, a code string of 16416 bits (one sector) in which the MS0000 of D0000 bytes is "1" and the others is "0" is input into the shift register 50, which is the EDC generator shown in FIG. The EDCTable [0] is set to 32-bit value (expected value) = 0x8af08bed obtained by

The selector 62 then reads the value of EDCTable [M + 10] (S15). As described above, this embodiment uses the 19 expected values of the most significant bit in Row = 0 as the initial expected values, and generates all expected values from those 19 expected values.

Since the count value M of the column counter 61 is initially M = 0, the process reads the value of EDCTable [10]. Then, user data is acquired from the next channel CH1 (step S16). One sector of 2052 bytes (including 4-byte data) includes D0000 to D2051 in the user data direction, and the process of step S16 performs D0108 + 216 * N (N = 0 to 8) at the head in the user data direction. 108-byte data is obtained sequentially.

In the present exemplary embodiment, the obtained data is stored in units of 1 byte (8 bits) and processed in the following manner. First, if the MSB of the acquired data is "1", the sector 64 outputs the expected value generated by the expected value generator 63 to the XOR circuit 65. The selector 68 selects to read the value of the sector of the corresponding processing state from the EDCValue [0 to 31], and outputs the selected value to the XOR circuit 65. The XOR circuit 65 calculates these Exclusive-ORs and outputs the result to the selector 68. The selector 68 writes the result back to the storage area of the corresponding sector of the EDC buffer 33 (step S18). The process then rotates the data stored in the EDC expected value generator 63 (S19), shifts the 8-bit data (S20), and repeats step S17 and subsequent steps 8 times for 8 bits (S21). . Specifically, the process shifts one bit in step S20, and determines whether or not the bit stored at the position of the MSB is "1". If "1", calculate Exclusive-OR with the expected value and write the result back to EDCValue [0 to 31].

The process then repeats the above processing for A bytes, which in this embodiment is the burst transfer size m = 6 (S22). Upon completing the processing for 108 bytes of the first column, the process determines whether the count value M of the column counter 61 is 8 (S23). If it is not the count value M, the count value is increased (S24). If the count value is 8, meaning sector boundary, the process resets the count value (S25), and sets the count value sector of the sector counter 67 to be +2. If the determination result in step S23 results in "no", it means that the process of 9 columns is not completed, and in step S27, it is determined that the processing for one sector is not completed ("no" in step S27). . Thus, the process repeats the processing from step S15. Specifically, the process reads the initial expected value of the count value M + 10 of the column counter 61 into the expected value generator 63, rotates the shift register for each time to obtain 1-bit data, and user data. Generate the expected value corresponding to. If the user data is "1", the process reads the value of the corresponding sector of EDCValue [0-31], calculates Exclusive-OR, and writes the result back.

On the other hand, if the determination in step S23 is YES, the process of 9 columns is completed (YES in step S27). If there is a subsequent good sector, processing is performed thereon ("No" in step S28). When the processing for the last sector is completed, or when the count value of the sector counter 67 is 32, the process ends. Thus, the processing of path 1 of one data block is completed.

The EDC generation processing of path 2 will now be described in detail with reference to FIGS. 15, 16, and 18-26. 18 is a flowchart illustrating an EDC generation process of path 2. FIG. 20, 21, 22, 23 and 25 are flowcharts showing details of the processing of steps S31, S35, S41 and S42 of FIG. 18, respectively. 19 is a diagram for explaining an EDC flag and an EDC region flag. 24 is a diagram for explaining updating of an EDC table. 26 is a diagram for explaining updating of a sector counter.

First, the process initializes the value of each counter, the EDC table, and the like (step S31). Next, user data is acquired (S32). The data obtained in path 2 is burst-transmitted from channel CH2 of the data buffer 2.

After obtaining the data, the process determines whether it is data of the head of the EDC. Since 4-byte 0 data is added to the 2048-byte user data, the data following the 2048th byte data is detected as the head data of the EDC. In the data block shown in FIG. 15, the data input corresponding to the position of row Row = 104 and column M = 9 is detected as the head of the EDC of the even sector, and the data corresponding to the position of row Row = 212 and column M = 18. The input is detected as the head of the EDC of the odd sector. Detection may be made by checking whether the EDC flag indicating that the data is the head of the EDC indicates 1 (S33).

If the EDC flag is "1", it is determined that the data is the head of the EDC, and the obtained data is replaced with 00h (S36). Therefore, input 8-bit data is detected as "0", and the selector 74 selects and outputs 0000h. After performing 8-bit processing in the XOR circuit 75, the process repeats this a total of four times by the number of bytes of the EDC (S37 to S40) and proceeds to step S41. Also, when the EDC flag is not "1" and the EDC area flag is "1" (NO in step S34), the process proceeds to the next step S41. If the input 8-bit data are all "0", EDC generator 34 does not update the value of EDC buffer 33. Therefore, in fact, the data stored in the EDC buffer 33 at the same time as the completion of the EDC operation of the 2048th byte of user data is an EDC. The EDC flag and the EDC region flag will be described later in detail.

On the other hand, if the EDC flag is "0" and the EDC area flag indicating whether or not it is in the EDC area is "0", the process proceeds to step S35. In step S35, the process includes the expected value of the user data as "1" and the exclusive of the result of the operation stored in the EDC buffer as path 1, for the unprocessed user data in the path 1 (here also as the target data). OR is calculated sequentially. First, the process performs an operation of 8 bits (= 1 byte) of the target data, and then proceeds to step S41 (S35).

In step S41, the process updates each counter and the EDC table 32 (step S41), and further updates the sector counter 77 as necessary (S42). Then, the above-described processing is repeated by the number of m bytes (6 bytes in the present exemplary embodiment) of the burst transfer size (S43). Processing of 6 bytes is performed in the user data direction Q. After performing processing of the burst transfer size m (6 bytes in this embodiment), the process then performs processing of 304 columns (S44). Specifically, 6-byte data arranged in the user data direction Q is recovered 304 times in the recording frame direction P, and this processing is repeated 216 / m times (36 times in this embodiment) (S39), whereby Complete the processing of one data block. If 216 cannot be divided by the burst transfer size m, it is repeated by the number after rounding up the decimal. For example, if m = 16, 216/16 = 13.5, and the quotient is not an integer. In this case, in step S46, it is determined whether or not the number (14 times) after rounding up the decimal is performed. At this time, the EDC buffer 33 stores 32 sectors of the EDC.

The above-described processing will be described in more detail below. In the initialization processing of step S31, the count values of the sector counter 77, the base low counter (not shown), the burst transfer low counter (not shown), the column counter 71, and the area counter (not shown) are set to "0". It resets (S51 to S55) and reads the initial expected value, which is the expected value of the most significant bit at row = 0, into the EDC table 32 as shown in the flowchart of FIG. 20 (S56). The process also sets the EDC flag and the EDC region flag to "0".

As described above, the base row counter continuously counts all rows of one data block, and the count value corresponds to row numbers Row = 0 to 215. In addition, the burst transfer low counter counts row numbers N = 0 to 5 of the data transmitted in each burst transfer. The burst transfer low counter is used to count the burst transfer size, and the base low counter is used to count the rows of the entire data block. The area counter counts areas, each area having a pair of even and odd sectors. Sectors Sec 0 and Sec 1 form area Area 0, and the last two sectors Sec 30 and Sec 31 form area Area 15. Thus, the area counter counts from 0 to 15. These count values contribute to the proper selection of initial expected values to be read and to control timing such as writing back and resetting the expected values in the EDC table 32.

Hereinafter, the EDC flag and the EDC area flag will be described. When calculating the EDC, a predetermined operation is performed on a 2052 byte code string comprising 2048-byte data and 4-byte 0 data. Specifically, the EDC is obtained as a 32-bit shift register obtained by sequentially inputting a code string into the shift register 50 as shown in FIG. Also in the exemplary embodiment, the EDC is obtained by calculating an Exclusive-OR of expected values for 2052 bytes including 2048-byte user data and 4-byte 0 data.

4-byte 0 data is added to the data after the 2048th byte of the user data direction Q. Therefore, it is necessary to perform processing for 4 bytes of 2049 to 2052 bytes by detecting the 2049th byte corresponding to EDC0 as the head data of the EDC and replacing the obtained data with 00h. Thus, the EDC generator 34 determines whether or not the data to be obtained next is the 2049th byte data of the user data direction Q for each time to recover the data.

In this embodiment, an EDC flag for detecting whether or not data is the 2049th data is set at this terminal. Therefore, the EDC flag is a flag for detecting data that functions as head data of the EDC when the EDC is added. In the following description, the data of the fourth byte data in the head data, which functions as the EDC, is referred to as EDC0 to EDC3. EDC0 to EDC3 are located in the 2049th to 2052th bytes of the data block.

The EDC flag indicates "1" only when the input data is data input at the 2049th position of the sequence of the user data direction Q of each sector. Since the calculation of the EDC performs an exclusive OR of the expected values for each byte of the 2052-byte code string containing 2048-byte data and 4-byte zero data, the 4-byte portion (EDC) where the EDC is located Area) is processed as 4-byte 0 data regardless of input. Thus, in addition to detecting the EDC head data by the EDC flag, data input in the EDC area of the 2049th to 2052th bytes of the user data direction Q is detected by the EDC area flag. The EDC flag indicates "1" only when the column number of the even sector is 9 and the row number is 104 and the column number of the odd sector is 18 and the row number is 212. The EDC area flag indicates " 1 " only when the column number of the even sector is 9 and the row number is 104 to 107, and when the column number of the odd sector is 18 and the row number is 212 to 215. These flags are set based on count values of the base low counter, burst transfer low counter, column counter, and the like.

Thereafter, the process reads from the EDC table the initial expected value of the corresponding column number (count value of the column counter) M to the expected value generator 73 (S59). For example, when processing the first data of path 2, the value of EDCtable [0] is read because user data of sector Sec 0 of column number = 0 and row number = 0 is input first.

The details of step S35 are described below. In step S35, when the user data processed in the path 1 is input, the sum of the count value Row and the row count value N of the base row counter is 108 or more, and the column number (column count value of the column counter 71) M is If 0 to 8, the process proceeds to the next step S41 (S61). When Row + N = 0-107, or when Row + N = 108-215 and 0 ≦ column count value M ≦ 8, the processing of step S62 and subsequent steps is performed.

Specifically, as shown in FIG. 21, the process determines whether the above-described execution condition is satisfied (step S61), and if the condition is satisfied, it means that the obtained data is the target data, and the process determines the It is determined whether or not each bit is "1" (S62). If this is "1", selector 78 reads the EDCValue [sector] and provides it to XOR circuit 75. In addition, the selector 74 selectively outputs the expected value and provides it to the XOR circuit 75. The XOR circuit 75 calculates Exclusive-OR of these values and outputs the result to the selector 78. The selector 78 writes the result back to the EDCValue [sector] (S63). Then, the process rotates each data of the predictive value generator 73 to generate the predicted value, obtains the data one bit until the eight bits of processing is completed (S63 to S66), whereby the EDC The operation result or the EDC intermediate value stored in the buffer 33 is updated (corrected). The process of step S34 also stores one byte of the obtained data into a rotatable register or the like, and performs processing from step S63 on the bits stored in the position of the MSB, so that eight bits of processing are performed one bit at a time as described above. To perform.

Hereinafter, the details of step S41 will be described with reference to FIGS. 22 and 23. This step performs control of the respective counters, the lighting-back and the EDC table 32. As shown in Fig. 22, the process determines whether current processing is performed for the final area Area 15 and whether the count value N of the burst transfer low counter for counting the row number of the burst transfer is m-1. (S81). Since m = 6 in the present exemplary embodiment, it is determined whether N = 5 or not. In other words, the process determines whether processing for the last byte of one column of the last area Area 15 is complete. In the present embodiment, if it is determined that processing for the sixth byte of the final area Area 15 is completed, the process returns the current expected value EDCTmp (see FIG. 24) to the area EDCtable [M] of the corresponding column of the EDC table 32. Write on.

In the processing from head Area 0 to final Area 15, the process reads the expected value from EDC table 32 each time processing the column of each area. Specifically, in Area 0 to Area 15, the same EDC table value is used for the processing of the same transport block. For example, in the first processing of path 2, the EDC table 32 maintains an initial estimate, which is likewise sequentially read in the final area Area 15. On the other hand, after completing the operation for the final area Area 15, processing for the next transport block is started, and processing from the first area Area 0 is performed again. In the processing of the next transport block, the initial estimate is not needed, and 19 estimates corresponding to the most significant bit of the first row of the transport block are needed. Thus, when processing the last area Area 15 of the preceding transport block, rotate the expected value of the least significant bit of the last row of the preceding transport block to form an expected value corresponding to the MSB of the head byte of the head area, and then It is necessary to write the expected value back to the EDC table 32 for use in the expected value generation of the transport block.

As described above, since the processing for the final area Area 15 uses the same value of the EDC table 32 that was used for the head area Area 0, the corresponding process until the processing for the columns in the final area Area 15 is completed. You cannot overwrite the EDC table for a given column. Thus, the process first determines whether the current processing is performed for the final area Area 15 (S81). If it is not the final area Area 15, the process proceeds to step S83. If it is the last byte of the last area Area 15, the value held in the expected value generator 73 is an expected value corresponding to the LSB of the sixth byte of the last row of the transport block of step S64 described above (EDCTmp1 in Fig. 24). Is the value obtained by rotating (EDCTmp2 in FIG. 24). Therefore, it is an expected value corresponding to the MSB of the head byte of the burst transfer of the head area. This value is written back to the EDC table 32.

The process then increments the count value N of the burst transfer low counter (S83). Further, the process determines whether the row count value N is equal to m (m = 6 in this exemplary embodiment) (S84). If m = 6, the low count value is reset (S85). The process then increases the column count value M (S86), and determines whether the column count value M is 19, i.e., whether the head row of the region has been reached as a result of the increase (S87). If the column count value M is 19, the column count value M is reset, and the area count value of the area counter is increased (S89). Then, the process determines whether the current area is Area 16 = Area 0 (see Fig. 6), which is the head area of the transport block (S90). If the area count value Area is 16, the process resets this value (S91), and also resets the sector counter (S82). The process then adds m to the count value of the base low counter (S93).

After writing back the expected value to the EDC table 32 and resetting the counter or the like, the expected value generator reads the value from the EDC table 32. First, the process determines whether the burst low count value N = 0. If N = 0, a value corresponding to the current column count value M is read from the EDC table 32, and the value is set in the expected value generator (S95). Further, it is determined whether the Row + burst transfer low count values N = 108 and M≥9 (S96). At the boundary of row number Row = 108, the head byte of the even sector is included as shown in FIG. Since row = 108 is the boundary between the odd and even sectors, it is necessary to write back and reset the expected value once used in S82 to the initial expected value. Thus, if a boundary with low count value = 108 is detected, the process sets the EDC table 32 to the initial expected value as shown in * 2, and the value of the column count value M-9 EDCTable [M-9]. Reading (S97).

The process then sets the EDC flag and the EDC region flag by subsequent steps S98 to S105. First, in step S98, it is determined whether the user data to be obtained next is arranged at the head position of the EDC of the even sector. Since the byte of the 105th row of the 10th column is the EDC head data EDC0 of the even sector, it is determined whether the conditions of the column count values M = 9 and Row + N = 104 are satisfied (S98). If it is determined that the data is EDC head data, the process sets the EDC flag = 1 (S100). If it is not EDC head data of the even sector, the process determines whether it is head data of the odd sector. Since the byte of the 213th row of the 19th column is the EDC head data of the odd sector, it is determined whether the conditions of the column count values M = 18 and Row + N = 212 are satisfied (S99). If it is determined that the user data is EDC head data, the process proceeds to step S100 and sets the EDC flag = 1. On the other hand, if the data is neither the EDC head data of the even sector nor the EDC head data of the odd sector, the process sets the EDC flag = 0 (S101).

Then, as described in the above steps S37 to S40, for the EDC head data of the 2049th to 2052th bytes, the operation is performed on the byte data replaced with 00h. Accordingly, the EDC generator 34 performs the processing of steps S37 to S40 on the data of the EDC region after detecting the 2049th byte of EDC head data until the 2052th byte is reached without performing a normal operation. . Therefore, it is necessary to mask these user data during the input of the user data of the EDC area after detecting the EDC area.

To determine whether the input data is data of the 2049th to 2052th bytes of the even sector, that is, the data of the EDC area, the process determines whether the conditions of column numbers M = 9 and Row + M = 104 to 107 are satisfied. It is determined (S102). If the condition is not satisfied, the process determines whether the input data is the 2049th to 2052th data of the odd sector, that is, the EDC region by determining whether the conditions of column numbers M = 18 and Row + M = 212 to 215 are satisfied. It is additionally determined whether or not the data is (S103). If it is determined in step S102 or S103 that the input data is data in the EDC region, the process sets the EDC region flag = 1 (S104). If it is determined that it is not data in the EDC area, the process sets the EDC area flag = 0 (S105). The process then proceeds to step S42.

For example, if the burst transfer size m is 2, the data transfer up to 106th byte is completed by the 52nd burst transfer and the data transfer up to 108th byte is completed by the next (53th) burst transfer. In this case, it is necessary to transmit the EDC in two burst transmissions. Thus, the operation on the 2049th byte or the 2050th byte needs to be completed on the 52nd burst transfer. In other words, the operation on the 4-byte EDC needs to be completed when entering the EDC head byte or EDC1. In the above case, the expected value calculation for the user data of rows Row = 106 and 107 must be completed when processing the 2049th byte data of the even sector. Thus, in this case, the EDC median value is determined from the user data of row Row = 106 and 215 of the even sector of path 1.

When the EDC is located in two consecutive transport blocks, the process yields all 4-byte EDCs before the last EDC operation of the first transport block. In this case, it is necessary to complete the expected value calculation for 2048 bytes of user data before the operation timing of the first EDC0, and the process adjusts the user data, and for this, the median of the EDC in path 1 depends on the burst transfer size. Is calculated.

The processing of step S42 is described below. The process of this step determines the sector boundary and updates the sector counter. 25 is a diagram for explaining the details of the process of step S42, and FIG. 26 is a diagram for explaining the processing of step S42. As shown in FIG. 25, the process first determines whether the condition of the row count value Row + N < 108 is satisfied (S111). Specifically, the process determines whether the conditions of the row count value Row + N <108 and the column count value M = 10 are satisfied to determine whether the next user data to be transmitted is the user data of the odd sector (step S111 and FIG. 26). Even if the conditions of Row + N <108 and M = 10 are not satisfied, if Row + N ≧ 108 and M = 9, the next user data to be transmitted is data of the odd sector. Thus, if the conditions of Row + N <108 and M = 10 or the conditions of Row + N≥108 and M = 9 are satisfied, the process sets the sector count value to the area count value Area * 2 + 1 of the area center ( Step S113 and FIG. 26).

On the other hand, if the area count value Area is not 0 and the column count value M is 0 (see steps S114 and FIG. 26), it is determined that the user data to be transmitted next is the data of the even sector, and the process returns the sector count value. Set the count value Area * 2 (S115). In other cases, the sector counter is not updated and the process proceeds to the next step S43.

As a result of the above-described processing, the EDC median value calculated from the user data of the latter part of the even sector of the path 1 is corrected based on the remaining user data of the path 2, and the EDC is calculated based on these values and all user data of the odd sector. do. By performing some or all of the EDC operation of path 2, access to the data buffer of path 1 may be reduced to about one quarter. In path 1, when transmitting the user data of path 2 (second half of the good sector) in a different order from the user data direction Q in sequence, the operation is performed only on user data that cannot be input before adding the EDC, whereby the path Reduce access to data buffer 2 of one.

27 is a diagram for explaining the advantages of the present embodiment. The method shown in FIG. 3 calculates the EDC of path 1, and then outputs the EDC-added data using the EDC calculated on path 2. In this method, the user data read from the data buffer by channel CH1 is one data block containing 2048 bytes x 32 sectors. On the other hand, this exemplary embodiment performs processing of user data only in rows after Row 108 of the even sector of path 1. Thus, user data read from the data buffer can be reduced to 972 bytes x 16 sectors.

As shown in FIG. 27, the recording apparatus 1 of this embodiment adds the EDC generator 34 and the EDC table 32 to the recording apparatus shown in FIG. However, since the EDC generator 31 and the EDC generator 34 combine to perform processing of one data block to produce an EDC, additional power consumption is only used for the EDC table 32. EDC table 32 performs data processing of one data block, and power consumption is increased by 2048 * 32 bytes (65536 bytes) in an EDC operation. However, the data transfer amount of path 1 is about 1/4 of the amount when processing the entire data block as shown in FIG. Thus, power consumption is reduced by 99968 bytes ((2048 * 32-972 * 16) * 2) with respect to the data buffer and buffer controller 3. As a result of this embodiment, power consumption is reduced. The effect of reduced power consumption becomes more important as the operational clocks of the data buffers and buffer controllers become higher.

As mentioned above, due to the reduction in data buffer access, which can be an obstacle to encoding, the present embodiment has the advantage of achieving high speed encoding and reduced power consumption. The amount of data that can access the data buffer for a certain length of time is fixed and time decreases as the speed increases. Thus, data buffer access is a barrier to high speed encoding. Reducing the absolute amount of data access enables fast encoding and reduction of power consumption by the amount of data access. In addition, the reduction in the absolute amount of access allows the use of cheap buffers that still run at a slower clock while still achieving fast encoding. It is also possible to reduce the operating clock frequency for the data buffers and buffer controllers used to enable high speed encoding.

An exemplary operation of outputting recording data from the EDC-addition data generated in the above manner is described herein. The processing of calculating the EDC from the EDC median and outputting the recording data is performed by each circuit as the processing of path 2. Referring again to FIG. 4, user data burst-transmitted from channel CH2 is provided to EDC generator 34 and integration section 35.

The data buffer 2 is composed of a memory that requires refreshing, such as SDRAM, and is capable of random access and burst transfer. The following explanation describes the case of using SDRAM. SDRAM is DRAM with higher speed access than random access when accessing consecutive addresses, and the use of burst transfer function enables high speed data transfer. Thus, it is possible to reduce the cost compared to a memory capable of fast random access such as SRAM.

The channel CH2 of the buffer controller 3 repeatedly reads user data of one burst transfer size (m bytes) from the data buffer 2 of the user data direction Q, and the EDC-added data is arranged in the recording frame direction P. Send data sequentially. Thus, the 216-byte data of the user data direction Q is burst-transmitted repeatedly 304 times, each of one burst transfer size (m bytes), which is the number (304 bytes, 304 interleaving) of the bytes of the recording frame direction P. As a result, the user data (data block 41) contained in one RUB of the recording frame direction P becomes m bytes arranged in the user data direction Q. The m-byte data of the user data direction Q is then scrambled and stored in the substitution buffer 38, which may be an SRAM capable of fast random access, thereby outputting the recording data in the recording frame direction P.

The channel CH2 or integration section 35 has the function of specifying the head address of the burst transmission or controlling the timing of reading the EDC from the EDC buffer 33.

The scrambler 36 calculates the scrambled value corresponding to the sequence of the user data direction Q as the scrambled data and the exclusive-OR of the user data. Thus, when scrambling data, the scrambled data DS _i is

DS _i = S _i + D _i (where the symbol "+" stands for Exclusive-OR)

It can be obtained by the mod 2 addition (exclusive-OR) of the 8-bit scrambled data (scrambled value) _Si and the 8-bit input data D _i generated by the scrambler.

The scrambler of the Blu-ray disc sets an initial value to a 16-bit shift register to perform a predetermined operation, and generates a scrambled value of the user data direction Q for each time shifting the value. Therefore, if the data is inputted 6 bytes each in the recording frame direction P as in this embodiment, it is necessary to shift the data 210 times after obtaining the 6-byte scrambled value to obtain the scrambled value corresponding to the next column, This takes time. To solve this concern, the recording apparatus of the present embodiment has a scramble value generator 37 capable of calculating scramble values in this order from user data input. The scrambler value generator 37 provides the scrambler 36 with a scrambled value corresponding to the input data.

The replacement buffer 38 is constituted by a memory that can be randomly accessed without requiring refreshing such as SRAM. The following embodiment uses SRAM, but the critical buffer is not limited to SRAM, which allows fast random access. In order to replace the scrambled data with the data in the recording frame direction P, the substitution buffer 38 is located, and it is possible to transfer the scrambled data in the recording frame direction P at high speed. The replacement buffer 38 has two or more areas having a size equal to or larger than the above-mentioned transport block, and outputs recording data from one transport block while writing the transport block to another area. The size of the replacement buffer 38 may be much smaller than the size of the data buffer 2, thereby enabling cost reduction while achieving high speed transfer compared to the case of using SRAM as the data buffer 2.

The operation of path 2 is described in detail here. First, user data transmitted to the replacement buffer 38 will be described in detail. In a Blu-ray disc, the data of the user data direction Q is 216 bytes in one column. In the present exemplary embodiment, 216 bytes are divided into 36 parts (burst transfer size m = 6 bytes) to perform burst transmission of 6 bytes each.

SDRAM is a DRAM that is synchronized to a clock for fast burst transfers. For example, if the memory cells of the SDRAM consist of four blocks (banks) that can operate independently of each other, 32 bytes of burst transfers are possible by using eight consecutive burst transfers. The SDRAM can perform high speed data transfer by burst transfer of predetermined data if the first address to be transferred is specified.

The data in the recording frame direction P is every 216 bytes of data when viewed in the user data direction Q. In the Blu-ray standard, one sector contains 2048 bytes of user data and 4 bytes of EDC, and since the data transmitted from the data buffer 2 is data to which no EDC is added yet, for example, one sector is Has 2048 bytes. Thus, the first column byte of the odd sector, here referred to as the odd sector head column, adjacent to the even sector is every 212 bytes of data, not every 216 bytes. The odd sector head column is the ninth or tenth column of the sequence of the recording frame P of sector Sec 1, which is the tenth column of row Row = 0 to 107 of the user data direction Q and the ninth column of row Row = 108 to 215. to be. Therefore, when reading the data corresponding to the odd sector head column in the recording frame direction P, the data is every 212 bytes, not every 216 bytes. Since the head address of the data buffer 2 of the burst transfer is every 216 bytes in the parts other than the sector boundary, and every 212 bytes in the sector boundary, the buffer controller 3 counts the column counters and rows for counting column numbers such as areas. The sector boundary is detected using the counter, and the first address (head address) of the burst transfer of the data buffer 2 is calculated and specified based on the burst transfer size m. Specifically, the process sets +212 when detecting sector boundaries, otherwise adds 216 to the head address sequentially, thereby specifying the head address appropriately.

In a Blu-ray disc, the EDC added after the last data of the even sector is located in the middle of one data string when the data is arranged in the user data direction Q of row Row = 104 to 107. Thus, when transmitting user data containing this address, the integration section 35 reads the EDC from the EDC buffer 33, adds it to the user data, and outputs the EDC-added data to the scrambler 36.

The burst-transmitted 6-byte data is in the data direction Q, and the scramble value generator 37 can generate a scrambled value using a conventional scrambler. After processing the transmission data of one burst, the user data of the next column is burst-transmitted. Thus, with the use of a conventional scrambler, it is necessary to wait up to 210 clocks to obtain a scrambled value. On the other hand, the data of the Blu-ray Disc is every 216 or 108 bytes in the recording frame direction as shown in FIG. Thus, in addition to the usual scrambler that shifts data by one byte in the user data direction Q in one shift operation, a shift register capable of obtaining a value shifted 216 or 108 times in one shift operation is located, thus shifting The register is switched at each burst transfer. Thus, it becomes possible to provide a scrambled value corresponding to the user data in the user data direction Q transmitted from the channel CH2 to the scrambler 36.

The replacement buffer 38 has two or more recording areas, each of which has a size of a burst transfer size m × 1 recording frame (304 bytes). As described above, in order to perform processing on user data (data block) corresponding to 1 RUB of the path S2, a transport block written in one recording area is read and a transport block is written in another recording area. . The recording area may have two or more planes.

As a result, in the processing of outputting user data as recording data, the recording apparatus 1 adds the EDC to the user data, scrambles the EDC-addition of the user data direction Q, and writes the scrambled data back to the data buffer. Then, there is no need to read the data again in the recording frame direction P. This enables a high speed transfer of the recorded data without using an expensive memory capable of high speed random access such as SRAM as the data buffer 2. In addition, since access to the data buffer 2 occurring in path 1 is reduced as described above, it is possible to provide an optical recording disc encoding device or recording apparatus that achieves a reduction in power consumption and high speed encoding.

2nd Embodiment

A second exemplary embodiment of the present invention is described herein. 28 is a diagram illustrating a recording apparatus according to the second embodiment. In the second embodiment shown in FIG. 28, the same elements as in the first embodiment shown in FIG. 4 are denoted by the same reference symbols, and will not be described in detail here. The recording apparatus 81 of the present embodiment has an encoder 84 instead of the encoder 4 shown in FIG. Like the encoder 4 of FIG. 4, the encoder 84 performs an EDC operation on a portion of the even sector of path 1, and then calculates the EDC of path 2. The scramble processor of the encoder 4 according to the first embodiment performs scrambling after adding the EDC to the user data, but the scramble processor of the encoder 84 according to the present embodiment scrambles the user data and the EDC separately, The scrambled EDC is then added to the scrambled user data.

Thus, in path 2, user data from channel CH2 is also provided to EDC generator 34 and scrambler 96. The scrambler 96 receives a scrambled value corresponding to the input user data from the scrambled value generator 97, scrambles the data, and provides the scrambled user data to the substitution buffer 99. The scrambled user data is also provided to the ECC generator 39.

The EDC generated by the EDC generator 34 is provided to the scrambler 98 added in this embodiment. The scrambler 98 performs scrambling on the EDC. The scrambler 98 receives the scrambled value corresponding to the EDC from the scrambled value generator 97, scrambles the EDC, and then provides the scrambled EDC to the integration section 95 and the ECC generator 39.

The substitution buffer 99 provides the received scrambled user data to the integration section 95. The unifying section 95, unlike the unifying section 35 of the encoder 4 shown in FIG. 4, receives scrambled user data from the substitution buffer 99 and receives scrambled EDC from the scrambler 98, These data are integrated and output as recording data.

The ECC generator 39 receives the scrambled user data from the substitution buffer 99 and also receives the scrambled EDC from the scrambler 98 at an appropriate timing to add the EDC, thereby generating 32 sectors of ECC. The generated ECC is output through the ECC buffer 40.

Like the encoder 4 according to the first embodiment described above, the encoder 84 of the present embodiment receives the user data of the second half of the even sector, generates the EDC median of path 1, and then the even sector. For the EDC, EDC of path 2 is generated using the EDC median value, and for the odd sector, the EDC is calculated directly from the user data and the expected value. Thereby, the user data read out from the data buffer 3 is reduced by about a quarter as compared with the above reference, and thus has the advantage of reducing the access to the data buffer as in the first embodiment.

Encoder 4 scrambles the EDC-addition data, but scrambler 84 scrambles the data before adding the EDC, and then adds the scrambled EDC to the scrambled user data. This makes it possible to flex the timing of the calculation and the EDC addition.

The present invention is not limited to the above-described embodiment, and may be changed in various ways without departing from the scope of the present invention. For example, while the above embodiment describes a hardware configuration, the present invention is not limited thereto, and given processing may be implemented by executing a computer program on a CPU. In this case, the computer program may be recorded on a recording medium, or transmitted and provided through the Internet or another transmission medium.

Also, as described in the above-described second embodiment, the timing of the EDC addition may be before or after scrambling. In addition, the timing or order of providing data to circuits for EDC addition, such as integration sections, scramblers, scramble value generators, and substitution buffers, is not limited to the above, and may be changed in various ways.

It is apparent that the present invention is not limited to the above-described embodiments, and may be modified and changed without departing from the spirit and scope of the present invention.

According to the present invention, it is possible to provide an error detection code calculation circuit, an error detection code calculation method, and a recording apparatus that enable a reduction in access to a data buffer when calculating an error detection code for detecting an error of user data. .

Claims (27)

An error detection code calculation circuit for calculating an error detection code for detecting an error in a user data code string having a first sequence, The error detection code calculating circuit is configured to process data in units of a data group including two or more sectors including the user data code string, Each of the data groups is characterized in that the error detection code appears at the end of the user data code string when read in the first sequence and the error detection code is read in the user data code when read in a different sequence than the first sequence. An arithmetic target sector having a structure appearing in the middle of the string, The error detection code calculation circuit is A first calculation section for calculating an error detection code median value from a portion of user data of the calculation target sector; And A second operation section for calculating an error detection code from the remaining portion of user data of the operation target sector and the error detection code intermediate value; And the second operation section calculates the error detection code to be added to the user data code string included in the operation target sector read in a sequence different from the first sequence. The method of claim 1, And the second operation section updates the error detection code intermediate value based on the remaining portion of user data input in a sequence different from the first sequence to calculate the error detection code. The method of claim 1, The remaining part of the user data of the operation target sector is detected from the head data when the error is added to the user data code string included in the operation target sector when reading the data group in a sequence different from the first sequence. An error detection code calculation circuit including user data in the range up to the data immediately before the code. The method of claim 3, wherein The portion of the user data of the operation target sector is a user after the error detection code added to the user data code string included in the operation target sector when reading the data group in a sequence different from the first sequence. An error detection code calculation circuit comprising data. The method of claim 1, Each data group comprises a block having K rows and L columns (K and L are integers), The block includes user data included in a minimum recording unit for recording data on a disc, The first sequence is a user data coding sequence corresponding to the column direction of the block, And the row direction of the block corresponds to the recording sequence of the user data. The method of claim 5, And the data group includes the operation target sector into which the error detection code is inserted in the middle of one code string of the block. The method of claim 6, The portion of the user data of the arithmetic target sector is located after a row in which the last byte of the error detection code of the arithmetic target sector is inserted in which the error detection code is inserted in the middle of one code string of the block. An error detection code calculation circuit comprising data. The method of claim 5, The second operation section is K / m times (a fraction of K / m is rounded up to receive m-byte user data of the first sequence L times in the row direction as a sequence different from the first sequence). And an error detection code calculation circuit for receiving the data group by repeating. The method of claim 8, The user data code string is burst-transmitted from a data buffer, M bytes is the burst transfer size, And the error detection code is m bytes or less. The method of claim 5, The error detection code is obtained from a sector of k bytes composed of the user data code string having the first sequence and zero data of the same byte as the error detection code, The first operation section obtains an expected value from a k-byte code string having the first sequence, wherein a bit corresponding to the first sequence of the input user data is 1 and other bits are 0, and the input user When the data is 1, by calculating the exclusive-OR of the expected value sequentially, the error detection code intermediate value is calculated, The second operation section calculates the expected value of the input user data, and sequentially detects the predictive value of the input user data equal to 1 and an exclusive-OR of the error detection code intermediate value to detect the error. An error detection code calculating circuit for calculating a code. The method of claim 10, The first operation section is configured to receive the data group including the portion of the user data of the operation target sector in the first sequence, And the second operation section receives the data group in a sequence different from the first sequence. The method of claim 10, The second operation section performs operations in a different order from that of the first sequence, on data in which zero data of the same byte as the error detection code is added to an end of the user data code string of the first sequence, And calculating all the error detection codes before the operation on the last byte of zero data. The method of claim 10, And the first operation section and the second operation section calculate the expected value with reference to an initial expected value that is an expected value corresponding to a specific bit of the user data code string. The method of claim 10, And the first operation section and the second operation section calculate the expected value with reference to an initial expected value that is an expected value corresponding to one row of the block. The method of claim 14, The block includes a plurality of regions each having a pair of sectors, And the initial expected value is an expected value of one row of one region. The method of claim 15, An expected value table for storing the initial expected value; And And a buffer for storing the error detection code, The first operation section and the second operation section generate the expected value with reference to the expected value table, calculate the exclusive-OR, and calculate the intermediate value of the error detection code and the error detection code. Error detection code calculation circuit to store in a buffer. The method of claim 16, One of the sectors included in the area is the arithmetic target sector. The method of claim 10, The second operation section is the expected value of the input user data on a non-operation target sector having a structure in which the error detection code is added to the distal end even when read in a different sequence from the first sequence. And calculating the error detection code by sequentially calculating the exclusive-OR of the expected value when the input user data is 1. The method of claim 18, The second operation section performs operations in a different order from that of the first sequence, for data to which zero data of the same byte as the error detection code is added to the end of the user data code string of the first sequence. And calculating all the error detection codes before the operation on the last byte of zero data. The method of claim 1, And a sequence different from the first sequence corresponds to the row direction of the block. The method of claim 1, Wherein the first operation section processes a t-th data group and the second operation section processes a (t-1) th data group. An error detection code calculation method for calculating an error detection code for detecting an error in a user data code string having a first sequence, comprising: The error detection code calculation method may include processing data in units of a data group including two or more sectors including the user data code string, Each of the data groups is characterized in that the error detection code appears at the end of the user data code string when read in the first sequence and the error detection code is read in the user data code when read in a different sequence than the first sequence. An arithmetic target sector having a structure appearing in the middle of the string, The error detection code calculation method, Calculating, by a first operation section, an error detection code median value from a portion of user data of the operation target sector; And A second operation section, from the remaining portion of the user data of the operation target sector and the error detection code intermediate value, to the user data code string included in the operation target sector read out in a sequence different from the first sequence; Calculating the error detection code to be added. A recording apparatus for recording a data group including two or more user data code strings having a first sequence on a disc in a second sequence different from the first sequence, The recording apparatus processes data in units of a data group including two or more sectors including the user data code string, Each of the data groups is characterized in that the error detection code appears at the end of the user data code string when read in the first sequence and the error detection code is read in the user data code when read in a different sequence than the first sequence. An arithmetic target sector having a structure appearing in the middle of the string, The recording device, An error detection code calculation circuit for calculating an error detection code for detecting an error of the user data code string having a first sequence; And And a scramble processor that scrambles the data group based on the error detection code and the user data code string calculated by the error detection code calculation circuit and outputs the scrambled data group as recording data. The error detection code calculation circuit is A first calculation section for calculating an error detection code median value from a portion of user data of the calculation target sector; And A second operation section for calculating an error detection code from the remaining portion of user data of the operation target sector and the error detection code intermediate value; And the second operation section calculates the error detection code to be added to the user data code string included in the operation target sector read in a sequence different from the first sequence. The method of claim 23, The scramble processor, An integration section for adding the error detection code calculated by the error detection code calculation circuit to the user data code string; And And a scrambler for scrambling said data to which said error detection code incorporated by said integrating section has been added. The method of claim 24, Each data group includes a block comprising K rows and L columns (K and L are integers), The first sequence is a user data coding sequence corresponding to the column direction of the block, The recording data has a second sequence different from the first sequence, And the recording apparatus further comprises a substitution buffer for outputting the scrambled data scrambled by the scrambler in the second sequence. The method of claim 23, The scramble processor, A first scrambler that scrambles the user data code string; A second scrambler that scrambles the error detection code; And And an integration section for adding the error detection code scrambled by the second scrambler to the user data code string scrambled by the first scrambler. The method of claim 26, Each data group includes a block comprising K rows and L columns (K and L are integers), The first sequence is a user data coding sequence corresponding to the column direction of the block, The recording data has a second sequence different from the first sequence, The recording apparatus further includes a substitution buffer for outputting scrambled data scrambled by the scrambler in the second sequence, The integration section receives the scrambled data of the second sequence from the substitution buffer, adds the scrambled error detection code to the scrambled user data code string received in the second sequence, and adds the recording data. Output device to output.

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