KR100784014B1 - Organic Light Emitting Display Device and Driving Method Thereof - Google Patents

Abstract

The present invention relates to an organic light emitting display device capable of reducing the number of output lines of a data driver and ensuring sufficient driving time.

A method of driving an organic light emitting display device according to an embodiment of the present invention includes supplying i (i is a natural number) data signals and i reset voltages so as not to overlap each other to each output line during a horizontal period, Supplying i data signals and i reset voltages supplied to the output lines to i data lines using the i data signals and i reset voltages to the i data lines; Charging a voltage corresponding to a data signal, and emitting light from the pixels in response to the charged voltage.

Description

Organic Light Emitting Display Device and Driving Method Thereof}

1 illustrates a conventional organic light emitting display device.

2 is a diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating the demultiplexer illustrated in FIG. 2.

4 is a waveform diagram illustrating a method of driving an organic light emitting display device according to a first embodiment of the present invention.

FIG. 5 is a diagram illustrating a first embodiment of the pixel illustrated in FIG. 2.

FIG. 6 is a diagram illustrating a coupling structure of a pixel and a demultiplexer illustrated in FIG. 5.

7 is a waveform diagram illustrating a method of driving an organic light emitting display device according to a second embodiment of the present invention.

FIG. 8 is a diagram illustrating a second embodiment of the pixel illustrated in FIG. 2.

9 is a diagram illustrating a coupling structure of a pixel and a demultiplexer illustrated in FIG. 8.

<Explanation of symbols for main parts of the drawings>

10,110: scan driver 20,120: data driver

30,130: pixel portion 40,140: pixel

50,150: timing controller 142,142 ': pixel circuit

160: demultiplexer block portion 162: demultiplexer

170: demultiplexer control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display device and a driving method thereof, and more particularly, to an organic light emitting display device and a method of driving the same, which reduce the number of output lines of a data driver and ensure sufficient driving time.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, and an organic light emitting display device.

Among the flat panel displays, an organic light emitting display device displays an image using an organic light emitting diode (OLED) that generates light by recombination of electrons and holes. Such an organic light emitting display device has an advantage of having a fast response speed and being driven with low power consumption. In general, an organic light emitting display device generates light in an organic light emitting diode by supplying a current corresponding to a data signal to the organic light emitting diode using a driving transistor formed for each pixel.

1 is a diagram illustrating a conventional organic light emitting display device.

Referring to FIG. 1, a conventional organic light emitting display device includes a pixel portion 30 including pixels 40 formed at an intersection area of scan lines S1 to Sn and data lines D1 to Dm, and a scan line. (S1 to Sn) and the light emission control lines (E1 to En), the scan driver 10 for driving the data lines (D1 to Dm), the scan driver (10) and A timing controller 50 for controlling the data driver 20 is provided.

The scan driver 10 generates a scan signal in response to the scan drive control signals SCS supplied from the timing controller 50, and sequentially supplies the generated scan signal to the scan lines S1 to Sn. In addition, the scan driver 10 generates a light emission control signal in response to the scan drive control signals SCS, and sequentially supplies the generated light emission control signals to the light emission control lines E1 to En.

The data driver 20 generates data signals in response to the data driving control signals DCS supplied from the timing controller 50, and supplies the generated data signals to the data lines D1 to Dm. At this time, the data driver 20 supplies a data signal for one line to each of the data lines D1 to Dm in each horizontal period 1H.

The timing controller 50 generates the data drive control signal DCS and the scan drive control signals SCS in response to the synchronization signals supplied from the outside. The data driving control signals DCS generated by the timing controller 50 are supplied to the data driver 20, and the scan driving control signals SCS are supplied to the scan driver 10. The timing controller 50 rearranges the data Data supplied from the outside and supplies the data to the data driver 20.

The pixel unit 30 receives the first power source ELVDD and the second power source ELVSS from the outside and supplies the pixel power to each of the pixels 40. The pixels 40 supplied with the first power source ELVDD and the second power source ELVSS are transferred from the first power source ELVDD to the second power source ELVSS via the organic light emitting diode OLED in response to the data signal. Control the amount of current flowing. Here, the emission time of the pixels 40 is controlled corresponding to the emission control signal.

In the conventional organic light emitting display device driven as described above, each of the pixels 40 is positioned at an intersection of the scan lines S1 to Sn and the data lines D1 to Dm. Here, the data driver 20 includes m output lines to supply a data signal to each of the m data lines D1 to Dm. That is, in the conventional organic light emitting display device, the data driver 20 includes the same number of output lines as the data lines D1 to Dm. To this end, the data driver 20 includes a plurality of data driving circuits, and thus, a manufacturing cost increases. In particular, as the resolution and inch of the pixel unit 30 become larger, the data driver 20 includes more output lines, thereby further increasing the manufacturing cost.

Accordingly, an object of the present invention is to provide an organic light emitting display device and a method of driving the same, which reduce the number of output lines of the data driver and ensure sufficient driving time.

In order to achieve the above object, the driving method of the organic light emitting display device according to the embodiment of the present invention uses i (i is a natural number) data signals and i reset voltages so as not to overlap each other with each output line during the horizontal period. Supplying the i data signals and i reset voltages supplied to the output lines to the i data lines by using a demultiplexer; Charging each of the connected pixels with a voltage corresponding to the data signal, and emitting light from the pixels corresponding to the charged voltage.
Preferably, the reset voltage is supplied to each of the data lines after the data signal is supplied to initialize the voltages of the data capacitors equivalently formed on the data lines. The pixels are initialized by an initialization power supply connected to each of the pixels during a period in which a scan signal is supplied to a previous scan line, and charged with a voltage corresponding to a data signal supplied to the pixels during a period in which a scan signal is supplied to the current scan line. do.

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An organic light emitting display device according to an embodiment of the present invention includes a data driver for supplying i (i is a natural number) data signals and i reset voltages so as not to overlap each other with each output line every horizontal period, and the output line. A demultiplexer for supplying the i data signals and the i reset voltages to the i data lines, a scan driver for sequentially supplying the scan signals to the scan lines every horizontal period, the data lines and the scan lines; And pixels connected to each other, the pixels being initialized by the reset voltage when the scan signal is supplied to the previous scan line, and charged with a voltage corresponding to the data signal when the scan signal is supplied to the current scan line.

Preferably, the data driver alternately supplies the data signal and the reset voltage to the output line. Each of the pixels comprises an organic light emitting diode; A storage capacitor for charging a voltage corresponding to the data signal; A first transistor for supplying a current corresponding to the voltage charged in the storage capacitor to the organic light emitting diode; A second transistor connected to the data line, the current scan line, and the second electrode of the first transistor and turned on when a scan signal is supplied to the current scan line; A third transistor connected between the first electrode and the gate electrode of the first transistor and turned on when a scan signal is supplied to the current scan line; And a sixth transistor connected between the gate electrode of the first transistor and the data line and turned on when a scan signal is supplied to the previous scan line.

Hereinafter, preferred embodiments of the present invention may be easily implemented by those skilled in the art with reference to FIGS. 2 to 9 as follows.

2 is a diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.

2, an organic light emitting display device according to an exemplary embodiment of the present invention includes a scan driver 110, a data driver 120, a pixel unit 130, a timing controller 150, a demultiplexer block unit 160, And a demultiplexer controller 170 and data capacitors Cdata.

The pixel unit 130 includes a plurality of pixels 140 positioned in an area partitioned by the scan lines S1 to Sn and the data lines D1 to Dm. Each of the pixels 140 generates light having a predetermined luminance in response to a supplied data signal supplied from the data line D. To this end, each of the pixels 140 is connected to two scan lines, one data line, a power supply line for supplying a first power supply ELVDD, and an initialization power supply line (not shown) for supplying an initialization power supply. For example, each of the pixels 140 positioned in the last horizontal line is connected to the n-th scan line Sn-1, the n-th scan line Sn, the data line D, the power line, and the initialization power line. Meanwhile, a scan line (eg, a zeroth scan line S0), which is not shown, is further provided to be connected to the pixels 140 positioned in the first horizontal line.

The scan driver 110 generates a scan signal in response to the scan drive control signal SCS supplied from the timing controller 150, and sequentially supplies the generated scan signal to the scan lines S1 to Sn. Here, the scan driver 110 supplies the scan signal only to a part of one horizontal period 1H as shown in FIG. 4.

In detail, in the first embodiment of the present invention, one horizontal period 1H is divided into a syringe period and a data period. The scan driver 110 supplies a scan signal to the scan line S during the interval between the syringes in one horizontal period 1H. The scan driver 110 does not supply the scan signal during the data period of one horizontal period 1H. The scan driver 110 generates a light emission control signal in response to the scan drive control signal SCS, and sequentially supplies the generated light emission control signals to the light emission control lines E1 to En. Here, the light emission control signal is supplied for at least two horizontal periods.

The data driver 120 generates data signals in response to the data driving control signal DCS supplied from the timing controller 150, and supplies the generated data signals to the output lines O1 to Om / i. Here, the data driver 120 sequentially supplies at least i (i is a natural number of two or more) data signals to each of the output lines O1 to Om / i during one horizontal period 1H as shown in FIG. 4.

In detail, the data driver 120 sequentially supplies i data signals R, G, and B to be supplied to actual pixels during the data period of one horizontal period 1H. Here, since the data signals R, G, and B to be supplied to the actual pixels are supplied only during the data period, the data signals R, G, and B to be actually supplied to the pixels do not overlap with the scan time. The data driver 120 supplies dummy data DD that does not contribute to luminance during the interval between the syringes in one horizontal period 1H. Here, the dummy data DD may not be supplied because it is data that does not contribute to luminance.

The timing controller 150 generates a data driving control signal DCS and a scan driving control signal SCS in response to the synchronization signals supplied from the outside. The data driving control signal DCS generated by the timing controller 150 is supplied to the data driver 120, and the scan driving control signal SCS is supplied to the scan driver 110.

The demultiplexer block unit 160 includes m / i demultiplexers 162. In other words, the demultiplexer block unit 160 includes the same number of demultiplexers 162 as the output lines O1 to Om / i, and each of the demultiplexers 162 is any of the output lines O1 to Om / i. Is connected with one. Each of the demultiplexers 162 is connected to i data lines (D). The demultiplexer 162 supplies i data signals supplied to the output line O to the i data lines D during the data period.

When the data signal supplied to one output line O is supplied to the i data lines D, the number of output lines O included in the data driver 120 is drastically reduced. For example, if i is assumed to be 3, the number of output lines O included in the data driver 120 is reduced to about 1/3 of the conventional level, and accordingly, the data driving circuit included in the data driver 120 is included. The number of furnaces is also reduced. That is, in the present invention, a manufacturing cost can be reduced by supplying data signals supplied to one output line O to i data lines D using the demultiplexer 162.

The demultiplexer controller 170 demultiplexes the i control signals during the data period of one horizontal period 1H so that the i data signals supplied to the output line O can be divided into i data lines D and supplied. 162 supplies each. Here, the demultiplexer controller 170 sequentially supplies the i control signals supplied during the data period so as not to overlap each other as shown in FIG. 4. Meanwhile, although the demultiplexer controller 170 is illustrated as being installed outside the timing controller 150 in FIG. 2, the present invention is not limited thereto. For example, the demultiplexer controller 170 may be installed inside the timing controller 150.

The data capacitors Cdata are provided for each data line D, respectively. The data capacitors Cdata temporarily store the data signal supplied to the data line D and supply the stored data signal to the pixel 140. Here, the data capacitor Cdata is used as a parasitic capacitor that is equivalently formed in the data line D. In fact, the parasitic capacitors equivalently formed in each of the data lines D have a larger capacity than the storage capacitors formed in each of the pixels 140, so that the data signals can be stably stored.

FIG. 3 is a diagram illustrating an internal circuit diagram of the demultiplexer illustrated in FIG. 2. In FIG. 3, i is assumed to be 3 for convenience of description. 3 shows a demultiplexer 162 connected to the first output line O1.

Referring to FIG. 3, each of the demultiplexers 162 includes a first switching device T1, a second switching device T2, and a third switching device T3.

The first switching element T1 is connected between the first output line O1 and the first data line D1. The first switching device T1 is turned on when the first control signal CS1 is supplied from the demultiplexer controller 170 to supply a data signal supplied to the first output line O1 to the first data line D1. ). When the first control signal CS1 is supplied, the data signal supplied to the first data line D1 is temporarily stored in the first data capacitor CdataR.

The second switching element T2 is connected between the first output line O1 and the second data line D2. The second switching device T2 is turned on when the second control signal CS2 is supplied from the demultiplexer controller 170 to supply the data signal supplied to the first output line O1 to the second data line D2. ). When the second control signal CS2 is supplied, the data signal supplied to the second data line D2 is temporarily stored in the second data capacitor CdataG.

The third switching element T3 is connected between the first output line O1 and the third data line D3. The third switching device T3 is turned on when the third control signal CS3 is supplied from the demultiplexer controller 170 to supply the data signal supplied to the first output line O1 to the third data line D3. ). When the third control signal CS3 is supplied, the data signal supplied to the third data line D3 is temporarily stored in the third data capacitor CdataB.

FIG. 5 is a circuit diagram illustrating a first embodiment of the pixel illustrated in FIG. 2. The structure of the pixel shown in FIG. 5 is an example of the present invention, and the present invention is not limited thereto.

Referring to FIG. 5, each of the pixels 140 of the present invention is connected to the organic light emitting diode OLED, the data line D, the scan line Sn, and the emission control line En so that the organic light emitting diode OLED is connected. A pixel circuit 142 for controlling.

The anode electrode of the organic light emitting diode OLED is connected to the pixel circuit 142, and the cathode electrode is connected to the second power source ELVSS. The second power supply ELVSS is set to a voltage lower than the first power supply ELVDD, for example, a ground voltage. The organic light emitting diode (OLED) generates one of red, green, and blue light corresponding to the amount of current supplied from the pixel circuit 142.

The pixel circuit 142 may include a storage capacitor Cst and a sixth transistor M6 connected between the first power supply ELVDD and the initialization power supply Vint, and between the first power supply ELVDD and the organic light emitting diode OLED. A fourth transistor M4, a first transistor M1, a fifth transistor M5, a third transistor M3 connected between a gate electrode and a first electrode of the first transistor M1; A second transistor M2 is connected between the data line D and the second electrode of the first transistor M1.

Here, the first electrode is set to any one of a drain electrode and a source electrode, and the second electrode is set to an electrode different from the first electrode. For example, if the first electrode is set as the source electrode, the second electrode is set as the drain electrode. In addition, although the first to sixth transistors M1 to M6 are illustrated as P-type MOSFETs in FIG. 5, the present invention is not limited thereto. However, when the first to sixth transistors M1 to M6 are formed of N-type MOSFETs, the polarity of the driving waveform is inverted as is well known to those skilled in the art.

The first electrode of the first transistor M1 is connected to the first power supply ELVDD via the fourth transistor M4, and the second electrode is connected to the organic light emitting diode OLED via the fifth transistor M5. Connected. The gate electrode of the first transistor M1 is connected to the storage capacitor Cst. The first transistor M1 supplies a current corresponding to the voltage charged in the storage capacitor Cst to the organic light emitting diode OLED.

The first electrode of the third transistor M3 is connected to the first electrode of the first transistor M1, and the second electrode is connected to the gate electrode of the first transistor M1. The gate electrode of the third transistor M3 is connected to the nth scan line Sn. The third transistor M3 is turned on when the scan signal is supplied to the nth scan line Sn to connect the first transistor M1 in the form of a diode. That is, when the third transistor M3 is turned on, the first transistor M1 is connected in the form of a diode.

The first electrode of the second transistor M2 is connected to the data line D, and the second electrode is connected to the second electrode of the first transistor M1. The gate electrode of the second transistor M2 is connected to the nth scan line Sn. The second transistor M2 is turned on when the scan signal is supplied to the nth scan line Sn to supply the data signal supplied to the data line D to the second electrode of the first transistor M1. .

The first electrode of the fourth transistor M4 is connected to the first power source ELVDD, and the second electrode is connected to the first electrode of the first transistor M1. The gate electrode of the fourth transistor M4 is connected to the emission control line En. The fourth transistor M4 is turned on when the emission control signal is not supplied (that is, when the low emission control signal is supplied) to electrically turn on the first power source ELVDD and the first transistor M1. Connect.

The first electrode of the fifth transistor M5 is connected to the first transistor M1, and the second electrode is connected to the organic light emitting diode OLED. The gate electrode of the fifth transistor M5 is connected to the emission control line En. The fifth transistor M5 is turned on when the emission control signal is not supplied (that is, when the low emission control signal is supplied) to electrically connect the first transistor M1 and the organic light emitting diode OLED. Connect.

The first electrode of the sixth transistor M6 is connected to the storage capacitor Cst and the gate electrode of the first transistor M1, and the second electrode is connected to the initialization power supply Vint. The gate electrode of the sixth transistor M6 is connected to the n-1 th scan line Sn-1. The sixth transistor M6 is turned on when the scan signal is supplied to the n-th scan line Sn-1 to initialize the gate electrode of the storage capacitor Cst and the first transistor M1. To this end, the voltage value of the initialization power supply (Vint) is set lower than the voltage value of the data signal.

6 is a diagram illustrating in detail a connection structure of a demultiplexer and pixels.

4 and 6, an operation process will be described in detail. First, a scanning signal is supplied to the n−1 th scan line Sn−1 during an interval between syringes during one horizontal period 1H. When the scan signal is supplied to the n-1 th scan line Sn-1, the sixth transistor M6 included in each of the pixels 140R, 140G, and 140B is turned on. When the sixth transistor M6 is turned on, the gate terminal of the storage capacitor Cst and the first transistor M1 is connected to the initialization power supply Vint. Then, the storage electrode Cst and the gate electrode of the first transistor M1 are initialized to the voltage of the initialization power Vint.

Thereafter, the first switching device T1, the second switching device T2, and the third switching device T3 are applied by the first control signal CS1 to the third control signal CS3 sequentially supplied during the data period. It is turned on sequentially. When the first switching device T1 is turned on, a voltage corresponding to the data signal is charged in the first data capacitor CdataR formed on the first data line D1. When the second switching device T2 is turned on, a voltage corresponding to the data signal is charged in the second data capacitor CdataG formed on the second data line D2. When the third switching device T3 is turned on, a voltage corresponding to the data signal is charged in the third data capacitor CdataB formed on the third data line D3. In this case, since the second transistor M2 included in each of the pixels 140R, 140G, and 140B is set to a turn-off state, the data signal is not supplied to the pixels 140R, 140G, and 140B.

Thereafter, the scanning signal is supplied to the nth scan line Sn during the inter-syringe following the data period. When the scan signal is supplied to the nth scan line Sn, the second transistor M2 and the third transistor M3 included in each of the pixels 140R, 140G, and 140B are turned on. When the second transistor M2 and the third transistor M3 included in each of the pixels 140R, 140G, and 140B are turned on, the data signals stored in the first data capacitor CdataR to the third data capacitor CdataB are turned on. The voltage corresponding to is supplied to the pixels 140R, 140G, and 140B.

Here, since the voltage of the gate electrode of the first transistor M1 included in the pixels 140R, 140G, 140B is initialized by the initialization power supply Vint (that is, is set lower than the voltage of the data signal), 1 transistor M1 is turned on. When the first transistor M1 is turned on, the data signal is supplied to one terminal of the storage capacitor Cst via the first transistor M1 and the third transistor M3. In this case, a voltage corresponding to the data signal is charged in the storage capacitor Cst included in each of the pixels 140R, 140G, and 140B.

Here, the storage capacitor Cst is additionally charged with a voltage corresponding to the threshold voltage of the first transistor M1 in addition to the voltage corresponding to the data signal. Subsequently, when the emission control signal is not supplied to the emission control signal E (that is, when the emission control signal of a low level is supplied), the fourth and fifth transistors M4 and M5 are turned on and the storage capacitor Cst is turned on. The current corresponding to the voltage charged in the ()) is supplied to the organic light emitting diodes OLED (R), OLED (G), and OLED (B) to generate red, green, and blue light having a predetermined luminance.

That is, according to the present invention, the data signal supplied to one output line O can be supplied to i data lines D using the demultiplexer 162. However, in the driving method according to the first embodiment of the present invention shown in FIG. 4, sufficient charging time can be ensured because the data signal is supplied to the storage capacitor Cst only during the interval between syringes during one horizontal period 1H. There is no problem. In fact, it is necessary to ensure a sufficient period for the control signal CS to be supplied so that a sufficient voltage can be charged in the data capacitors Cdata during the data period. However, the filling time is further shortened because the interval between the syringes is shortened so that the period during which the control signal CS is supplied is sufficiently secured.

7 is a waveform diagram illustrating a method of driving an organic light emitting display device according to a second embodiment of the present invention.

Referring to FIG. 7, in the driving method of the organic light emitting display device according to the second embodiment of the present invention, the scan driver 110 sequentially supplies a scan signal during each horizontal period 1H. The scan driver 110 supplies the light emission control signal to overlap the two scan signals.

The demultiplexer controller 170 supplies the first control signal CS1, the second control signal CS2, and the third control signal CS3 to overlap the scan signal during each horizontal period 1H. Here, the first control signal CS1, the second control signal CS2 and the third control signal CS3 are sequentially supplied so as not to overlap each other.

The data driver 120 sequentially supplies the i data signals R, G, and B to the respective output lines O during the period in which the scan signals are supplied. Here, the data driver 120 supplies a reset voltage Vr between the data signals R, G, and B.

In detail, the data driver 120 supplies the data signals R, G, and B to overlap the control signals CS1, CS2, and CS3 when the control signals CS1, CS2, and CS3 are supplied. For example, the data driver 120 supplies the red data signal R to overlap the first control signal CS1 and the green data signal G to overlap the second control signal CS2. The data driver 120 supplies the blue data signal B to overlap the third control signal CS3.

In addition, the data driver 120 supplies the reset voltage Vr to the output line O after the respective data signals R, G, and B are supplied. For example, the data driver 120 supplies the reset voltage Vr to the output line O after the supply of the red data signal R is stopped. Here, the reset voltage Vr partially overlaps the first control signal CS1 and is supplied until the second control signal CS2 is supplied. The data driver 120 supplies the reset voltage Vr to the output line O after the supply of the green data signal G is stopped. Here, the reset voltage Vr partially overlaps the second control signal CS2 and is supplied until the third control signal CS3 is supplied. In addition, the data driver 120 supplies the reset voltage Vr to the output line O after the supply of the blue data signal B is stopped.

Here, the reset voltage Vr partially overlaps with the third control signal CS3 and is supplied until the next control signal CS1 is supplied next time. The reset voltage Vr is used to initialize the voltage charged in the data capacitor Cdata (that is, the parasitic capacitor) included in each of the data lines D. To this end, the voltage value of the reset voltage Vr is set lower than the voltage value of the data signal. In other words, the reset voltage Vr is set to a voltage value lower than the voltage of the lowest data signal that can be supplied from the data driver 120. For example, the voltage value of the reset voltage Vr may be set equal to the voltage value of the initialization power supply Vint.

6 and 7 will be described in detail the operation process. 6 illustrates the pixel 140 connected to the n-th scan line Sn-1 and the n-th scan line Sn.

First, a scan signal is supplied to the n-1 th scan line Sn-1. When the scan signal is supplied to the n-1 th scan line Sn-1, the sixth transistor M6 included in each of the pixels 140R, 140G, and 140B is turned on. When the sixth transistor M6 is turned on, one terminal of the storage capacitor Cst and the gate electrode of the first transistor M1 are initialized to the voltage of the initialization power supply Vint.

Meanwhile, the first control signal CS1 to the third control signal CS3 are sequentially supplied during the period in which the scan signal is supplied to the n-1 th scan line Sn-1. Then, the first switching device T1 to the third switching device T3 are sequentially turned on to supply the data signals to the data lines D1 to D3. In this case, since the scan signal is not supplied to the nth scan line Sn, in other words, since the second transistor M2 is turned off, the pixels 140R, 140G, and 140B connected to the nth scan line Sn are turned off. Is not supplied with the data signal.

Thereafter, the scan signal is supplied to the nth scan line Sn during the next horizontal period. When the scan signal is supplied to the nth scan line Sn, the second transistor M2 and the third transistor M3 included in each of the pixels 140R, 140G, and 140B are turned on. In addition, the first switching element T1, the second switching element T2, and the first switching element CS1 through the first control signal CS1 to the third control signal CS3 during the period in which the scan signal is supplied to the nth scan line Sn. The three switching elements T3 are sequentially turned on.

When the first switching device T1 is turned on, the red data signal R, which is supplied to the first output line O1, is supplied to the first data line D1. The red data signal R supplied to the first data line D1 is supplied to the pixel 140R via the second transistor M2 of the red pixel 140R. In this case, since the gate electrode of the first transistor M1 of the red pixel 140R is initialized by the initialization power supply Vint, the first transistor M1 of the red pixel 140R is turned on. When the first transistor M1 of the red pixel 140R is turned on, the red data signal R passes through the first transistor M1 and the third transistor M3 of the red pixel 140R through the storage capacitor Cst. It is supplied to one terminal of). At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal and the threshold voltage of the first transistor M1.

Thereafter, the reset voltage Vr is supplied to the output line O1 to overlap the first control signal CS1 for a period of time. The reset voltage Vr supplied to the output line O1 changes the voltage of the parasitic capacitor CdataR (that is, the data capacitor) of the first data line D1 to the voltage of the reset voltage Vr. Meanwhile, even when the parasitic capacitor CdataR of the first data line D1 is changed to the voltage of the reset voltage Vr, the voltage charged in the red pixel 140R is stably maintained. In other words, since the first transistor M1 is connected in the form of a diode, the voltage charged in the storage capacitor Cst is stably maintained without being resupplied to the first data line D1.

When the second switching device T2 is turned on by the second control signal CS2, the green data signal G, which is supplied to the first output line O1, is supplied to the second data line D2. The green data signal G supplied to the second data line D2 is supplied to the pixel 140G via the second transistor M2 of the green pixel 140G. In this case, since the gate electrode of the first transistor M1 of the green pixel 140G is initialized by the initialization power supply Vint, the first transistor M1 of the green pixel 140G is turned on. When the first transistor M1 of the green pixel 140G is turned on, the green data signal G passes through the first transistor M1 and the third transistor M3 of the green pixel 140G through the storage capacitor Cst. It is supplied to one terminal of). At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal and the threshold voltage of the first transistor M1.

Thereafter, the reset voltage Vr is supplied to the output line O1 to overlap the second control signal CS2 for a period of time. The reset voltage Vr supplied to the output line O1 changes the voltage of the parasitic capacitor CdataG (that is, the data capacitor) of the second data line D2 to the voltage of the reset voltage Vr. Meanwhile, even when the parasitic capacitor CdataG of the second data line D2 is changed to the voltage of the reset voltage Vr, the voltage charged in the green pixel 140G is stably maintained. In other words, since the first transistor M1 is connected in the form of a diode, the voltage charged in the storage capacitor Cst is stably maintained without being resupplied to the second data line D2.

When the third switching device T3 is turned on by the third control signal CS3, the blue data signal B supplied to the first output line O1 is supplied to the third data line D3. The blue data signal B supplied to the third data line D3 is supplied to the pixel 140B via the second transistor M2 of the blue pixel 140B. In this case, since the gate electrode of the first transistor M1 of the blue pixel 140B is initialized by the initialization power supply Vint, the first transistor M1 of the blue pixel 140B is turned on. When the first transistor M1 of the blue pixel 140B is turned on, the blue data signal B passes through the first transistor M1 and the third transistor M3 of the blue pixel 140B and the storage capacitor Cst. It is supplied to one terminal of). At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal and the threshold voltage of the first transistor M1.

Thereafter, the reset voltage Vr is supplied to the output line O1 to overlap the third control signal CS3 for a period of time. The reset voltage Vr supplied to the output line O1 changes the voltage of the parasitic capacitor CdataG (that is, the data capacitor) of the third data line D3 to the voltage of the reset voltage Vr. Meanwhile, even when the parasitic capacitor CdataG of the third data line D3 changes to the voltage of the reset voltage Vr, the voltage charged in the blue pixel 140B is stably maintained. In other words, since the first transistor M1 is connected in the form of a diode, the voltage charged in the storage capacitor Cst is stably maintained without being resupplied to the second data line D2.

As described above, in the driving method according to the second embodiment of the present invention, since the data signal supplied to one output line O can be supplied to i data lines D, the manufacturing cost can be reduced. There is this. In addition, in the present invention, the scan signal is supplied for one horizontal period, and the control signals CS1, CS2, and CS3 are sequentially supplied during the scan signal period. In addition, the supply time of the data signal may be improved by supplying a desired data signal during a period in which the control signal is supplied, thereby sufficiently securing the charging time of the pixel 140.

In the present invention, the reset voltage Vr supplied to the output line O allows the pixels to be driven stably. In detail, the second transistor M2 included in each of the pixels 140R, 140G, and 140B is turned on during the scan signal period. Here, if the data lines D1 to D3 are not initialized by the reset voltage Vr, the green pixel 140G and the first control signal CS1 are supplied while the first switching device T1 is turned on. The pixel voltage of the blue pixel 140B is changed. In other words, the voltage of the previous data signal that was charged in the data capacitor CdataB via the second transistor M2 of the blue pixel 140B during the period in which the first control signal CS1 is supplied is the blue pixel 140B. Is supplied. Then, the voltage that was initialized by the initialization voltage Vint is changed to the voltage of the previous data signal, thereby causing a problem in that it cannot be driven stably. For example, even when the third control signal CS3 is supplied and the third switching device T3 is turned on, the voltage of the blue pixel 140B may be maintained at the voltage of the previous data signal.

Therefore, in the present invention, the reset signal Vr is supplied to overlap the control signals CS1, CS2, and CS3 for some period so that the desired voltage can be charged in the pixels 140. On the other hand, since the pixel 140 of the present invention shown in FIG. 5 is additionally connected to the wiring connected to the initialization power supply Vint, the structure is complicated. In order to overcome this problem, the pixel according to the second embodiment of the present invention is proposed as shown in FIG. 8.

8 is a circuit diagram illustrating a pixel according to a second exemplary embodiment of the present invention. In FIG. 8, for convenience of description, the pixel connected to the n−1 th scan line Sn−1 and the n th scan line Sn is illustrated.

Referring to FIG. 8, the pixel 140 according to the second embodiment of the present invention includes an organic light emitting diode OLED, a data line D, a scan line Sn-1, Sn, and a light emission control line En. And a pixel circuit 142 'for controlling the organic light emitting diode OLED.

The anode electrode of the organic light emitting diode OLED is connected to the pixel circuit 142 ', and the cathode electrode is connected to the second power source ELVSS. The second power supply ELVSS is set to a voltage lower than the first power supply ELVDD, for example, a ground voltage. The organic light emitting diode (OLED) generates one of red, green, and blue light corresponding to the amount of current supplied from the pixel circuit 142 '.

The pixel circuit 142 'includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a storage. Capacitor Cst is provided. Here, although the first to sixth transistors M6 are illustrated as P-type MOSFETs in FIG. 8, the present invention is not limited thereto.

The first electrode of the first transistor M1 is connected to the first power supply ELVDD via the fourth transistor M4, and the second electrode is connected to the organic light emitting diode OLED via the fifth transistor M5. Connected. The gate electrode of the first transistor M1 is connected to one terminal of the storage capacitor Cst. The first transistor M1 supplies a current corresponding to the voltage charged in the storage capacitor Cst to the organic light emitting diode OLED.

The first electrode of the third transistor M3 is connected to the first electrode of the first transistor M1, and the second electrode is connected to the gate electrode of the first transistor M1. The gate electrode of the third transistor M3 is connected to the nth scan line Sn. The third transistor M3 is turned on when the scan signal is supplied to the nth scan line Sn to connect the first transistor M1 in the form of a diode.

The first electrode of the second transistor M2 is connected to the data line D, and the second electrode is connected to the second electrode of the first transistor M1. The gate electrode of the second transistor M2 is connected to the nth scan line Sn. The second transistor M2 is turned on when the scan signal is supplied to the nth scan line Sn to supply the data signal supplied to the data line D to the second electrode of the first transistor M1. .

The first electrode of the fourth transistor M4 is connected to the first power source ELVDD, and the second electrode is connected to the first electrode of the first transistor M1. The gate electrode of the fourth transistor M4 is connected to the emission control line En. The fourth transistor M4 is turned on when the emission control signal is not supplied to electrically connect the first power source ELVDD and the first transistor M1.

The first electrode of the fifth transistor M5 is connected to the second electrode of the first transistor M1, and the second electrode is connected to the organic light emitting diode OLED. The gate electrode of the fifth transistor M5 is connected to the emission control line En. The fifth transistor M5 is turned on when the emission control signal is not supplied to electrically connect the first transistor M1 and the organic light emitting diode OLED.

The first electrode of the sixth transistor M6 is connected to the gate electrode of the first transistor M1, and the second electrode is connected to the data line D. The gate electrode of the sixth transistor M6 is connected to the n-1 th scan line Sn-1. The sixth transistor M6 is turned on when the scan signal is supplied to the n-th scan line Sn- 1 to initialize the gate electrode of the first transistor M1 to the reset voltage Vr.

9 is a diagram illustrating a connection structure between a pixel and a demultiplexer according to a second embodiment of the present invention. In FIG. 9, the pixel connected to the n-th scan line Sn-1 and the n-th scan line Sn is illustrated.

7 and 9, first, a scan signal is supplied to the n-th scan line Sn-1 (the previous scan line) and a light emission control signal is supplied to the n-th emission control line En. When the scan signal is supplied to the n-th scan line Sn-1, the sixth transistor M6 included in each of the pixels 140R, 140G, and 140B is turned on. When the emission control signal is supplied to the nth emission control line En, the fourth transistor M4 and the fifth transistor M5 are turned off.

Meanwhile, the first control signal CS1, the second control signal CS2, and the third control signal CS3 are sequentially supplied during the period in which the scan signal is supplied to the n−1 th scan line Sn−1. When the first control signal CS1 is supplied, the first switching device T1 is turned on to supply the red data signal R and the reset voltage Vr sequentially. At this time, since the sixth transistor M6 included in the red pixel 140R is set to be turned on, one terminal of the gate electrode and the storage capacitor Cst of the first transistor M1 is reset to the reset voltage Vr. It is initialized. In other words, one terminal of the gate electrode and the storage capacitor Cst of the first transistor M1 included in the red pixel 140R is connected to the reset voltage by the reset voltage Vr supplied after the red data signal R. Is changed to (Vr).

Similarly, when the second control signal CS2 is supplied, one terminal of the gate electrode and the storage capacitor Cst of the first transistor M1 included in the green pixel 140G is initialized to the reset voltage Vr. When the third control signal CS3 is supplied, one terminal of the gate electrode and the storage capacitor Cst of the first transistor M1 included in the blue pixel 140B is initialized to the reset voltage Vr.

Thereafter, the scan signal is supplied to the nth scan line Sn (the current scan line). When the scan signal is supplied to the nth scan line Sn, the second transistor M2 and the third transistor M3 included in each of the pixels 140R, 140G, and 140B are turned on. In addition, the first switching element T1, the second switching element T2, and the first switching element CS1 through the first control signal CS1 to the third control signal CS3 during the period in which the scan signal is supplied to the nth scan line Sn. The three switching elements T3 are sequentially turned on.

When the first switching device T1 is turned on, the red data signal R, which is supplied to the first output line O1, is supplied to the first data line D1. The red data signal R supplied to the first data line D1 is supplied to the pixel 140R via the second transistor M2 of the red pixel 140R. In this case, since the gate electrode of the first transistor M1 of the red pixel 140R is initialized to the reset voltage Vr, the first transistor M1 of the red pixel 140R is turned on. When the first transistor M1 of the red pixel 140R is turned on, the red data signal R passes through the first transistor M1 and the third transistor M3 of the red pixel 140R through the storage capacitor Cst. It is supplied to one terminal of). At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal and the threshold voltage of the first transistor M1.

Thereafter, the reset voltage Vr is supplied to the output line O1 to overlap the first control signal CS1 for a period of time. The reset voltage Vr supplied to the output line O1 changes the voltage of the parasitic capacitor CdataR of the first data line D1 to the voltage of the reset voltage Vr. Meanwhile, even when the parasitic capacitor CdataR of the first data line D1 is changed to the voltage of the reset voltage Vr, the voltage charged in the red pixel 140R is stably maintained. In other words, since the first transistor M1 is connected in the form of a diode, the voltage charged in the storage capacitor Cst is stably maintained without being resupplied to the first data line D1.

When the second switching device T2 is turned on by the second control signal CS2, the green data signal G, which is supplied to the first output line O1, is supplied to the second data line D2. The green data signal G supplied to the second data line D2 is supplied to the pixel 140G via the second transistor M2 of the green pixel 140G. In this case, since the gate electrode of the first transistor M1 of the green pixel 140G is initialized by the reset voltage Vr, the first transistor M1 of the green pixel 140G is turned on. When the first transistor M1 of the green pixel 140G is turned on, the green data signal G passes through the first transistor M1 and the third transistor M3 of the green pixel 140G through the storage capacitor Cst. It is supplied to one terminal of). At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal and the threshold voltage of the first transistor M1.

Thereafter, the reset voltage Vr is supplied to the output line O1 to overlap the second control signal CS2 for a period of time. The reset voltage Vr supplied to the output line O1 changes the voltage of the parasitic capacitor CdataG of the second data line D2 to the voltage of the reset voltage Vr. Meanwhile, even when the parasitic capacitor CdataG of the second data line D2 is changed to the voltage of the reset voltage Vr, the voltage charged in the green pixel 140G is stably maintained. In other words, since the first transistor M1 is connected in the form of a diode, the voltage charged in the storage capacitor Cst is stably maintained without being resupplied to the second data line D2.

When the third switching device T3 is turned on by the third control signal CS3, the blue data signal B supplied to the first output line O1 is supplied to the third data line D3. The blue data signal B supplied to the third data line D3 is supplied to the pixel 140B via the second transistor M2 of the blue pixel 140B. In this case, since the gate electrode of the first transistor M1 of the blue pixel 140B is initialized by the reset voltage Vr, the first transistor M1 of the blue pixel 140B is turned on. When the first transistor M1 of the blue pixel 140B is turned on, the blue data signal B passes through the first transistor M1 and the third transistor M3 of the blue pixel 140B and the storage capacitor Cst. It is supplied to one terminal of). At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal and the threshold voltage of the first transistor M1.

Thereafter, the reset voltage Vr is supplied to the output line O1 to overlap the third control signal CS3 for a period of time. The reset voltage Vr supplied to the output line O1 changes the voltage of the parasitic capacitor CdataG of the third data line D3 to the reset voltage Vr. Meanwhile, even when the parasitic capacitor CdataG of the third data line D3 changes to the voltage of the reset voltage Vr, the voltage charged in the blue pixel 140B is stably maintained. In other words, since the first transistor M1 is connected in the form of a diode, the voltage charged in the storage capacitor Cst is stably maintained without being resupplied to the second data line D2.

As described above, in the present invention, since the data signal supplied to one output line O1 can be supplied to i data lines D, manufacturing cost can be reduced. In addition, in the present invention, since the control signals CS1, CS2, and CS3 are supplied during the scan signal supply period, the supply time of the data signal can be improved, thereby sufficiently securing the charging time of the pixel 140. Can be. Since the pixel according to the second embodiment of the present invention is initialized by the reset voltage Vr supplied to the data line D, the initialization power supply line can be omitted, thereby improving the aperture ratio.

The above detailed description and drawings are merely exemplary of the present invention, but are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the meaning or claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, according to the organic light emitting display device and the driving method thereof according to the embodiment of the present invention, since the data signals supplied to one output line are supplied to the plurality of data lines, the manufacturing cost can be reduced. have. In addition, in the present invention, since the reset voltage is supplied after the data signals are supplied, the scan signal and the control signals can be superimposed and thus, the charging time of the pixel can be improved. In addition, in the present invention, since the pixel is initialized using the reset voltage, the structure of the pixel can be simplified.

Claims (17)

Supplying i (i is a natural number) data signals and i reset voltages so as not to overlap each other to each output line during the horizontal period; Supplying i data signals and i reset voltages supplied to the output lines to i data lines using a demultiplexer; Charging a voltage corresponding to the data signal to each of the pixels connected to the i data lines while a scan signal is supplied to a current scan line; And emitting light from the pixels in response to the charged voltage. The method of claim 1, And a reset voltage is supplied to each of the data lines after the data signal is supplied to initialize the voltages of the data capacitors that are equivalently formed on each of the data lines. delete The method of claim 1, The pixels are initialized by an initialization power supply connected to each of the pixels during a period in which a scan signal is supplied to a previous scan line, and charged with a voltage corresponding to a data signal supplied to the pixels during a period in which a scan signal is supplied to the current scan line. A method of driving an organic light emitting display device, characterized in that. The method of claim 4, wherein And the initialization power supply is set to a voltage value lower than the voltage of the data signal. The method of claim 1, The pixels are initialized by the reset voltage during the period in which the scan signal is supplied to the previous scan line, and the pixel is charged with a voltage corresponding to the data signal supplied to the pixel during the period in which the scan signal is supplied to the current scan line. A method of driving an electroluminescent display. The method of claim 6, And the reset voltage is set to a voltage value lower than the voltage of the data signal. The method of claim 1, The demultiplexer includes i switching elements between the output line and the i data lines, and the switching elements are sequentially turned on during the period in which the scan signal is supplied. Way. A data driver for supplying i (i is a natural number) data signals and i reset voltages so as not to overlap each other with each output line in a horizontal period; A demultiplexer provided for each of the output lines to supply the i data signals and i reset voltages to i data lines; A scan driver for sequentially supplying scan signals to scan lines every horizontal period; Pixels connected to the data line and the scan line; Each of the pixels is initialized by the reset voltage when the scan signal is supplied to the previous scan line and is charged with a voltage corresponding to the data signal when the scan signal is supplied to the current scan line. . The method of claim 9, And the data driver alternately supplies the data signal and the reset voltage to the output line. delete The method of claim 9, And each of the demultiplexers comprises i switching elements positioned between the output line and the i data lines. The method of claim 12, And a demultiplexer controller for sequentially supplying i control signals in order to sequentially turn on the switching elements during the scanning signal supply period. The method of claim 9, Each of the pixels An organic light emitting diode; A storage capacitor for charging a voltage corresponding to the data signal; A first transistor for supplying a current corresponding to the voltage charged in the storage capacitor to the organic light emitting diode; A second transistor connected to the data line, the current scan line, and the second electrode of the first transistor and turned on when a scan signal is supplied to the current scan line; A third transistor connected between the first electrode and the gate electrode of the first transistor and turned on when a scan signal is supplied to the current scan line; And a sixth transistor connected between the gate electrode of the first transistor and the data line and turned on when a scan signal is supplied to the previous scan line. The method of claim 14, A fourth transistor connected between the first electrode of the first transistor and the storage capacitor; And a fifth transistor connected between the second electrode of the first transistor and the organic light emitting diode. The method of claim 15, And the fourth transistor and the fifth transistor are turned off when the emission control signal is supplied from the scan driver, and are turned on for another period of time. The method of claim 16, And the emission control signal is superimposed with a scan signal supplied to the previous scan line and the current scan line.

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