KR100783999B1 - The method for reading a non-volatile memory device - Google Patents

Abstract

A method for reading a nonvolatile memory device is provided to reduce coupling noise by dividing each page buffer into an odd-numbered page buffer group and an even-numbered page buffer group and separating a sensing period of a voltage level of a first bit line of each page buffer group temporarily during a read operation period of a memory cell. According to a method for reading a nonvolatile memory device including a number of page buffers connected to a pair of bit lines of a memory cell array, a specific word line is turned on. A drain selection transistor is turned on. A first voltage is applied to a gate of a bit line selection transistor connected between a sensing line and a first bit line of each page buffer. A source selection transistor is turned on and then is turned off after a constant time. After the source selection transistor is turned off, a second voltage is applied to the gate of the bit line selection transistor connected to the first bit line of an odd-numbered page buffer and a read signal is applied to the corresponding page buffer. After the source selection transistor is turned off, the second voltage is applied to the gate of the bit line selection transistor connected to a first bit line of an even-numbered page buffer and a read signal is applied to the corresponding page buffer.

Description

The method for reading a non-volatile memory device

1 is a block diagram showing a configuration of a nonvolatile memory device to which the present invention is applied.

2 is a circuit diagram showing a configuration of a nonvolatile memory device to which the present invention is applied.

3 is a timing diagram illustrating a read operation of a nonvolatile memory device according to an embodiment of the present invention.

Description of the main parts of the drawing

110: memory cell array

120, 122, 124, 126: page buffer

130, 132, 134, 136: bit line selector

140, 142, 144, 146: precharge part

150, 152, 154, 156: main register

160, 162, 164, 166: cache register

170: column selector

The present invention relates to a method of driving a page buffer included in a nonvolatile memory device, and more particularly, to reduce sensing error due to coupling noise between sensing lines in an operation of reading data of a specific cell of the memory device. It relates to a reading method.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function that requires rewriting data at regular intervals. NAND-type flash memory of the nonvolatile memory device uses a page buffer to store a large amount of information in a short time and to verify normal program and erase. Conventional page buffers consist of a single register to temporarily store data, but recently, dual registers are used to increase the speed of data programs.

On the other hand, as the memory capacity becomes larger and the pitch of the bit lines becomes narrower, the page buffers are more densely arranged. As a result, the pitch of the sensing lines that sense the voltage level of the bit lines also becomes narrower, resulting in a coupling between the sensing lines. Ring noise is a major problem. That is, in the case of a programmed cell, the sensing line maintains a high level of voltage, whereas in the case of an erased cell, the sensing line transitions from a high level to a low level as a current flows between a bit line and a string line of a memory cell. Although the cell is programmed under the influence of the adjacent sensing line due to the generation of coupling noise between the sensing lines, the voltage state of the sensing line is reduced to a certain degree so that the erased cell may be erroneously read.

In order to solve the above-described problem, the read method of the present invention divides each page buffer into an odd-numbered page buffer group and an even-numbered page buffer group in a read operation period of a memory cell, and applies a voltage to the first bit line of each page buffer group. By reducing the detection interval of the level in time to reduce the coupling noise, the evaluation time of the bit line voltage between each buffer group is the same so that the deviation of the current flowing through the bit line and the cell string during the evaluation time for each page buffer group It is an object of the present invention to provide a method of reducing reading.

The present invention for achieving the above object is a plurality of cell strings are connected to a plurality of memory cells in series, a plurality of bit lines connected through the cell string and the drain select transistor, connected through the cell string and the source select transistor Reading a nonvolatile memory device including a common source line, a memory cell array including a plurality of word lines connected to a gate of the cell, and a plurality of page buffers respectively connected to a pair of bit lines of the memory cell array. A method comprising: selecting a particular wordline, turning on the drain select transistor, and applying a first voltage to a gate of a bitline select transistor connected between a first bitline and a sensing line of each page buffer. Applying, turning off the source select transistor after a predetermined time and turning off the source select transistor; A first sensing step of turning off a source select transistor and applying a read signal to a corresponding page buffer while applying a second voltage to a gate of the bit line select transistor connected to a first bit line of an odd-numbered page buffer; And a second sensing step of applying a read signal to the page buffer while turning off the source select transistor while applying a second voltage to the gate of the bit line select transistor connected to the first bit line of the even-numbered page buffer. It is characterized by.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a configuration of a nonvolatile memory device to which the present invention is applied. The nonvolatile memory device includes a memory cell array 110, page buffers 120, 122, 124, and 126, and a column selector 170, and each page buffer 120, 122, 124, and 126 is a bit line. Selector 130, 132, 134, 136, precharger 140, 142, 144, 146, main registers 150, 152, 154, 156, cache registers 160, 162, 164, 166 do.

Although the detailed configuration of the memory cell array 110 is not shown, a plurality of memory cells for storing data, a plurality of cell strings in which a plurality of cells are connected in series, and a plurality of bit lines connected to a common drain terminal of the cell string And a common source line connected to the common source terminal of the cell string, and a plurality of word lines connected to the cell in a direction perpendicular to the bit line.

The bit lines BLe_1,..., Ble_2n-1 represent first bit lines of odd-numbered page buffers among page buffers connected to memory cells constituting one page, respectively. .BLe_2n + 1) denotes first bit lines of even-numbered page buffers, respectively. Similarly, the bit lines BLo_1, ..., BLo_2n-1 represent the second bit lines of the odd-numbered page buffers among the page buffers, and the bit lines BLo_2, ..., BLo_2n + 1 respectively represent the page buffers. Represents a second bit line of even-numbered page buffers.

The page buffer 120 is connected to a bit line of the memory cell array to write data to or read data from the memory cell array. The page buffer 120 reads the memory cell array through a pair of bit lines BLe_1 and BLo_1. And a column selector 170 that selects to write / read data of a specific bit line. The bit line selector 130 selectively adjusts the connection between the page buffer 120 and the specific bit lines BLe_1 and BLo_1. The precharge unit 140 selectively connects the power supply voltage VCC (not shown) and the sensing line SO_1 to precharge the sensing line SO_1 to the power supply voltage VCC. The main register 150 is connected between the sensing line SO_1 and the input / output terminal, and includes a latch (not shown) for temporarily storing data. The main register 150 includes data for writing, reading, copying back or verifying a page buffer. Temporarily stores the role. The cache register 160 is connected between the sensing node SO_1 and the input / output terminal and includes a latch (not shown) that temporarily stores data. However, unlike the main register 160, the cache register 160 is inactive in read and verify operations. do.

Remaining page buffers 122, 124, 126, bit line selector 132, 134, 136, precharge units 142, 144, 146, main registers 152, 154, 156, cache registers 162, 164 166 also performs the same operation as described above.

In the present invention, each page buffer is classified into an odd-numbered page buffer group and an even-numbered page buffer group in a section for detecting a voltage level of a bit line or a sensing line during a read operation of a page buffer for reading data stored in a memory cell. Each of the first bit line BLe connected to the odd-numbered page buffer group and the first bit line BLe connected to the even-numbered page buffer group have two sensing intervals separated in time. Its content will be described in detail with reference to the drawings.

2 is a circuit diagram showing a configuration of a nonvolatile memory device to which the present invention is applied. For simplicity, only the first bit line BLe_1 of the odd-numbered page buffer and the first bit line Ble_2 of the even-numbered page buffer are shown. Also, in the page buffers connected to each bit line, the first and second bit lines Only the first bit line selection transistors BSLe_1 and BSLe_2 and the main registers constituting each page buffer among the transistors for selection are shown.

The transistors N201 and N202 are connected between the cell strings SL1 and SL2 having the memory cell transistors connected in series and a bit line. In response to the signal DSL applied to the gate, the connection between the bit lines BLe_1 and BLe_2 and the cell strings SL1 and SL2 are respectively controlled.

Transistors N203 and N204 are connected between the cell strings SL1 and SL2 and a ground power source. In response to the signal SSL applied to the gate, the cell strings SL1 and SL2 are connected to the ground power source. Particularly, in the present invention, the evaluation time of each bit line BLe_1 and BLe_2 is the same by adjusting the signal SSL applied to the gate, which will be described in detail later.

The transistors N211 and N221 are connected between the bit lines BLe_1 and BLe_2 and the sensing lines SO_1 and SO_2. In response to the bit line selection signals BSLe_1 and BSLe_2 applied to the gate, the connection between the bit lines BLe_1 and BLe_2 and the sensing lines SO_1 and SO_2 is controlled.

The PMOS transistors P210 and P220 are connected between the sensing lines SO_1 and SO_2 and the connection node of the gates of the transistors N214 and N224 and the power supply voltage. The power supply voltage VCC is supplied to the sensing lines SO_1 and SO_2 and the gates of the transistors N214 and N224 in response to the precharge signals PRECHb_1 and PRECHb_2 applied to the gates.

Transistors N212 and N222 are connected between the input terminals of the inverters IV210 and IV220 and the input terminals Q_1b and Q_2b of the latch composed of two inverters and the sensing lines SO_1 and SO_2. The connection between the sensing lines SO_1 and SO_2 and the input terminals Q_1b and Q_2b of the latch is controlled in response to the copyback signals COPYBACK_1 and COPYBACK_2 applied to the gate.

The transistors N213 and N223 are connected between the connection nodes of the sensing lines SO_1 and SO_2 and the bit lines BLe_1 and BLe_2 and the connection nodes of the transistors N217 and N227 and output terminals of the inverters IV210 and IV220. In response to the program signals PGM_1 and PGM_2 applied to the gate, the connection between the sensing lines SO_1 and SO_2 and the input terminals Q_1b and Q_2b of the latch is controlled.

Transistors N214 and N224 are connected between the input terminals Q_1b and Q_2b of the latch and the drains of the transistors N215 and N225. The ground voltage is applied to the input terminals Q_1b and Q_2b of the latch according to the potential state of the sensing lines SO_1 and SO_2 applied to the gate.

Transistors N215 and N225 are connected between the source of transistors N214 and N224 and a ground power supply. The ground voltage is applied to the connection nodes Q_1b and Q_2b in response to the read signals READ_1 and READ_2 applied to the gate.

The inverters IV210 and IV220 are connected between the transistors N213 and N223 and the connection nodes of the transistors N217 and N227 and the input terminals Q_1b and Q_2b of the latches. When the transistors N213 and N223 are turned on, the potentials of the input terminals Q_1b and Q_2b of the latch are inverted and transferred to the memory cell array.

Inverters IV212 and IV222 and IV214 and IV224 are connected to an input terminal and an output terminal, respectively, to form a latch. Q_1b and Q_2b, and the connection node between the output terminal of the inverters IV212 and IV222 and the input terminal of the inverters IV214 and IV224 becomes the output terminals Q_1 and Q_2 of the latch.

Transistors N216 and N226 are connected between the output terminals Q_1 and Q_2 of the latch and the ground power supply. The ground voltage is applied to the output terminals Q_1 and Q_2 of the latch in response to the reset signals RESET_1 and RESET_2 applied to the gate.

Transistors N217 and N227 are connected between the connection nodes of the inverters IV210 and IV220 and the transistors N213 and N223 and an input / output terminal (not shown). In response to the page buffer detection signals PBDO_1 and PBDO_2, the input terminals Q_1b and Q_2b of the latch are connected to the input / output terminals.

The operation of the above-described circuit will be described in detail with reference to the timing diagram.

3 is a timing diagram illustrating a read operation of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIGS. 2 and 3, an embodiment of the present invention will be described. First, in a period T1, high level reset signals RESET_1 and RESET_2 are applied to the gates of the transistors N216 and N226, respectively. The output terminals Q_1 and Q_2 are initialized to the low level. Also, although not shown in FIG. 3, a specific word line to which data is to be read is selected. In general, a low level signal is applied to a selected word line and a high level signal is applied to an unselected word line.

In the period T2, the drain select transistors N201 and N202 are turned on to connect the bit lines BLe and BLo of the page buffers connected to the memory cell array to the cell strings SL1 and SL2, and the first and second page buffers are connected. One bit line is connected to a sensing line connected to a power supply voltage, respectively, to be precharged. To this end, a high level signal DSL is applied to the gates of the drain select transistors N201 and N202 connected to the cell strings SL1 and SL2 to connect the specific bit lines to the cell strings SL1 and SL2.

In addition, the PMOS transistors P210 and P220 are applied by applying low-level precharge signals PRECHb_1 and PRECHb_2 to gates of the PMOS transistors P210 and P220 connected between the sensing lines SO_1 and SO_2 and the power supply voltage source, respectively. By turning on, a power supply voltage is applied to each of the sensing lines SO_1 and SO_2. At the same time, a bit line selection signal BSLe_1 having a high level voltage V1 at the gate of the bit line selection transistors N211 and N221 connected between the first bit lines BLe_1 and BLe_2 and the sensing lines SO_1 and SO_2. , BSLe_2 is applied to apply the high level voltages of the sensing lines SO_1 and SO_2 to the bit lines BLe_1 and BLe_2. Through this process, each of the bit lines BLe_1 and BLe_2 is precharged to voltages V1 -Vt minus the threshold voltage Vt from the voltage V1.

In the period T3, the connection between the first bit lines BLe_1 and BLe_2 and the sensing lines SO_1 and SO_2 is cut off, and the cell strings SL1 and SL2 are connected to the common source line for a predetermined time, so that each bit line ( The voltage levels of BLe_1 and BLe_2 are evaluated.

The bit lines BLE_1 and BLe_2 are floated by turning off the transistors N211 and N221 by transitioning the bit line selection signals BSLe_1 and BSLe_1 to a low level. In addition, the high level signal DSL is continuously applied to the gates of the common drain terminals N201 and N202 of the cell strings SL1 and SL2, and the common source terminals N203 and N204 of the cell strings SL1 and SL2 are continuously applied. The high level signal SSL is applied to the gate for a predetermined period of time. If the memory cell of the selected word line is a programmed cell, the voltage level of the precharged bit line is maintained. If the memory cell is an erased cell, current flows from the bit line to the string line of the memory cell. Is reduced. In this way, it is possible to determine whether data is stored in the memory cell according to whether the voltage level of the precharged bit line changes.

In FIG. 3, the voltage level of the bit line BLe-1 transitions to a low level, and the voltage level of the bit line BLe_2 remains unchanged. Based on this, the cell string connected to the bit line BLe-1 is based on this. The memory cell of the selected word line of SL1 is an erased cell, and the memory cell of the selected word line of the cell string SL2 connected to the bit line BLe-2 is a programmed cell.

Meanwhile, in the present invention, when detecting the voltage level of each page buffer bit line, the first bit line of the odd-numbered page buffer and the first bit line of the even-numbered page buffer have a detection interval separated in time. It features. However, different sensing periods, but the interval for evaluating the voltage level of each bit line is the same as the characteristic component. That is, as described above, the high level signal SSL is applied to the gates of the transistors N203 and N204 for both bit lines BLe_1 and BLe_2 for the same time, and then the transistors N203 and N204 are turned off to thereby turn off the bit lines BLe_1. , BLe_2 blocks the current flowing to the cell strings SL1 and SL2. By doing so, it is possible to minimize deviations of currents flowing through the bit lines BLe_1 and BLe_2 and the cell strings SL1 and SL2 during the evaluation time for each page buffer group.

The sections T4 and T6 are sections in which the voltage levels of the bit lines BLe_1 and BLe_2 are sensed through the sensing lines SO_1 and SO_2 and data is stored in the latches according to the values.

In the period T4, a high level voltage V2 is applied to a gate of the bit line select transistor N211 connected to the first bit line BLe_1 of odd-numbered page buffer groups among the page buffers. A read signal is applied to the page buffer to sense the voltage level of each bit line. The voltage V2 applied as the bit line selection signal BSLe_1 is smaller than the voltage V1 applied in the section T2, but applies a voltage V2 for turning on the transistor N211. Although not shown in the drawing, the bit line selection signals BSLe_3, ..., BSLe_2n-1 at the same time with respect to the first bit lines BLe_3, ..., Ble_2n-1 of the other odd-numbered page buffer groups. Is shifted to a high level to connect each bit line (BLe_3, ..., BLe_2n-1) and the sensing lines (SO_3, ... SO_2n-1).

In addition, the high level precharge signal PRECHb_1 is applied to turn off the transistor P210 so that the sensing line SO_1 changes according to the voltage level of the bit line BLe_1. In FIG. 3, when the selected memory cell is an erased cell, the voltage level of the sensing line SO_1 is shifted to the low level.

Meanwhile, at this time, the high level signal READ_1 is applied to the gate of the transistor N215. In FIG. 3, since the voltage level of the sensing line SO_1 is low level, the transistor N214 is not turned on and thus the input terminal of the latch ( No ground voltage source is applied to Q_1b). If the voltage level of the sensing line SO_1 is high, that is, if the selected memory cell is a programmed cell, the transistor N214 is turned on so that the ground voltage source is applied to the input terminal Q_1b of the latch by the transistor N215. do.

The section T5 is a section that temporally separates the section T4 and the section T6.

In the section T6, the same operation as the section T4 is performed, but only the target on which the operation is performed is different.

A read signal is applied to the corresponding page buffer while applying a high level voltage V2 to the gate of the bit line select transistor N221 connected to the first bit line BLe_1 of the even-numbered page buffer groups among the page buffers. To sense the voltage level of each bit line. The voltage V2 applied as the bit line selection signal BSLe_2 is smaller than the voltage V1 applied in the section T2, but applies a voltage V2 for turning on the transistor N221. Although not shown in the drawing, the bit line selection signals BSLe_4, ..., BSLe_2n are set to the high level at the same time with respect to the first bit lines Ble_4,..., BLe_2n of the other even-numbered page buffer groups. Transitions are made to connect the bit lines Ble_4, ..., Ble_2n and the sensing lines SO_4, ... SO_2n.

In addition, the high level precharge signal PRECHb_2 is applied to turn off the transistor P220 so that the sensing line SO_2 is changed according to the voltage level of the bit line BLe_2. In FIG. 3, when the selected memory cell is a programmed cell, the voltage level of the sensing line SO_2 is maintained at a high level. The operation of changing data stored in the latch according to the state of the sensing line is as described above.

In the above embodiment, the first bit line of the odd-numbered page buffer group is configured as a method having a sensing period first. However, the first bit line of the even-numbered page buffer group may be configured as a method having a sensing period first for the first bit line of an even-numbered page buffer group. Can be.

In addition, although not shown in FIG. 3, a read operation on the second bit lines BLO_1, BLo_2,... BLo_2n of each page buffer group may be performed on the first bit lines BL_1, BLe_2, ... BLe_2n. Similar to the read operation, the sensing period is first performed on the second bit line of the odd-numbered page buffer group, and the sensing period is later performed on the second bit line of the even-numbered page buffer group. In addition, according to the selection, the second bit line of the even-numbered page buffer group may be configured to have a sensing period first.

In addition, the read operation may be performed on the first bit line after the read operation is performed on the second bit line of each page buffer group according to the selection.

The above content will be described in a sequential order according to the flow of time.

4 is a flowchart illustrating a read operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

First, the latch is initialized by applying a reset signal to the registers of the entire page buffer (step 410).

Next, although a specific word line, which is not shown in FIG. 3, is selected, the low level signal is applied to the selected word line, and the high level signal is applied to the unselected word line. (Step 420).

Next, the sensing line included in each page buffer is precharged to a high level (step 430).

Next, a first voltage is supplied to a bit line select transistor connected to the first bit line of each page buffer to precharge the first bit line (step 440).

Next, the source select transistor connected between the common drain terminal and the bit line of each cell string is turned on only for a predetermined time to evaluate the voltage level of the first bit line (step 450).

Next, a second voltage is supplied to a bit line selection transistor connected to a first bit line of an odd-numbered page buffer among all page buffers connected to the memory cell array to sense the voltage level of the bit line through the sensing line. A data read signal is supplied to the page buffer (step 460).

Next, a second voltage is supplied to a bit line selection transistor connected to a first bit line of an even-numbered page buffer among all page buffers connected to the memory cell array to sense the voltage level of the bit line through the sensing line. The data read signal is supplied to the page buffer (step 470).

After performing the above steps, the data of each memory cell is read through the second bit line of each page buffer, and the method is almost similar to the read operation through the first bit line.

According to the above configuration, the sensing intervals for the first bit line of the odd-numbered page buffer group and the first bit line of the even-numbered page buffer group are temporally separated, thereby reducing coupling noise of the sensing line, respectively. The time performed for the evaluation of the bit line voltage level performed before the same may be configured to reduce the deviation of the current flowing through the bit line and the cell string during the evaluation time.

Claims (6)

A plurality of cell strings in which a plurality of memory cells are connected in series, a plurality of bit lines connected through the cell string and a drain select transistor, a common source line connected through the cell string and a source select transistor, and a gate of the cell A memory cell array comprising a plurality of word lines, A read method of a nonvolatile memory device including a plurality of page buffers connected to a pair of bit lines of the memory cell array, respectively. Selecting a specific wordline, Turning on the drain select transistor; Applying a first voltage to a gate of a bit line select transistor connected between a first bit line and a sensing line of each page buffer; Turning off the source select transistor after a predetermined time, and A first sensing step of turning off the source select transistor and applying a read signal to a corresponding page buffer while applying a second voltage to a gate of the bit line select transistor connected to a first bit line of an odd-numbered page buffer; A second sensing step of turning off the source select transistor and applying a read signal to a corresponding page buffer while applying a second voltage to a gate of the bit line select transistor connected to a first bit line of an even-numbered page buffer Read method of a nonvolatile memory device comprising a. The nonvolatile memory device of claim 1, wherein the applying of the first voltage comprises controlling a gate of a transistor connected between the sensing line and a power supply voltage source to apply a power supply voltage to the sensing line. How to read the device. The method of claim 1, wherein applying the first voltage comprises stopping supply of the first voltage before performing the step of turning on the source select transistor. Way. The method of claim 1, wherein the second sensing step is performed after the first sensing step is performed. The method of claim 1, wherein the second sensing step is performed before the first sensing step is performed. The method of claim 1, further comprising: selecting a specific word line after the first and second sensing steps are performed; Turning on the drain select transistor; Applying a first voltage to a gate of a bit line select transistor connected between a second bit line and a sensing line of each page buffer; Turning on the source select transistor for a predetermined time; A third sensing step of applying a read signal to a corresponding page buffer while applying a second voltage to a gate of the bit line select transistor connected to a second bit line of an odd-numbered page buffer; And a fourth sensing step of applying a read signal to a corresponding page buffer while applying a second voltage to a gate of the bit line select transistor connected to a second bit line of an even-numbered page buffer. Read method.

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