KR100782790B1 - Semiconductor device and fabrication method of thereof - Google Patents

Semiconductor device and fabrication method of thereof Download PDF

Info

Publication number
KR100782790B1
KR100782790B1 KR1020020045019A KR20020045019A KR100782790B1 KR 100782790 B1 KR100782790 B1 KR 100782790B1 KR 1020020045019 A KR1020020045019 A KR 1020020045019A KR 20020045019 A KR20020045019 A KR 20020045019A KR 100782790 B1 KR100782790 B1 KR 100782790B1
Authority
KR
South Korea
Prior art keywords
dielectric layer
forming
insulating film
semiconductor device
lower electrode
Prior art date
Application number
KR1020020045019A
Other languages
Korean (ko)
Other versions
KR20040011247A (en
Inventor
조경수
Original Assignee
동부일렉트로닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 동부일렉트로닉스 주식회사 filed Critical 동부일렉트로닉스 주식회사
Priority to KR1020020045019A priority Critical patent/KR100782790B1/en
Publication of KR20040011247A publication Critical patent/KR20040011247A/en
Application granted granted Critical
Publication of KR100782790B1 publication Critical patent/KR100782790B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor

Abstract

금속/ 절연체/ 금속 (MIM) 구조의 커패시터를 포함하는 반도체 소자 및 그 제조방법에 관한 것으로, 그 목적은 홀 형성을 위한 산화막 식각시 하부전극이 손상되는 언더컷으로 인해 커패시터가 파괴되는 것을 방지하는 데 있다. 이를 위해 본 발명에서는 반도체 기판의 구조물 상에 하부절연막을 형성하는 단계; 하부절연막 상에 소정폭의 하부전극을 형성하고, 하부전극의 적어도 일부분 상에 제1유전체층 및 제2유전체층을 형성하는 단계; 제2유전체층을 포함하여 하부절연막의 상부 전면에 층간절연막을 형성하는 단계; 층간절연막을 소정폭으로 식각하여, 제2유전체층의 상면을 일부 노출시키는 비아홀을 형성하는 단계; 비아홀의 내부에 상부전극을 매립하도록 형성하는 단계; 상부전극 및 층간절연막 상에 금속배선을 형성하는 단계를 포함하여 반도체 소자를 제조한다.The present invention relates to a semiconductor device including a capacitor having a metal / insulator / metal (MIM) structure, and a method of manufacturing the same, the purpose of which is to prevent the capacitor from being destroyed by an undercut that damages the lower electrode during the etching of an oxide for forming a hole. have. To this end, the present invention comprises the steps of forming a lower insulating film on the structure of the semiconductor substrate; Forming a lower electrode having a predetermined width on the lower insulating layer, and forming a first dielectric layer and a second dielectric layer on at least a portion of the lower electrode; Forming an interlayer insulating film on the entire upper surface of the lower insulating film including the second dielectric layer; Etching the interlayer insulating film to a predetermined width to form a via hole exposing a portion of the top surface of the second dielectric layer; Forming an upper electrode in the via hole; Forming a metal wiring on the upper electrode and the interlayer insulating film to manufacture a semiconductor device.

커패시터, 유전체층, 언더컷Capacitor, Dielectric Layer, Undercut

Description

반도체 소자 및 그 제조 방법 {Semiconductor device and fabrication method of thereof} Semiconductor device and fabrication method

도 1은 종래 반도체 소자를 도시한 단면도이다.1 is a cross-sectional view showing a conventional semiconductor device.

도 2a 내지 도 2c는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 금속/ 절연체/ 금속 (MIM) 구조의 커패시터를 포함하는 반도체 소자 및 그 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device comprising a capacitor of a metal / insulator / metal (MIM) structure and a method of manufacturing the same.

최근 등장하는 복합 반도체장치(MML:Merged Memory Logic)는 하나의 칩 내에 메모리 셀 어레이부, 예컨대 디램(DRAM :dynamic random access memory)과 아날로그 또는 주변회로가 함께 집적화된 소자이다. 이러한 복합 반도체장치의 등장으로 인해 멀티미디어 기능이 크게 향상되어 종전보다 반도체장치의 고집적화 및 고속화를 효과적으로 달성할 수 있게 되었다.BACKGROUND ART Recently, a merged memory logic (MML) is a device in which a memory cell array unit such as dynamic random access memory (DRAM) and an analog or peripheral circuit are integrated together in one chip. Due to the emergence of such composite semiconductor devices, multimedia functions have been greatly improved, and high integration and speed of semiconductor devices can be effectively achieved.

한편, 고속 동작을 요구하는 아날로그 회로에서는 고용량의 커패시터를 구현 하기 위한 반도체소자 개발이 진행 중에 있다. 일반적으로, 커패시터가 다결정실리콘(polysilicon)/ 절연체(insulator)/ 다결정실리콘(polysilicon)의 PIP 구조일 경우에는 상부전극 및 하부전극을 도전성 다결정실리콘으로 사용하기 때문에 상,하부전극과 유전체 박막 계면에서 산화반응이 일어나 자연산화막이 형성되어 전체커패시턴스의 크기가 줄어들게 되는 단점이 있다. Meanwhile, in an analog circuit requiring high speed operation, development of a semiconductor device for implementing a high capacity capacitor is underway. In general, when the capacitor is a PIP structure of polysilicon / insulator / polysilicon, the upper electrode and the lower electrode are used as the conductive polysilicon, so that the oxides are oxidized at the upper and lower electrodes and the dielectric thin film interface. The reaction occurs to form a natural oxide film has the disadvantage that the size of the total capacitance is reduced.

이를 해결하기 위해 커패시터의 구조를 금속/절연체/실리콘 (metal/insulator/silicon : MIS) 또는 금속/절연체/금속(metal/insulator/metal : MIM)으로 변경하게 되었는데, 그 중에서도 MIM 구조의 커패시터는 비저항이 작고 내부에 공핍(deplection)에 의한 기생 커패시턴스가 없기 때문에 고성능 반도체 장치에 주로 이용되고 있다.To solve this problem, the structure of the capacitor was changed to metal / insulator / silicon (MIS) or metal / insulator / metal (MIM). Because of its small size and no parasitic capacitance due to depletion inside, it is mainly used for high performance semiconductor devices.

그러면, 종래 반도체 소자 제조방법에 따라 MIM 구조의 커패시터를 제조하는 방법을 첨부된 도면을 참조하여 설명한다. 도 1은 종래 방법에 따라 형성된 반도체 소자를 도시한 단면도이다.Next, a method of manufacturing a capacitor having a MIM structure according to a conventional semiconductor device manufacturing method will be described with reference to the accompanying drawings. 1 is a cross-sectional view showing a semiconductor device formed according to a conventional method.

먼저, 반도체 기판(1)의 상부에 통상의 반도체 소자 공정을 진행하고 하부산화막(2)을 형성한 다음, 하부산화막(2) 상에 하부전극(3)을 형성하고, 하부전극(3) 상에 감광막 패턴(미도시)을 형성한 후 감광막 패턴을 마스크로 하여 하부전극(3)을 식각하여 소정폭을 남긴다.First, a normal semiconductor device process is performed on the semiconductor substrate 1, and a lower oxide film 2 is formed. Then, a lower electrode 3 is formed on the lower oxide film 2, and the lower electrode 3 is formed on the lower electrode 3. After the photoresist pattern (not shown) is formed on the lower electrode 3 by etching the photoresist pattern as a mask, a predetermined width is left.

다음, 하부전극(3)을 포함하여 하부산화막(2)의 상부전면에 산화막(4)을 두껍게 증착하고 화학기계적 연마하여 상면을 평탄화한 후, 산화막(4) 상에 하부전극(3) 상부의 소정영역이 오프닝된 감광막 패턴을 형성하고, 그 감광막 패턴 을 마스크로 하여 하부전극(3) 상의 산화막(4)을 소정영역 식각함으로써, 하부전극(3)의 표면을 개방하는 소정폭의 홀(100)을 형성한다. 그러나, 이러한 홀(100) 형성을 위한 산화막(4) 식각시, 하부전극(3)의 표면, 특히 홀의 하단 양 모서리와 인접한 부분(도 1에서 A로 표시됨)이 손상되는 언더컷 현상이 발생하기가 쉽다. Next, the oxide film 4 is thickly deposited on the upper surface of the lower oxide film 2 including the lower electrode 3 and chemically mechanically polished to planarize the upper surface, and then the upper surface of the lower electrode 3 is deposited on the oxide film 4. A hole 100 having a predetermined width that opens the surface of the lower electrode 3 by forming a photoresist pattern in which a predetermined region is opened and etching the predetermined region of the oxide film 4 on the lower electrode 3 using the photoresist pattern as a mask. ). However, when etching the oxide film 4 to form the hole 100, an undercut phenomenon occurs in which the surface of the lower electrode 3, in particular, the portions adjacent to both bottom edges of the hole (indicated by A in FIG. 1) are damaged. easy.

다음, 홀(100)의 내벽에 유전체층(5)을 형성하고, 유전체층(5) 상에 상부전극(6)을 홀(100) 내부가 매립되도록 형성함으로써, 하부전극(3), 유전체층(5) 및 상부전극(6)으로 이루어진 MIM 구조의 커패시터 제조를 완료한다.Next, the dielectric layer 5 is formed on the inner wall of the hole 100, and the lower electrode 3 and the dielectric layer 5 are formed by forming the upper electrode 6 on the dielectric layer 5 so that the inside of the hole 100 is embedded. And to complete the manufacturing of the capacitor of the MIM structure consisting of the upper electrode (6).

그러나, 상기한 바와 같은 종래 방법에서는 언더컷에 의해 A 부분 상에는 유전체층이 균일하게 형성되지 않기 때문에, 결과적으로 A 부분에서 상부전극이 하부전극과 상호 도통하여 커패시터의 역할을 못하게 되는 문제점이 있었다. However, in the conventional method as described above, since the dielectric layer is not uniformly formed on the A portion by the undercut, there is a problem that the upper electrode in the A portion is electrically conductive with the lower electrode, thereby preventing the role of the capacitor.

본 발명은 상기한 바와 같은 문제점을 해결하기 위한 것으로, 그 목적은 홀 형성을 위한 산화막 식각시 하부전극이 손상되는 언더컷으로 인해 커패시터가 파괴되는 것을 방지하는 데 있다.The present invention is to solve the problems as described above, the object is to prevent the capacitor from being destroyed by the undercut damage to the lower electrode during the etching of the oxide film for hole formation.

상기한 바와 같은 목적을 달성하기 위하여, 본 발명에서는 커패시터의 하부전극 상에 유전체층을 2층의 적층구조로 형성한 후, 비아홀을 형성하고 비아홀 내에 상부금속을 매립하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized in that after forming a dielectric layer in a stacked structure of two layers on the lower electrode of the capacitor, a via hole is formed and an upper metal is embedded in the via hole.

이하, 본 발명에 따른 반도체 소자 및 그 제조 방법에 대해 상세히 설명한 다. 도 2a 내지 도 2c는 본 발명에 따른 반도체 소자 제조 방법을 도시한 단면도이다.Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail. 2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

본 발명에 따라 제조된 반도체 소자는 도 2c에 도시되어 있으며, 이에 도시된 바와 같이, 본 발명에 따른 반도체 소자에서는, 반도체 기판(11)의 구조물 상에는 하부절연막(12)이 형성되어 있고, 하부절연막(12) 상에는 소정폭의 하부전극(13)이 형성되어 있으며, 하부전극(13) 상에는 이보다 좁은 폭을 가지는 제1유전체층(15) 및 제2유전체층(16)이 형성되어 있고, 제2유전체층(16) 상에는 이보다 좁은 폭의 비아홀(200)이 형성되어 있으며, 비아홀(200)의 내부에는 텅스텐 등으로 이루어진 상부전극(21)이 매립되어 있고, 비아홀(200)의 외측방, 하부전극(13)과 제1유전체층(15) 및 제2유전체층(16)의 외부, 및 하부절연막(12) 상에는 층간절연막(18)이 형성되어 있고, 상부전극(21) 및 층간절연막(18) 상에는 소정폭의 금속배선(23)이 형성되어 있다. The semiconductor device manufactured according to the present invention is illustrated in FIG. 2C. As shown in FIG. 2, in the semiconductor device according to the present invention, a lower insulating film 12 is formed on a structure of the semiconductor substrate 11, and a lower insulating film is provided. A lower electrode 13 having a predetermined width is formed on the lower surface 12, and a first dielectric layer 15 and a second dielectric layer 16 having a narrower width are formed on the lower electrode 13, and a second dielectric layer ( 16, a narrower width of the via hole 200 is formed. An upper electrode 21 made of tungsten or the like is embedded in the via hole 200, and an outer side and a lower electrode 13 of the via hole 200 are embedded. An interlayer insulating film 18 is formed on the outside of the first dielectric layer 15 and the second dielectric layer 16 and on the lower insulating film 12, and a metal having a predetermined width is formed on the upper electrode 21 and the interlayer insulating film 18. The wiring 23 is formed.

이 때, 하부전극(13) 상에는 반사방지막(14)이 추가로 형성될 수 있으며, 비아홀(200)의 내벽에는 제1베리어금속막(20)이, 금속배선(23)의 하면에는 제2베리어금속막(22)이 형성될 수 있다. In this case, an anti-reflection film 14 may be further formed on the lower electrode 13. The first barrier metal film 20 is formed on the inner wall of the via hole 200, and the second barrier is formed on the bottom surface of the metal wiring 23. The metal film 22 may be formed.

또한, 비아홀(200)의 폭은 제2유전체층(16) 폭의 1/2 보다 크면서 제2유전체층(16) 폭보다 좁은 것이 바람직하다.In addition, the width of the via hole 200 is preferably greater than 1/2 of the width of the second dielectric layer 16 and narrower than the width of the second dielectric layer 16.

제2유전체층(16)의 두께는 제1유전체층(15)의 두께보다 더 두꺼우며, 그 값은 제1유전층이 200~400Å의 두께이고, 제2유전체층이 300~500Å의 두께인 것이 바람직하다. 이러한 제1유전체층(15) 및 제2유전체층(16)은 각각 산화물, 실리콘나이 트라이드, 및 실리콘옥시나이트라이드 중의 어느 한 물질로 이루어질 수 있으며, 제1유전층으로 실리콘옥시나이트라이드를 사용할 때에는 실리콘옥시나이트라이드 상에 100Å 이하의 두께로 산화막을 더 형성하는 것이 바람직하다.The thickness of the second dielectric layer 16 is thicker than the thickness of the first dielectric layer 15, and the value of the second dielectric layer is preferably 200 to 400 kPa and the second dielectric layer is 300 to 500 kPa. The first dielectric layer 15 and the second dielectric layer 16 may be made of any one of an oxide, silicon nitride, and silicon oxynitride, respectively, and when silicon oxynitride is used as the first dielectric layer, silicon oxy It is preferable to further form an oxide film on the nitride with a thickness of 100 kPa or less.

그러면, 상기한 바와 같은 본 발명의 반도체 소자를 제조하는 방법에 대해 상세히 설명한다.Then, the method of manufacturing the semiconductor device of the present invention as described above will be described in detail.

먼저, 도 2a에 도시된 바와 같이, 반도체 기판(11)의 상부에 통상의 반도체 소자 공정을 진행하고 하부절연막(12)을 형성한 다음, 하부절연막(12) 상에 하부전극(13) 및 제1유전체층(15)을 차례로 형성한다. 이 때 하부전극(13) 상에는 반사방지막(14)을 형성한 후, 반사방지막(14) 상에 유전체층(15)을 형성할 수도 있다. First, as shown in FIG. 2A, a normal semiconductor device process is performed on the semiconductor substrate 11, and a lower insulating film 12 is formed. Then, the lower electrode 13 and the first electrode are formed on the lower insulating film 12. One dielectric layer 15 is formed in sequence. In this case, after forming the anti-reflection film 14 on the lower electrode 13, the dielectric layer 15 may be formed on the anti-reflection film 14.

이 때, 제1유전체층(15)은 200~400Å의 두께로 형성하는 것이 바람직하며, 이러한 제1유전체층(15)은 산화물, 실리콘나이트라이드, 및 실리콘옥시나이트라이드 중의 어느 한 물질을 사용하여 형성할 수 있다.At this time, the first dielectric layer 15 is preferably formed to a thickness of 200 ~ 400Å, such a first dielectric layer 15 may be formed using any one of oxide, silicon nitride, and silicon oxynitride. Can be.

이어서, 유전체층(15)의 상부 전면에 감광막을 도포하고 노광 및 현상하여 소정폭의 감광막만을 남기고 나머지를 식각함으로써 감광막 패턴(미도시)을 형성하고, 그 감광막 패턴을 마스크로 하여 상면이 노출된 유전체층(15), 반사방지막(14), 및 하부전극(13)을 소정부분을 식각하여, 유전체층(15), 반사방지막(14), 및 하부전극(13)을 소정폭으로 남긴 후, 감광막 패턴을 제거하고 세정공정을 수행한다.Subsequently, a photoresist film is applied to the entire upper surface of the dielectric layer 15 and exposed and developed to form a photoresist pattern (not shown) by leaving only the photoresist film having a predetermined width and etching the rest, and using the photoresist pattern as a mask to expose the upper surface. (15), the antireflection film 14 and the lower electrode 13 are etched to a predetermined portion to leave the dielectric layer 15, the antireflection film 14, and the lower electrode 13 at a predetermined width, and then the photoresist pattern is removed. Remove and perform the cleaning process.

다음, 제1유전체층(15)을 포함하여 하부절연막(12)의 상부 전면에 제2유전체층을 형성한다. 이 때, 제2유전체층(16)은 제1유전체층(15)보다 두껍게 형성하며, 그 두께는 300~500Å의 두께로 형성하는 것이 바람직하다. 이러한 제2유전체층(16)은 산화물, 실리콘나이트라이드, 및 실리콘옥시나이트라이드 중의 어느 한 물질을 사용하여 형성할 수 있다.Next, a second dielectric layer is formed on the entire upper surface of the lower insulating layer 12 including the first dielectric layer 15. At this time, the second dielectric layer 16 is formed to be thicker than the first dielectric layer 15, the thickness is preferably formed to a thickness of 300 ~ 500 ~. The second dielectric layer 16 may be formed using any one of an oxide, silicon nitride, and silicon oxynitride.

이어서, 제2유전체층(16)의 상부 전면에 감광막을 도포하고 노광 및 현상하여 소정폭의 감광막만을 남기고 나머지를 식각함으로써 감광막 패턴(17)을 형성하고, 감광막 패턴(17)을 마스크로 하여 상면이 노출된 제2유전체층(16)을 식각하여 제2유전체층(16)을 소정폭으로 남긴 후, 연속하여 제1유전체층(15)을 건식식각하여 소정폭으로 남긴 다음, 감광막 패턴(17)을 제거하고 세정공정을 수행한다. 그러면, 소정폭의 하부전극(13) 및 반사방지막(14)의 적어도 일부분 상에 제1유전체층(15) 및 제2유전체층(16)이 형성되는 것이다.Subsequently, a photoresist film is applied to the entire upper surface of the second dielectric layer 16, and the photoresist film is exposed and developed, leaving only the photoresist film having a predetermined width and etching the remaining portion to form a photoresist pattern 17. After the exposed second dielectric layer 16 is etched to leave the second dielectric layer 16 at a predetermined width, the first dielectric layer 15 is continuously etched to remain at a predetermined width, and then the photoresist pattern 17 is removed. Carry out a cleaning process. Then, the first dielectric layer 15 and the second dielectric layer 16 are formed on at least a portion of the lower electrode 13 and the anti-reflection film 14 having a predetermined width.

다음, 제2유전체층(16)을 포함하여 하부절연막(12)의 상부 전면에 산화막 등으로 이루어진 층간절연막(18)을 두껍게 증착한다. 층간절연막(18)의 증착 후에는 화학기계적 연마하여 그 상면을 평탄화할 수 있으며, 평탄화 후에는 400~600℃의 온도로 열처리할 수 있다. Next, a thick interlayer insulating film 18 made of an oxide film or the like is deposited on the entire upper surface of the lower insulating film 12 including the second dielectric layer 16. After the deposition of the interlayer insulating film 18, the upper surface of the interlayer insulating film 18 may be flattened by chemical mechanical polishing.

이어서, 평탄화된 층간절연막(18)의 상면에 감광막을 도포하고 노광 및 현상하여 비아로 예정된 부분의 제2층간절연막(18) 상면을 노출시키는 감광막 패턴(19)을 형성한다. Subsequently, a photosensitive film is coated on the top surface of the planarized interlayer insulating film 18, and the photosensitive film pattern 19 is formed to expose and expose the top surface of the second interlayer insulating film 18 in a portion intended as a via.

다음, 감광막 패턴(19)을 마스크로 하여 상면이 노출된 층간절연막(18) 부분을 건식식각하여 제2유전체층(16)의 표면을 개방하는 소정폭의 비아홀(200)을 형성한다. 이 때, 본 발명에서의 유전체층은 제1유전체층(15) 및 제2유전체층(16)의 2 층 구조로 되어 있기 때문에 비아홀 형성을 위한 식각시 제2유전체층이 만약 손상을 입더라도 그 하부의 제1유전체층은 보호되기 때문에, 커패시터의 유전체층은 안정한 구조로 형성되는 장점이 있다. Next, the photoresist pattern 19 is used as a mask to dry-etch the portion of the interlayer insulating layer 18 having the upper surface exposed to form a via hole 200 having a predetermined width opening the surface of the second dielectric layer 16. At this time, since the dielectric layer of the present invention has a two-layer structure of the first dielectric layer 15 and the second dielectric layer 16, the second dielectric layer during the etching for forming the via hole may be damaged even if it is damaged. Since the dielectric layer is protected, the dielectric layer of the capacitor has an advantage of being formed in a stable structure.

다음, 감광막 패턴(19)을 제거하고 세정공정을 수행한 다음, 비아홀(200)의 내벽에 제1베리어금속막(20)을 증착하고, 제1베리어금속막(20) 상에 텅스텐 등의 상부전극(21)을 증착하여 비아홀(200)의 내부를 완전히 매립한다. 상부전극(21)의 증착 후에는 층간절연막(18)의 상면이 노출될 때까지 화학기계적 연마하여 상면을 평탄화시킬 수 있으며, 평탄화 후에는 400~600 ℃의 온도로 열처리할 수 있다. Next, the photoresist layer pattern 19 is removed and a cleaning process is performed. Then, the first barrier metal layer 20 is deposited on the inner wall of the via hole 200, and an upper portion of tungsten or the like is formed on the first barrier metal layer 20. The electrode 21 is deposited to completely fill the inside of the via hole 200. After the deposition of the upper electrode 21, the upper surface of the interlayer insulating film 18 may be chemically polished until the upper surface is exposed to planarize the upper surface, and after the planarization, the upper electrode 21 may be heat-treated at a temperature of 400 to 600 ° C.

상기한 구조에서, 하부전극(13), 제1유전체층(15), 제2유전체층(16) 및 상부전극(21)은 MIM 구조의 커패시터에 해당된다.In the above structure, the lower electrode 13, the first dielectric layer 15, the second dielectric layer 16, and the upper electrode 21 correspond to a capacitor of the MIM structure.

이어서, 평탄화된 상면에 제2베리어금속막(22) 및 금속배선막(23)을 차례로 증착하고 이들을 패터닝하여 금속배선을 형성한다. 이 때 제2베리어금속막(22) 형성 이전에, 플라즈마 식각을 수행하여 상부전극(21) 표면의 이물질을 제거할 수 있다.Subsequently, the second barrier metal film 22 and the metal wiring film 23 are sequentially deposited on the flattened top surface and patterned to form metal wirings. At this time, before forming the second barrier metal layer 22, plasma etching may be performed to remove foreign substances on the surface of the upper electrode 21.

상술한 바와 같이, 본 발명에서는 커패시터의 하부전극 상에 유전체층을 형성한 후, 비아홀을 형성하고 비아홀 내에 상부금속을 매립하기 때문에, 종래 비아홀 식각시 하부전극이 손상되는 언더컷 현상이 방지되는 효과가 있으며, 따라서, 유전체층을 안정된 구조로 형성하는 효과가 있다.As described above, in the present invention, since the dielectric layer is formed on the lower electrode of the capacitor, the via hole is formed and the upper metal is buried in the via hole, thereby preventing the undercut phenomenon in which the lower electrode is damaged during the conventional via hole etching. Therefore, there is an effect of forming the dielectric layer into a stable structure.

특히, 본 발명에서는 유전체층을 2층 구조로 형성하기 때문에, 비아홀 형성 을 위한 식각시 상층의 유전체층이 손상을 입는다 하더라도 하층의 유전체층은 보호되기 때문에, 커패시터의 유전체층을 더욱 안정된 구조로 형성할 수 있다는 효과가 있다.In particular, in the present invention, since the dielectric layer is formed in a two-layer structure, even if the upper dielectric layer is damaged during the etching of via holes, the lower dielectric layer is protected, so that the dielectric layer of the capacitor can be formed in a more stable structure. There is.

따라서, 언더컷으로 인해 커패시터가 파괴되는 일이 방지되는 효과가 있다.Therefore, there is an effect of preventing the capacitor from being destroyed by the undercut.

Claims (18)

반도체 기판의 구조물 상에 형성된 하부절연막;A lower insulating film formed on the structure of the semiconductor substrate; 상기 하부절연막 상에 형성된 소정폭의 하부전극;A lower electrode having a predetermined width formed on the lower insulating layer; 상기 하부전극의 일부분 상에 형성된 제1유전체층;A first dielectric layer formed on a portion of the lower electrode; 상기 제1유전체층 상에 형성된 제2유전체층;A second dielectric layer formed on the first dielectric layer; 상기 제2유전체층 상에 형성되고 상기 제2유전체층 보다 좁은 폭을 가지는 비아홀;A via hole formed on the second dielectric layer and having a narrower width than the second dielectric layer; 상기 비아홀의 내부에 매립된 상부전극;An upper electrode embedded in the via hole; 상기 비아홀의 외측방, 상기 하부전극 및 유전체층의 외부, 및 상기 하부절연막 상에 형성된 층간절연막;An interlayer insulating film formed on an outer side of the via hole, outside of the lower electrode and the dielectric layer, and on the lower insulating film; 상기 상부전극 및 층간절연막 상에 형성된 금속배선을 포함하는 반도체 소자.A semiconductor device comprising a metal wiring formed on the upper electrode and the interlayer insulating film. 제 1 항에 있어서, The method of claim 1, 상기 하부전극 상에 형성된 반사방지막을 더 포함하는 반도체 소자.The semiconductor device further comprises an anti-reflection film formed on the lower electrode. 제 2 항에 있어서,The method of claim 2, 상기 비아홀의 내벽에 형성된 제1베리어금속막을 더 포함하는 반도체 소자. And a first barrier metal film formed on an inner wall of the via hole. 제 3 항에 있어서, The method of claim 3, wherein 상기 금속배선의 하면에 형성된 제2베리어금속막을 더 포함하는 반도체 소자.The semiconductor device further comprises a second barrier metal film formed on the lower surface of the metal wiring. 제 4 항에 있어서,The method of claim 4, wherein 상기 비아홀의 폭은 상기 제2유전체층 폭의 1/2보다 큰 반도체 소자.And a width of the via hole is greater than half the width of the second dielectric layer. 제 5 항에 있어서,The method of claim 5, 상기 제2유전체층의 두께가 상기 제1유전체층의 두께보다 두꺼운 반도체 소자. And a thickness of the second dielectric layer is thicker than that of the first dielectric layer. 제 6 항에 있어서,The method of claim 6, 상기 제1유전체층의 두께는 200~400Å이고, 상기 제2유전체층의 두께는 300~500Å인 반도체 소자. The thickness of the first dielectric layer is 200 ~ 400Å, the thickness of the second dielectric layer is 300 ~ 500Å semiconductor device. 제 7 항에 있어서, The method of claim 7, wherein 상기 제1유전체층 및 제2유전체층은 각각 산화물, 실리콘나이트라이드, 및 실리콘옥시나이트라이드 중의 어느 한 물질로 이루어지는 반도체 소자.And the first dielectric layer and the second dielectric layer each comprise one of an oxide, silicon nitride, and silicon oxynitride. 제 8 항에 있어서,The method of claim 8, 상기 제1유전체층으로 실리콘옥시나이트라이드를 사용할 때에는, 상기 실리콘옥시나이트라이드 상에 100Å 이하의 두께로 형성된 산화막을 더 포함하는 것을 특징으로 하는 반도체 소자.When silicon oxynitride is used as the first dielectric layer, the semiconductor device further comprises an oxide film formed on the silicon oxynitride to a thickness of 100 GPa or less. 제 9 항에 있어서, The method of claim 9, 상기 상부전극은 텅스텐으로 이루어지는 반도체 소자.The upper electrode is a semiconductor device made of tungsten. 반도체 기판의 구조물 상에 하부절연막을 형성하는 단계;Forming a lower insulating film on the structure of the semiconductor substrate; 상기 하부절연막 상에 하부전극을 형성하고, 상기 하부전극의 일부분 상에 제1유전체층 및 제2유전체층을 형성하는 단계;Forming a lower electrode on the lower insulating layer, and forming a first dielectric layer and a second dielectric layer on a portion of the lower electrode; 상기 제2유전체층을 포함하여 상기 하부절연막의 상부 전면에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the entire upper surface of the lower insulating film including the second dielectric layer; 상기 층간절연막을 선택적으로 식각하여, 비아홀을 형성하는 단계;Selectively etching the interlayer insulating film to form via holes; 상기 비아홀의 내부를 매립하여 상부전극을 형성하는 단계;Filling the inside of the via hole to form an upper electrode; 상기 상부전극 및 층간절연막 상에 금속배선을 형성하는 단계Forming a metal wiring on the upper electrode and the interlayer dielectric layer 를 포함하는 반도체 소자 제조 방법.Semiconductor device manufacturing method comprising a. 제 11 항에 있어서, The method of claim 11, 상기 하부절연막 상에 하부전극을 형성하고, 상기 하부전극의 일부분 상에 제1유전체층 및 제2유전체층을 형성하는 단계는,Forming a lower electrode on the lower insulating layer, and forming a first dielectric layer and a second dielectric layer on a portion of the lower electrode, 상기 하부절연막의 상부 전면에 하부전극 및 제1유전체층을 차례로 형성한 후, 감광막 패턴을 마스크로 이용하여 상기 하부전극 및 제1유전층을 식각하여 남기는 단계와;Forming a lower electrode and a first dielectric layer on the upper surface of the lower insulating layer in order, and then etching and leaving the lower electrode and the first dielectric layer using a photosensitive film pattern as a mask; 상기 제1유전체층을 포함하여 상기 하부절연막의 상부 전면에 제2유전체층을 형성한 후, 감광막 패턴을 마스크로 이용하여 상기 제2유전체층을 식각하여 남긴 다음, 상기 감광막 패턴을 마스크로 이용하여 제1유전체층을 식각하여 남기는 단계After the second dielectric layer is formed on the entire upper surface of the lower insulating layer including the first dielectric layer, the second dielectric layer is etched away using a photoresist pattern as a mask, and then the first dielectric layer is used using the photoresist pattern as a mask. Etching Steps 로 이루어지는 반도체 소자 제조 방법.The semiconductor element manufacturing method which consists of. 제 12 항에 있어서, The method of claim 12, 상기 층간절연막을 형성한 후에는 상면을 화학기계적 연마하여 평탄화시키는 단계를 더 포함하는 반도체 소자 제조 방법.And forming a top surface by chemical mechanical polishing after the interlayer dielectric layer is formed. 제 12 항에 있어서, The method of claim 12, 상기 상부전극을 형성한 후에는, 상기 층간절연막이 노출될 때까지 상면을 화학기계적 연마하여 평탄화시키는 단계를 더 포함하는 반도체 소자 제조 방법.After the forming of the upper electrode, further comprising chemically polishing the upper surface of the semiconductor device until the interlayer insulating film is exposed. 제 13 항 또는 제 14 항에 있어서, The method according to claim 13 or 14, 상기 평탄화 단계 후에는 400~600 ℃의 온도로 열처리하는 단계를 더 포함하는 반도체 소자 제조 방법.After the planarization step further comprises the step of heat treatment at a temperature of 400 ~ 600 ℃. 제 15 항에 있어서, The method of claim 15, 상기 상부전극의 형성 단계 이전에, 상기 비아홀의 내벽에 제1베리어금속막을 형성하는 단계를 더 포함하는 반도체 소자 제조 방법. And forming a first barrier metal film on an inner wall of the via hole before the forming of the upper electrode. 제 16 항에 있어서, The method of claim 16, 상기 금속배선의 형성 단계 이전에, 상기 상부전극 및 층간절연막 상에 제2베리어금속막을 형성하는 단계를 더 포함하는 반도체 소자 제조 방법.And forming a second barrier metal film on the upper electrode and the interlayer insulating film before the forming of the metal wiring. 제 17 항에 있어서,The method of claim 17, 상기 제2베리어금속막 형성 단계 이전에, 플라즈마 식각을 수행하여 상기 상부전극 표면의 이물질을 제거하는 단계를 더 포함하는 반도체 소자 제조 방법. Before the second barrier metal film forming step, further comprising the step of removing the foreign material on the surface of the upper electrode by performing plasma etching.
KR1020020045019A 2002-07-30 2002-07-30 Semiconductor device and fabrication method of thereof KR100782790B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020020045019A KR100782790B1 (en) 2002-07-30 2002-07-30 Semiconductor device and fabrication method of thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020020045019A KR100782790B1 (en) 2002-07-30 2002-07-30 Semiconductor device and fabrication method of thereof

Publications (2)

Publication Number Publication Date
KR20040011247A KR20040011247A (en) 2004-02-05
KR100782790B1 true KR100782790B1 (en) 2007-12-05

Family

ID=37319561

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020045019A KR100782790B1 (en) 2002-07-30 2002-07-30 Semiconductor device and fabrication method of thereof

Country Status (1)

Country Link
KR (1) KR100782790B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100710202B1 (en) * 2005-07-14 2007-04-20 동부일렉트로닉스 주식회사 method for manufacturing capacitor of semiconductor device and image sensor using the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000024736A (en) * 1998-10-01 2000-05-06 윤종용 Method for fabricating metal-insulator-metal capacitor
KR20010004719A (en) * 1999-06-29 2001-01-15 김영환 Method of forming a metal wiring in a semiconductor device
KR20010004717A (en) * 1999-06-29 2001-01-15 김영환 Method of forming a metal wiring in a semiconductor device
JP2002026145A (en) * 2000-06-19 2002-01-25 Hynix Semiconductor Inc Semiconductor element having plug coming into contact with capacitor electrode and its manufacturing method
JP2002100742A (en) * 2000-08-11 2002-04-05 Samsung Electronics Co Ltd Semiconductor memory device provided with capacitor encapsulated as multifilm comprising double film with each layer formed of the same substance, and method of manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000024736A (en) * 1998-10-01 2000-05-06 윤종용 Method for fabricating metal-insulator-metal capacitor
KR20010004719A (en) * 1999-06-29 2001-01-15 김영환 Method of forming a metal wiring in a semiconductor device
KR20010004717A (en) * 1999-06-29 2001-01-15 김영환 Method of forming a metal wiring in a semiconductor device
JP2002026145A (en) * 2000-06-19 2002-01-25 Hynix Semiconductor Inc Semiconductor element having plug coming into contact with capacitor electrode and its manufacturing method
JP2002100742A (en) * 2000-08-11 2002-04-05 Samsung Electronics Co Ltd Semiconductor memory device provided with capacitor encapsulated as multifilm comprising double film with each layer formed of the same substance, and method of manufacturing the same

Also Published As

Publication number Publication date
KR20040011247A (en) 2004-02-05

Similar Documents

Publication Publication Date Title
KR100343286B1 (en) Method for processing defect source of wafer rim
KR20040023297A (en) Semiconductor device having a SiN etch stopper by low temperature ALD and fabricating method the same
JP4964407B2 (en) Semiconductor device and manufacturing method thereof
US6448134B2 (en) Method for fabricating semiconductor device
KR100412128B1 (en) Method for manufacturing capacitor of semiconductor device
US6403431B1 (en) Method of forming in an insulating layer a trench that exceeds the photolithographic resolution limits
KR20050071149A (en) Method of manufacturing semiconductor device with mim capacitor
KR100415537B1 (en) Method for fabrication of semiconductor device
KR100465865B1 (en) Method for forming storage node electrode in MML device
KR100356136B1 (en) Semiconductor device fabrication method
KR100485167B1 (en) Semiconductor device and fabrication method of thereof
KR100835825B1 (en) Semiconductor device and method for fabricating the same
KR100782790B1 (en) Semiconductor device and fabrication method of thereof
KR100798270B1 (en) Semiconductor device and fabrication method of thereof
CN112635467A (en) Memory cell structure and forming method
US20090124079A1 (en) Method for fabricating a conductive plug
US20070075395A1 (en) Capacitor of a semiconductor device
KR100617060B1 (en) A method for fabricating a semiconductor device
KR100490836B1 (en) Thin film capacitor and fabrication method thereof
KR100450244B1 (en) Semiconductor device and fabrication method of thereof
KR100881738B1 (en) Method for fabrication of semiconductor device
KR100696774B1 (en) A method for forming a capacitor of a semiconductor device
US20040108534A1 (en) Semiconductor device and manufacturing method for the same
KR100485180B1 (en) Fabrication method of semiconductor device
KR100467781B1 (en) Thin film capacitor and fabrication method thereof

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20111020

Year of fee payment: 5

FPAY Annual fee payment

Payment date: 20121026

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee