KR100778459B1 - Apparatus and method for programming, erasing and verificating a pluality of electronic devices - Google Patents

Abstract

An apparatus for programming, erasing and verifying plural electronic devices are provided to operate plural FPGAs(Field Programmable Gate Arrays) via one CPU in one set of a device like a ROM writer, and to perform a programming procedure, an erasing procedure or a verification procedure regarding electronic devices like semiconductor chips for increasing efficiency. An apparatus for programming, erasing and verifying plural electronic devices comprises a buffer memory(10), electronic devices(50-1-n), FPGAs(40-1-n) and a CPU(20). The buffer memory(10) stores data to be programmed. The electronic devices(50-1-n) are targets where the data is programmed. The FPGAs(40-1-n) program the data for the electronic devices(50-1-n), verify programmed result data, and erase the data stored at the electronic devices(50-1-n). The CPU(20) controls the FPGAs(40-1-n) to perform programming, erasing and verification concurrently regarding the electronic devices(50-1-n). The FPGA checks a state of an electronic device included in itself, expresses the checked state with one bit data, transmits the checked state to the CPU(20). The FPGA compares original data of the buffer memory(10) with the data programmed at the electronic device, expresses the comparison result with one bit data, and transmits the comparison result to the CPU(20) in the verification. The CPU(20) checks an electronic device where there occurs an error regarding a currently progressed process and controls maintaining to perform the currently progressed process for only electronic devices without an error on the basis of the checked state and the comparison result from the plural FPGAs(40-1-n).

Description

Apparatus and method for programming, erasing and verificating a pluality of electronic devices}

1 is a block diagram illustrating an apparatus for programming, erasing, and verifying a plurality of conventional electronic devices;

2 is a block diagram of an apparatus for programming, erasing, and verifying a plurality of electronic devices according to the present invention;

3 is a detailed configuration diagram of the present invention shown in FIG.

4 is a diagram illustrating a state check of a plurality of electronic devices by a device for programming, erasing, and verifying the plurality of electronic devices according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10: buffer memory 20: CPU

30: mode setting unit

40_1 ~ 40_n: FPGA (field-programmable gate array)

41: control decoder 42: address latch

43: record data latch 44: comparison data latch

45: read data latch 46: status check unit

48: comparison result latch 49: selector

50_1 to 50_n: semiconductor chip (electronic device)

The present invention relates to a device for programming, erasing and verifying a plurality of electronic devices, and more particularly, a process of simultaneously programming and erasing a plurality of semiconductor devices (hereinafter, referred to as "electronic devices") capable of storing programs and data. And a device for drastically reducing the time spent in verifying stored data after a program.

Conventionally, nonvolatile semiconductor devices (ROMs, flash memories, etc.) and semiconductor devices (hereinafter, all referred to as "electronic devices") incorporating the same are written or programmed one by one in inversion in a programmer (for example, a ROM writer). Erase and verify were performed respectively.

In addition, in order to program more electronic devices at the same time, up to 4, 8, 16 devices at the same time have been developed. Such an apparatus is shown in FIG. 1.

As shown in Fig. 1, the conventional apparatus is equipped with 16 electronic devices (semiconductor chips) 5_1 to 5_16 to be programmed, and when the program mode is set via the mode setting section 3, the CPU 2 buffers the memory. Data stored in (1) is read and transferred to the logic ICs 4_1 to 4_16, and the data is written to the electronic devices (semiconductor chips) 5_1 to 5_16 by the logic ICs 4_1 to 4_16. When programming, you must check and program the status check bit for every byte written, and also check and clear the status check bit for every sector when erasing. In addition, when verifying the programmed contents, all contents should be compared with the contents of the buffer memory to indicate whether there is an error. In other words, in order to confirm the abnormality of the programmed contents, the contents stored in all the electronic devices (semiconductor chips) 5_1 to 5_16 should be read and compared with the contents of the buffer memory 1 to inform them of the abnormality. In this case, since the contents of each electronic device (semiconductor chip) 5_1 to 5_16 should be read and compared, the time required by the number of electronic devices (semiconductor chip) was required.

Therefore, in a conventional device, all one time is inevitable when programming, reading, and verifying one electronic device at a time. However, when performing a plurality of (16) electronic devices at a time, programs are simultaneously performed on 16 electronic devices. In the process of writing and checking the programmed contents, the electronic devices are classified and performed according to the number of electronic devices. Therefore, it takes time as many as the number of electronic devices to wait for several tens of minutes.

In recent years, with the increasing use of large-capacity flash memory, there is a greater need for this time reduction.

Accordingly, the present invention has been made in view of the above-described conventional situation, and provides an apparatus capable of drastically reducing the time required for simultaneously programming and erasing a plurality of electronic devices and verifying data stored after the program. The purpose is to.

In order to achieve the above object, an apparatus according to the present invention includes a buffer memory for storing data to be programmed (written); A plurality of electronic devices (semiconductor chips) to be mounted on the program; A plurality of FPGAs installed corresponding to each of the electronic devices to perform a function of programming data in the electronic device, verifying program result data, and erasing data stored in the electronic device; The CPU is configured to control the plurality of FPGAs to simultaneously perform a program process, a verification process, and an erase process for a plurality of electronic devices, wherein the FPGA checks a state of an electronic device belonging to the inspection device and checks the state. Is expressed as 1-bit data and transmitted to the CPU, and the comparison information on whether the original data from the buffer memory and the data programmed in the electronic device is the same as the 1-bit data during the verification process for the electronic device belonging to the CPU. Expresses and transmits the data to the CPU. The CPU identifies an electronic device in which an error has occurred regarding a process that is currently being processed, based on 1 bit of check status information or comparison information received from the plurality of FPGAs, and does not generate an error. It is characterized in that only the electronic devices which are not used are controlled to continue the processing currently in progress.

Hereinafter, an apparatus for programming, erasing, and verifying a plurality of electronic devices according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an apparatus for programming, erasing, and verifying a plurality of electronic devices according to the present invention. As shown in the figure, the apparatus according to the present invention includes a buffer memory 10, a CPU 20, a mode setting unit 30, a plurality of FPGAs 40_1 to 40_n, and a plurality of electronics mounted on a program target. It comprises a device (semiconductor chip) 50_1-50_n.

The buffer memory 10 is a device for temporarily storing data to be recorded in a program target electronic device (semiconductor chip) 50_1 to 50_n. The mode setting unit 30 is for setting various modes by a user. For example, a program mode for recording data in the program target electronic devices (semiconductor chips) 50_1 to 50_n, an erase mode for erasing data recorded in the program target electronic devices (semiconductor chips) 50_1 to 50_n, and The verification mode for checking the contents programmed in the electronic device (semiconductor chip) 50_1 to 50_n is set. Here, the electronic device is a nonvolatile semiconductor memory device (ROM, flash memory, etc.) and a semiconductor device containing the same.

The CPU 20 performs overall control of a program process, an erase process, and a verification process of the electronic device (semiconductor chip) 50_1 to 50_n according to the setting mode of the mode setting unit 30. In this case, the CPU 20 receives the result information from the FPGAs 40_1 to 40_n, respectively, in a process of performing a program in a 16-bit data unit, a process of erasing, and a process of verifying. In this case, the error processing is performed on the FPGA that transmits the error signal as the result information, and the subsequent processing is not performed.

The FPGAs 40_1 to 40_n are configured to actually perform a program process, an erase process, and a verification process of the electronic device (semiconductor chip) 50_1 to 50_n under the control of the CPU 20. In the figure, only the FPGA 40_1 is shown in the concrete block configuration for simplicity of the drawing, and the remaining FPGAs 40_2 to 40_n have the same configuration.

The FPGAs 40_1 to 40_n include a control decoder 41 for decoding a command signal transmitted from the CPU 41 and transmitting the decoded command signal to an electronic device (semiconductor chip) 50_1 to 50_n; An address latch 42 for latching an address transferred from the CPU 41; A write data latch 43 for latching write data transferred from the CPU 41 in program mode; A comparison data latch 44 for latching comparison data transmitted from the CPU 41 in the verify mode; A read data latch 45 for latching data read from the electronic device (semiconductor chip) 50_1 to 50_n; A state check unit 46 for checking a state of the electronic device (semiconductor chip) 50_1 to 50_n; A comparator (47) for comparing the data latched in the comparison data latch (44) with the data latched in the read data latch (45) during verification; 16-bit data comparison according to the signal from the CPU 20, readiness (RYBY) pin check of the semiconductor chip, read controller status check (bit 14), read controller status check (bit 10), NAND block unlock A selector 48 for outputting a selection signal for inspection, NAND block lock inspection, data polling inspection, protection state inspection, and the state inspection unit 46 according to the selection signal of the selector 48; And a comparison result latch 48 which selects any one of the state signals from the comparator and the comparison signal of the comparator and converts the signal into a 16-bit signal.

FIG. 3 is a detailed configuration diagram of the present invention shown in FIG. 2. In the same figure, the state checking unit 46 performs exclusive logical sum operation on bit 0 of the comparison data latch 44 and bit 0 of the read data latch 45 to output the exclusive logical sum gate A to check the protection state. And a batter logic gate (B) for performing exclusive logic operation on the bit 7 of the comparison data latch 44 and the bit 7 of the read data latch 45 to output the data polling check, and a NAND block ( In order to increase the lock state, the exclusive logical sum gate C outputting the exclusive logical operation of bit 1 of the comparison data latch 44 and bit 1 of the read data latch 45 and outputting the NAND block unlock state is performed. A batter logic gate (D) for performing exclusive logic operation on the bit 2 of the comparison data latch 44 and the bit 2 of the read data latch 45 for output, and the comparison data latch 44 for checking the state of the read controller. Bit 10) and read data latch 45 The exclusive logic sum gate (E) for outputting the exclusive logical sum operation of bit 10 and the output of the exclusive logical sum operation of bit 14 of the comparison data latch 44 and bit 14 of the read data latch 45 to check the read controller state. And a terminal G for checking the ready-use RYBY pin of the semiconductor chip. Here, two logic logic gates (E) and two battery logic gates (F) are provided because the bits for checking the read controller state differ depending on the type of electronic device (semiconductor chip) to be programmed.

The selector 48 has an output set as follows in accordance with a command of the CPU 20. In other words,

S2 S1 S0 E Explanation 0 0 0 One  6-bit data comparison 0 0 1 One  Semiconductor chip ready pin check 0 1 0 One  Check Read Controller Status (bit 14) 0 1 1 One  Check Read Controller Status (bit 10) 1 0 0 One  NAND block unlock check 1 0 1 One  NAND block lock check 1 1 0 One  Check data polling 1 1 1 One  Check protection status

When the comparison result latch 48 is " S2, S1, S0, E " is " 0, 0, 0, 1 ", the bit allocated to itself as shown in FIG. For example, bit 20 for the first FPGA, bit 2 for the second FPGA, bit 15 for the 16th FPGA, and bit 15 for the 16th FPGA, and the 16-bit value with the remaining high-impedance values filled in the CPU 20. To pass.

In addition, the comparison result latch 48 is a bit allocated to itself as shown in Figure 4 when the value of the terminal (G) when "S2, S1, S0, E" is "0, 0, 1, 1" It transmits to the CPU 20 a 16-bit value indicated by and filled in the high impedance value with all remaining bits.

Further, the comparison result latch 48 assigns the output value of the exclusive logic gate F to itself as shown in FIG. 4 when "S2, S1, S0, E" is "0, 1, 0, 1". The 16-bit value is displayed to the CPU 20 and the remaining bits are filled with the high impedance value.

The comparison result latch 48 assigns the output value of the exclusive logic gate E to itself as shown in FIG. 4 when " S2, S1, S0, E " is " 0, 1, 1, 1 ". The 16-bit value is displayed to the CPU 20 and the remaining bits are filled with the high impedance value.

Also, the comparison result latch 48 assigns the output value of the exclusive logical gate D to itself as shown in FIG. 4 when "S2, S1, S0, E" is "1, 0, 0, 1". The 16-bit value is displayed to the CPU 20 and the remaining bits are filled with the high impedance value.

The comparison result latch 48 assigns the output value of the exclusive logic gate C to itself as shown in FIG. 4 when " S2, S1, S0, E " is " 1, 0, 1, 1 ". The 16-bit value is displayed to the CPU 20 and the remaining bits are filled with the high impedance value.

Further, the comparison result latch 48 assigns the output value of the exclusive logic gate B to itself as shown in FIG. 4 when "S2, S1, S0, E" is "1, 1, 0, 1". The 16-bit value is displayed to the CPU 20 and the remaining bits are filled with the high impedance value.

The comparison result latch 48 assigns the output value of the exclusive logic gate A to itself when " S2, S1, S0, E " is " 1, 1, 1, 1 " The 16-bit value is displayed to the CPU 20 and the remaining bits are filled with the high impedance value.

Next, the operation of the apparatus according to the present invention configured as described above will be described.

First, a process of programming (writing) data in an electronic device (semiconductor chip) is as follows.

That is, when the program mode is set in the mode setting section 30, the CPU 20 outputs a write command to the control decoding section 41 to notify the semiconductor chips 50_1 to 50_n.

Thereafter, the CPU 20 reads the valid data from the buffer memory 10 in units of 16 bits, latches the write data latch 43, and simultaneously writes the write addresses of the semiconductor chips 50_1 to 50_n to the address latch 42. Latch it.

Subsequently, when the semiconductor chips 50_1 to 50_n are polled and the state check unit 46 confirms that the semiconductor chips 50_1 to 50_n are ready to be written, the data latched to the write data latch 43 is stored. Written in the semiconductor chips 50_1 to 50_n.

Subsequently, the address is increased and the above process is repeated to the last address to complete data writing (program) to the semiconductor chips 50_1 to 50_n.

On the other hand, after the polling of the semiconductor chips 50_1 to 50_n in the above-described process, whether or not the state checking unit 46 is ready to write among the semiconductor chips is transmitted to the CPU 20 in the format as shown in FIG. 4. At this time, if a bit indicating its state among the 16 bits is, for example, " 0 " (the state in which there is an error in writing), the CPU 20 executes the programming process of the semiconductor chip belonging to the corresponding FPGA. Error handling and program only the remaining semiconductor chip.

Next, a process of erasing data recorded in the electronic device (semiconductor chip) (sector erasing process) is as follows.

When the erase mode is set in the mode setting unit 30, the CPU 20 outputs an erase command to the control decoder 41 to notify the semiconductor chip 50_1 to 50_n of the erase command.

Thereafter, the CPU 20 latches the erase sector address of the semiconductor chips 50_1 to 50_n in the address latch 42.

Subsequently, when the semiconductor chips 50_1 to 50_n are polled and the state check unit 46 confirms that the semiconductor chips 50_1 to 50_n are ready to be erased, one sector is deleted after about 50 μs.

Subsequently, the sector address is increased and the above process is repeated until the last sector address to be erased, thereby completing data erasing to the semiconductor chips 50_1 to 50_n.

On the other hand, after the polling of the semiconductor chips 50_1 to 50_n in the above-described process, whether or not the erase is ready among the semiconductor chips is transmitted to the CPU 20 in the format as shown in FIG. 4. At this time, if a bit indicating its state among the 16 bits is, for example, " 0 " (an abnormal state in the erase), the CPU 20 performs an erase process of the semiconductor chip belonging to the corresponding FPGA. Error handling is performed and the erase process is continued only to the remaining semiconductor chips.

Next, a process of verifying data programmed (recorded) in the electronic device (semiconductor chip) is as follows.

That is, when the verification mode for the data (programmed) programmed in the mode setting unit 30 is set, the CPU 20 reads data from the buffer memory 10 in units of 16 bits and latches the data in the comparison data latch 44. At the same time, the address latch 42 latches the read addresses of the semiconductor chips 50_1 to 50_n.

Subsequently, 16-bit data read from the corresponding address in the semiconductor chips 50_1 to 50_n is latched in the read data latch 45.

Thereafter, the comparator 47 compares the data latched in the comparison data latch 44 and the data latched in the read data latch 45 in units of bits and outputs the comparison result to the comparison result latch 48.

Subsequently, the address is increased and the above process is repeated to the last address to complete verification of the write data to the semiconductor chips 50_1 to 50_n.

Meanwhile, in the above process, the comparison result by the comparator 47 of the semiconductor chips 50_1 to 50_n is transmitted to the CPU 20 in the format as shown in FIG. 4 through the comparison result latch 48. At this time, if a bit indicating its comparison result state among the 16 bits is, for example, "0" (that is, a state in which the comparison result does not match) occurs, the CPU 20 determines that the semiconductor chip belongs to the corresponding FPGA. Error verification process and continue the verification process only for the remaining semiconductor chips.

On the other hand, the present invention is not limited to the above specific embodiments, but can be modified and modified in various ways without departing from the gist of the present invention.

The conventional method reads data (programmed) written in a semiconductor chip in 16-bit units in the verification process and reads data from the buffer memory through the CPU in 16-bit units, so that 16-bit data in the buffer memory is read at one time. The 16-bit data is compared with the 16-bit data, and when it is finished, the next step is performed to the semiconductor chip and repeated 16 times to inform the user of the result.

However, according to the present invention, a plurality of FPGAs (eg, 16) are used to compare the contents of 16 semiconductor chips at the same time, and the result is notified to the user at once.

Therefore, in the present invention, a plurality of (for example, 16) FPGAs are simultaneously operated by one CPU in one set of devices (for example, a ROM writer) to program (write) and erase the electronic device (semiconductor chip). And verification can be performed to increase the efficiency of multiple times (eg, 16 times).

Claims (7)

A buffer memory in which data to be programmed (written) is stored; A plurality of electronic devices (semiconductor chips) to be mounted on the program; A plurality of FPGAs installed corresponding to each of the electronic devices to perform a function of programming data in the electronic device, verifying program result data, and erasing data stored in the electronic device; It is configured to include a CPU to control the plurality of FPGAs to perform the program process, verification process and erase process for a plurality of electronic devices at the same time The FPGA checks a state of an electronic device belonging to the FPGA and expresses the check state as 1-bit data to the CPU, and the original data from the buffer memory and the electronic device during the verification of the electronic device belonging to the FPGA. Represents the comparison information for the same or not as the data programmed in the 1-bit data and transmits it to the CPU. The CPU checks an electronic device having an error for the processing currently being performed based on the 1-bit check state information or the comparison information received from the plurality of FPGAs, and currently proceeds only for the electronic device in which the error has not occurred. And control to continue processing. The method of claim 1, The FPGA receives the valid data of a predetermined bit transmitted from the buffer memory through the CPU in the program (write) mode of the electronic device together with the write address, and checks the state of the electronic device after checking the state of the electronic device. And recording data repeatedly after recording data in the recording address of the electronic device. The method of claim 1, The FPGA, after receiving the erase address transmitted from the CPU in the erase mode of the electronic device and checking the state of the electronic device, erases the erase address of the electronic device, and repeats while increasing the erase address. Performing erasing. The method of claim 1, The FPGA receives original data of a predetermined bit transmitted from the buffer memory from the buffer memory with the read address in the verification mode of the electronic device, reads write data corresponding to the read address of the corresponding electronic device, And comparing the original data with the recorded data, and repeatedly performing a comparison while increasing a read address. The method according to any one of claims 1 to 4, The FPGA includes an address latch for latching an address transferred from the CPU; A write data latch for latching write data transferred from said CPU; A comparison data latch for latching comparison data which is original data from the buffer memory in the verify mode from the CPU; A read data latch for latching data read from the electronic device; A state check unit for checking a state of the electronic device and outputting a state check signal; A comparator for comparing original data latched in the comparison data latch and data latched in a read data latch in a verify mode; A selector for outputting a selection signal for selecting any one of a state output of the state checking unit and a comparison output of the comparator in accordance with a signal from the CPU; And a comparison result latch for outputting any one of a state output of the state check unit and a comparison output of the comparator according to the selection signal of the selector. The method of claim 5, The state checking unit performs a check of the RYBY pin of the semiconductor chip, a read controller state check, a NAND block unlock check, a NAND block lock check, a data polling check, and a protection state check. Device characterized in that. The method of claim 5, The electronic device is any one of a nonvolatile semiconductor memory device and a semiconductor device embedded therein.

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