KR100775009B1 - Correlated double sampling circuit and cmos image sensor having the same - Google Patents

Abstract

The present invention relates to a Correlated Double Sampling Circuit (CDS) and a CMOS image sensor having the same, which can simplify the circuit, and can be highly integrated while removing FPN (Fixed Pattern Noise). Is a first switching unit receiving a reset signal and an image signal output from a pixel unit in which a plurality of pixels are arranged in a matrix form through a column line, and transmitting the reset signal in response to a first control signal; The reset signal and the image signal, which are connected to a second unit and are transmitted through the first switching unit, are input through the first electrode, and a difference signal between the reset signal and the image signal according to a potential of a node connected to the second electrode. A first capacitor for sampling and being connected between the node and the voltage supply terminal and pulling up the potential of the node to a constant voltage in response to a second control signal; A pull-up transistor for maintaining a lot state, a source follower buffer amplifier for amplifying and outputting a difference signal sampled to the first capacitor, and an output of the buffer amplifier in response to a selection signal for selecting the column line. It provides a correlated double sampling circuit including a second switching unit for outputting a.

CMOS image sensor, correlated double sampling circuit (CDS), fixed pattern noise (FPN), offset voltage

Description

Correlated double sampling circuit and CMOS image sensor having the same {CORRELATED DOUBLE SAMPLING CIRCUIT AND CMOS IMAGE SENSOR HAVING THE SAME}

1 is a circuit diagram for explaining a correlated double sampling circuit according to the prior art;

2 is a circuit diagram for explaining a correlated double sampling circuit according to a first preferred embodiment of the present invention.

3 is an operational waveform diagram illustrating the operation characteristics of the correlated double sampling circuit shown in FIG. 2;

FIG. 4 is a circuit diagram illustrating an offset remover for removing an offset voltage generated in the correlated double sampling circuit shown in FIG.

FIG. 5 is a circuit diagram illustrating another offset remover for removing the offset voltage of the correlated double sampling circuit shown in FIG. 2; FIG.

FIG. 6 is an operation waveform diagram illustrating the operation characteristics of the offset removing unit illustrated in FIG. 5.

Fig. 7 is a circuit diagram for explaining a correlated double sampling circuit according to a second preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110, 210: unit pixel

20, 120, 220: Correlated Double Sampling Circuit (CDS)

30, 130, 230: buffer

140, 150: offset remover

M1 to M14: transistor

PD: Photodiode

FD: Floating Diffusion Area

Capacitors: C, Cs, C _R , Ccds, Cvdd

CL: column line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and in particular, to a correlated double sampling circuit for processing output signals of pixels arranged in a matrix form, and to a complementary metal oxide semiconductor (CMOS) image sensor having the same.

Recently, the demand for digital cameras is exploding with the development of video communication using the Internet. Moreover, the demand for small camera modules increases as the popularity of mobile communication terminals such as PDAs equipped with cameras, International Mobile Telecommunications-2000 (IMT-2000), Code Division Multiple Access (CDMA) terminals, etc. increases. Doing.

The camera module basically includes an image sensor. In general, an image sensor refers to a device that converts an optical image into an electrical signal. As such an image sensor, a charge coupled device (hereinafter referred to as a CCD) and a CMOS (Complementary Metal-Oxide-Semiconductor) image sensor are widely used.

CCD has a complicated driving method, high power consumption, complicated process due to the large number of mask processes in the manufacturing process, and it is difficult to realize a signal processing circuit in a chip, making it difficult to make one chip. There are disadvantages. In contrast, CMOS image sensors are receiving more attention recently because of the monolithic integration of control, drive, and signal processing circuitry on a single chip. In addition, CMOS image sensors offer potentially lower cost than conventional CCDs due to low voltage operation and low power consumption, compatibility with peripherals, and the availability of standard CMOS fabrication processes.

However, analog signals generated by light receiving elements, such as photo diodes, in CMOS image sensors have various parasitic effects caused by parasitic capacitance, resistance, dark current leakage, or mismatch of semiconductor device characteristics. Such a parasitic effect is essentially generated in a semiconductor device, resulting in a decrease in the signal to noise ratio of the image data. Therefore, noise is an important factor limiting the performance of the CMOS image sensor.

Noise in the CMOS image sensor is caused by kT / C noise related to the sampling of the image data, 1 / f noise associated with the circuit used to amplify the image signal, and fixed by the mismatch of the signal processing circuit of the sensor. Patterned Pattern Noise (hereinafter referred to as FPN). Dual FPNs are not very good visually because they appear as vertical lines or strips in the image and are easily found in the human eye.

Recently, a Correlate Double Sampling circuit (hereinafter referred to as CDS) has been used in a read out circuit to remove such FPN.

1 is a block diagram illustrating a unit pixel and a CDS in a general CMOS image sensor. Here, unit pixels having a 4-T (4-Transistor) structure will be described as one example of various structures.

Referring to FIG. 1, the unit pixel 10 includes one photodiode PD, three NMOS transistors M1 to M3, and four PMOS transistors M9 to M12. The four NMOS transistors M1 to M4 are transfer transistors M1 for transporting photo-generated charges concentrated in the photodiode PD to the floating diffusion region FD, A reset transistor M2 and a floating diffusion region for setting the potential of the floating diffusion region FD to a desired value and discharging the charge C _pd to reset the floating diffusion region FD. A drive transistor (M4) acting according to the charge accumulated in the FD and acting as a buffer amplifier in a source follower configuration, and a select transistor for addressing switching. select transistor (M3). A plurality of such unit pixels 10 are arranged in a matrix to form pixel units.

The CDS 20 reads and processes analog signals output from the plurality of unit pixels 10 connected to one column line CL and installed in the column line CL, one for each column line CL. do. The CDS 20 resets the floating diffusion region FD to the power supply voltage VDD by the reset transistor M2 that is turned on by the reset signal RST during the reset readout period. A signal output to the column line CL having a level corresponding to the potential of the reset floating diffusion region FD (hereinafter referred to as a reset voltage), and a photodiode during the signal detection section after the reset readout section Electrons and holes are formed by the light irradiated to the PD), and have a level corresponding to the accumulation of the electrons, and to read and sample the signals (hereinafter, referred to as image signal voltages) output to the column line CL, respectively. It consists of three NMOS transistors M6 to M8, four PMOS transistors M9 to M12, and two capacitors C _S and C _R.

The reading operation of the CMOS image sensor having such a configuration will be described below.

First, the reset transistor M2 is turned on by the reset signal RST during the reset read period, and the power supply voltage VDD is applied to the floating diffusion region FD through the reset transistor M2. Accordingly, the potential of the floating diffusion region FD is reset to a potential level lower than the power supply voltage VDD. The drive transistor M4 is turned on by the reset potential of the floating diffusion region FD. In this state, when the select transistor M3 is selected and turned on by the low line select signal SEL, the reset voltage including the offset voltage is output to the column line CL. Usually, the offset voltage is generated by drive transistor M4 configured as a source follower. That is, the reset voltage can be expressed as "Vreset + Voffset". In this state, when the SHR transistor M6 is turned on by the reset sample and hold signal (hereinafter referred to as SHR), the reset voltage output to the column line CL is used for storing the reset voltage. Stored in capacitor C _R. Of course, the SHS transistor M7 is turned off by the signal sample and hold signal (hereinafter referred to as SHS), and the Col transistors M9 and M11 are turned off by the column line selection signal Col. It remains turned off.

Subsequently, when the reset transistor M2 is turned off by the reset signal RST during the signal readout period, and the transfer transistor M1 is turned on by the transfer signal TR, the photodiode PD is irradiated. The electrons generated in the photodiode PD by the generated light are transferred to and accumulated in the floating diffusion region FD through the transfer transistor M1. At this time, holes are generated together with the electrons, and these holes are diffused to the silicon substrate. The floating diffusion region FD rises to a potential of a level corresponding to the accumulated charge to turn on the drive transistor M4. In this state, when the select transistor M3 is selected and turned on by the low line select signal SEL, the image signal voltage including the offset voltage is output to the column line CL. Here, similarly to the reset voltage, the offset voltage is generated by the drive transistor M4 configured as the source follower, so that the image signal voltage can be expressed as "Vsignal + Voffset". In this state, when the SHS transistor M7 is turned on by 'SHS', the image signal voltage output to the column line CL is stored in the image signal voltage storage capacitor C _S. Of course, the SHR transistor M6 is turned off by 'SHR', and the Col transistors M9 and M11 are both turned off by the column line select signal Col. .

Subsequently, the reset voltage and the image signal voltage stored in the capacitors C _R and C _S according to the turn-on state of the Col transistors M7 and M11 by the column line selection signal Col are respectively converted into the buffer amplifiers M10 and M12. Are input to the input terminals (+,-) of the operational amplifier 30 functioning as a subtractor. The operational amplifier 30 outputs an output voltage Vout, which is an output signal, by subtracting the reset voltage and the image signal voltage input to the non-inverting input terminal (+) and the inverting input terminal (-), respectively. In this case, the output voltage Vout may be expressed by Equation 1 below.

Vout = Vsignal-Vreset = (Vsignal + Voffset)-(Vreset + Voffset)

As described above, the CDS is implemented on the basis of the fact that the reset voltage and the image signal voltage output to the column line CL include the same offset voltage generated by the drive transistor M4. That is, the offset voltage is common in the reset voltage and the image signal voltage, and the offset voltage is removed by subtracting the reset voltage and the image signal voltage.

However, the CDS according to the prior art has a large number of elements required by the seven transistors M6 to M12 and two capacitors C _R and C _S , and thus has a high difficulty in high integration. In particular, in the case of a capacitor, since the implementation requires a relatively large space compared to other devices, such as transistors, there are many difficulties in high integration.

Meanwhile, the transistor M5 illustrated in FIG. 1 and not described is driven with a constant bias voltage Vb1 as a bias transistor of the pixel drive transistor M4. The transistor M5 connects the column line CL to the ground terminal when the selection signal SEL of the pixels in the same column line CL transitions to a low level and the SEL transistor M3 is turned off. Like the transistor M5, the transistors M13 and M14 are implemented as PMOS transistors and provide a power supply voltage VDD to the buffer amplifiers M10 and M12.

In addition, the transistor M8 is connected between the first electrodes of the capacitors C _R and C _S to keep the potentials of the nodes A and B the same. The control signal DDS transitions to a high level after the operational amplifier 30 receives the reset voltage and the image signal voltage from the capacitors C _R and C _S , respectively, and subtracts them. As a result, the transistor M8 is turned on by the control signal DDS to connect the nodes A and B to each other. As a result, nodes A and B have the same potential. However, since the buffer amplifiers M10 and M12 are not designed with the same size (W / L), the same voltage is not input to the operational amplifier 30, and a voltage having a slight potential difference is input and output.

The signal output through the operational amplifier 30 and the resultant value previously subtracted through the operational amplifier 30 are subtracted through the following predetermined circuit although not shown. As a result, the offset voltage generated by the buffer amplifiers M10 and M12 of the CDS 20 is eliminated.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and the circuit is simple, and highly integrated, while having a correlated double sampling circuit (CDS) capable of removing FPN (Fixed Pattern Noise) and having the same. Its purpose is to provide a CMOS image sensor.

According to an aspect of the present invention, a reset signal and an image signal output from a pixel unit in which a plurality of pixels are arranged in a matrix form are received through a column line, and transmitted in response to a first control signal. A first switching unit and a first electrode connected to the first switching unit receive the reset signal and the image signal transmitted through the first switching unit through the first electrode, the node of the node connected to the second electrode A first capacitor sampling the difference signal between the reset signal and the video signal according to the potential, and connected between the node and the voltage supply terminal, and pulling up the potential of the node to a constant voltage in response to a second control signal; Or a pull-up transistor for maintaining the floating state, a source follower buffer amplifier for amplifying and outputting a difference signal sampled to the first capacitor, and the column. In response to the selection signal for selecting and providing a second correlated double sampling circuit including a second switch for outputting the output of the buffer amplifier.

In addition, the present invention according to another aspect for achieving the above object is connected to the correlated double sampling circuit having the above configuration, and the output terminal of the plurality of correlated double sampling circuit, the buffer amplification unit of the correlated double sampling circuit It provides a CMOS image sensor further comprises an offset remover for removing the offset voltage generated by the.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, parts denoted by the same reference numerals throughout the specification represent the same elements performing the same function.

Example 1

2 is a circuit diagram illustrating a CDS according to a first preferred embodiment of the present invention. First, the unit pixel having the 4-T (4-Transistor) structure will be described.

Referring to FIG. 2, in the CDS 120 according to the first exemplary embodiment of the present invention, a plurality of unit pixels 110 are arranged in a plurality of unit pixels 110 during a reset readout period and a signal readout period to form corresponding column lines CL. Four transistors M6 to M9 and one capacitor C are read to read the reset voltage and the image signal voltage output through the same path.

The switching transistor M6 is connected between the column line CL and the capacitor C, and resets the reset voltage in response to the signal sample hold signal (hereinafter referred to as 'SHS') during the reset readout period. The signal is transmitted to one electrode, and the image signal voltage is transmitted to a signal reading section.

The capacitor C is connected between the switching transistor M6 and the node A to store the reset voltage transmitted through the switching transistor M6 in the reset readout section, and to store the reset voltage and the switching voltage stored in the signal readout section. The difference value of the image signal voltage transmitted through the transistor M6 is stored. In fact, 'VDD- (Vreset + Voffset)' is stored in the capacitor C in the reset read section. Here, the reset voltage is 'Vreset + Voffset'.

The pull-up transistor M7 has the reset signal RST enabled at a high level (logic '1') and at the same time enabled at a low level (logic '0'). In response to the control signal Cont, the power supply voltage VDD is transferred to the node A connected to the second electrode of the capacitor C during the reset read period, thereby raising the potential of the node A.

The drive transistor M8 amplifies and outputs VDD- (Vreset-Vsignal) stored in the capacitor C during a sampling period with a source follower buffer amplifier having an input terminal connected to the node A.

The switching transistor M9 is connected to the drive transistor M8 and outputs a voltage amplified and output from the drive transistor M8 in response to the column line select signal Col. At this time, the switching transistor M9 outputs 'VDD- (Vreset-Vsignal) -Vcds_offset' including the offset voltage Vcds_offset generated by the drive transistor M8.

The unit pixel 110 has a 4-T structure and includes one photodiode PD and four NMOS transistors M1 to M4. Since the unit pixel 110 has the same structure as a general configuration, a detailed description thereof will be omitted herein. However, as shown in FIG. 2, the select transistor M3 operated by the low line select signal SEL is connected between the power supply voltage terminal and the drive transistor M4. However, this is an example of the drive transistor M4 and the column. It may be connected between the lines CL to transfer the amplified signal of the drive transistor M4 to the column line CL. That is, the drain of the drive transistor M4, which is composed of a source follower and functions as a buffer amplifier, may be connected to the power supply voltage terminal, and the source may be connected to the drain of the select transistor.

Hereinafter, a read operation of the CDS according to the first embodiment of the present invention shown in FIG. 2 will be described with reference to FIG. 3. 3 is an operation waveform diagram of each signal shown in FIG. 2.

2 and 3, during the reset readout period, the pull-up transistor M7 is turned on by the control signal Cont enabled to the low level to be connected to the second electrode of the capacitor C. Node A is close to the power supply voltage VDD. In this state, the reset transistor M2 is turned on by the reset signal RST enabled to the high level, and the power supply voltage VDD is applied to the floating diffusion region FD. Accordingly, the floating diffusion region FD is reset to a potential level corresponding to the power supply voltage VDD. Then, the drive transistor M4 is turned on by the potential of the floating diffusion region FD reset to the predetermined potential level, and in this state, the select transistor M3 is selected by the low line select signal SEL and turned. When turned on, a reset voltage including an offset voltage is output to the column line CL. Usually, the offset voltage is generated by drive transistor M4 configured as a source follower. That is, the reset voltage can be expressed as "Vreset + Voffset". In this state, when the switching transistor M6 is turned on by 'SHS', the reset voltage output to the column line CL is stored in the capacitor C. As a result, 'VDD- (Vreset + Voffset)' is stored and maintained in the capacitor C.

Thereafter, in the signal read section, the control signal Cont transitions from the low level to the high level so that the pull-up transistor M7 is turned off. As a result, the node A connected to the second electrode of the capacitor C is floated. In this state, when the reset transistor M2 is turned off by the reset signal RST having a low level, and the transfer transistor M1 is turned on by the transfer signal TR, the photodiode PD is irradiated. The electrons generated in the photodiode PD by the generated light are transferred to and accumulated in the floating diffusion region FD through the transfer transistor M1. At this time, holes are generated together with the electrons, and these holes are diffused to the silicon substrate. The floating diffusion region FD rises to a potential of a level corresponding to the accumulated charge to turn on the drive transistor M4. In this state, when the select transistor M3 is selected and turned on by the low line select signal SEL, the image signal voltage including the offset voltage is output to the column line CL. Here, similarly to the reset voltage, the offset voltage is generated by the drive transistor M4 configured as the source follower, so that the image signal voltage can be expressed as "Vsignal + Voffset". In this state, when the switching transistor M8 is turned on by 'SHS', the image signal voltage output to the column line CL is transferred to the first electrode of the capacitor C. Accordingly, the second electrode of the capacitor C is changed to 'VDD- (Vreset-Vsignal)' by a coupling effect. That is, at the node A, 'VDD- (Vreset-Vsignal)' from which the offset voltage Voffset is removed appears. This operation is performed simultaneously in any same column line, and the difference of the image signal voltage at the reset voltage is shown at the node A, so that the correlated double sampling for the pixel is performed.

Thereafter, in the sampling period, the column line selection signal Col is enabled to a high level, and thus the switching transistor M9 is turned on to remove the potential of the node A, that is, the offset voltage Voffset. Vreset-Vsignal) 'is output through the buffer amplifier 130. Here, the buffer amplifier 130 is shown as being connected to one CDS 120, but this is for convenience of description, and is actually connected to all the column lines implemented in the chip. That is, only the analog signal of the CDS 120 selected by the column line selection signal Col is output to the buffer amplifier 130. However, depending on the design, one CDS 120 may be installed.

On the other hand, as described above, the analog signal output from the CDS 120 is also offset voltage (Vcds−) by using the drive transistor M8 configured as a source amplifier in the CDS 120 illustrated in FIG. 2. offset). The offset voltage Vcds_offset can be removed by providing a CDS offset remover at the output terminal of the CDS 120.

As shown in FIG. 4, the CDS offset remover 140 includes two NMOS transistors M11 and M12, two capacitors Ccds and Cvdd, and one comparator 141. Like the buffer amplifier 130 illustrated in FIG. 2, the CDS offset remover 140 is connected to all column lines implemented in the chip. That is, it is connected to the output terminals of all CDSs connected to all column lines constituting the array, and the selection is made by the corresponding column line selection signal Col.

The switching transistor M11 is connected between the output terminal of the CDS 120 and the inverting input terminal (-) of the comparator 141, and responds to the CDS signal sample and the hold signal (hereinafter referred to as 'SHS_cds'). Pass the output signal of. At this time, the output signal of the CDS 120 is 'VDD- (Vreset-Voffset) -Vcds_offset'. In addition, 'SHS_cds' has a high level when the control signal Cont is at a high level in the sampling period and the column line selection signal Col is at a high level.

The capacitor Ccds of the CDS 120 in which the first electrode is connected to the ground voltage terminal and the second electrode is connected between the switching transistor M11 and the inverting input terminal of the comparator 141 is transferred through the switching transistor M11. Stores the output signal, ie 'VDD- (Vreset-Vsignal) -Vcds_offset'.

The switching transistor M12 is connected between the output terminal of the CDS 120 and the non-inverting input terminal (+) of the comparator 141, and responds to the power supply voltage reset sample and the hold signal (hereinafter referred to as 'SHR_VDD'). 120 outputs an output signal. At this time, the output signal of the CDS 120 is 'VDD-Vcds_offset', which will be described in detail later. In addition, 'SHS_vdd' has a high level when the control signal Cont is at a low level and the column line selection signal Col is at a high level in the sampling period. That is, an inverted signal of 'SHS_cds' is obtained.

The capacitor Cvdd has a CDS (first electrode connected to the ground voltage terminal, a second electrode connected between the switching transistor M12 and the non-inverting input terminal of the comparator 141 and transferred through the switching transistor M12). The output signal of '120', that is, 'VDD-Vcds_offset' is stored and maintained.

The comparator 141 is composed of an operational amplifier and subtracts and outputs the voltages stored in the capacitors Ccds and Cvdd, that is, 'VDD- (Vreset-Vsignal) -Vcds_offset' and 'VDD-Vcds_offset', respectively. Therefore, the offset signal Vcds-offset 'is not included in the output signal of the comparator 141. That is, the output signal Vout of the comparator 141 becomes 'Vreset-Vsignal' from which the offset voltage is removed.

An offset removing operation of the CDS offset removing unit 140 having such a configuration will be described with reference to FIG. 3.

3 and 4, when 'SHS_cds' is enabled at the high level while the corresponding column line selection signal Col is selected and enabled at the high level in the T _{RS period} of the sampling period, the switching transistor ( M11) is turned on and the output signal of the CDS 120, that is, 'VDD- (Vreset-Vsignal) -Vcds_offset' is input to the first electrode of the capacitor Ccds and stored.

Thereafter, in the T _ss period, 'SHS_cds' transitions to a low level so that the switching transistor M11 is turned off, 'SHR_vdd' is enabled to a high level, and thus the switching transistor M12 is turned on. When the control signal cont is enabled at the low level, the pull-up transistor M7 is turned on so that 'VDD-Vcds_offset' from the CDS 120 is connected to the capacitor Cvdd through the switching transistor M9. It is input to the first electrode and stored. As a result, the voltages stored in the capacitors Ccds and Cvdd, that is, 'VDD- (Vreset-Vsignal) -Vcds_offset' and 'VDD-Vcds_offset' are applied to the input terminals of the comparator 141, respectively. The comparator 141 outputs the difference value between these two voltages. Accordingly, the comparator 141 outputs 'Vreset-Vsignal' from which the offset voltage is removed.

Meanwhile, FIG. 5 illustrates a switched capacitor amplifier as another embodiment of the offset remover for removing the offset voltage of the CDS 120. 6 is an operation waveform diagram of pixel signals, CDS signals, and chip signals illustrated in FIG. 5.

As shown in FIG. 5, the CDS offset remover 150 according to another embodiment includes one NMOS transistor M11, two capacitors Ccds and Cvdd, and one operational amplifier 151.

In the capacitor Ccds, a first electrode is connected to the output terminal of the CDS 120, and a second electrode is connected to the inverting input terminal (−) of the operational amplifier 151. The capacitor Cvdd has a first electrode connected between the inverting input terminal (−) and the output terminal of the operational amplifier 151. The switching transistor M11 is connected in parallel with the capacitor Cvdd to operate according to the switching signal SW. The inverting input terminal of the operational amplifier 151 is connected to the second electrode of the capacitor Ccds, and the reference voltage Vref is input to the non-inverting input terminal +.

An offset removing operation of the CDS offset removing unit 150 having such a configuration will be described with reference to FIG. 6.

As shown in FIG. 6, when the switching signal SW is enabled at a high level in a state where the corresponding column line selection signal Col is selected and enabled at a high level in the T _RS section of the sampling period, the switching transistor. The M11 is turned on so that the operational amplifier 151 outputs an output signal Vout corresponding to the reference voltage Vref. In this case, the difference between the reference voltage Vref and the output signal of the CDS 120, 'Vref-VDD- (Vreset-Vsignal) -Vcds_offset', is transmitted to the first electrode of the capacitor Ccds.

Subsequently, when the switching signal SW transitions to the low level in the T _ss period, the switching transistor M11 is turned off and the inverting input terminal of the operational amplifier 151 is floated. In this state, the control signal cont When enabled to the low level, the pull-up transistor M7 is turned on so that 'VDD-Vcds_offset' is input from the CDS 120 through the switching transistor M9 to the first electrode of the capacitor Ccds, and eventually The charge stored in the capacitor Ccds is transferred to the capacitor Cvdd during the T _RS period, and the operational amplifier 151 outputs 'Vref- (Vreset-Vsignal)'. That is, 'Vref- (Vreset-Vsignal)' from which the offset voltage Vcds_offset of the CDS is removed is output as a difference between 'Vref-VDD- (Vreset-Vsignal) -Vcds_offset' and 'VDD-Vcds_offset'.

Example 2

FIG. 7 is a circuit diagram illustrating a CDS according to a second preferred embodiment of the present invention, and has the same configuration as the first illustrative embodiment shown in FIG. However, Example 1 is a circuit for reading a signal generated in a unit pixel having a 4-T structure, whereas Example 2 is a circuit for reading a signal generated in a unit pixel having a 3-T (3-Transistor) structure. It is a circuit diagram for.

As shown in FIG. 7, first, the unit pixel 210 has a 3-T structure, and includes one photodiode PD and three NMOS transistors M1 to M3. The cathode of the photodiode PD is connected between the source of the reset transistor M1 and the gate of the drive transistor M3. The reset transistor M1 is connected between the power supply voltage terminal and the gate of the drive transistor M3. The select transistor M2 is connected between the power supply voltage terminal and the drain of the drive transistor M3. The drive transistor M3 is connected between the source of the select transistor M2 and the column line CL to function as a source follower buffer amplifier.

The operation of the unit pixel 210 will be described below. Unlike a read operation of a unit pixel having a 3-T structure, a read operation of a unit pixel having a 3-T structure is performed by first reading a signal generated by irradiation of light and then reading a reset signal.

First, when light is irradiated to the photodiode PD, electrons and holes are formed in the junction region of the photodiode PD, holes diffuse into the silicon substrate, electrons are axially accumulated in the junction region, and the accumulated electrons When the drive transistor M3 having the source follower configuration is turned on, and the select transistor M2 is selected, an output voltage of a unit pixel is generated according to a voltage change of the floating diffusion region FD to generate information on the pixel. Analog output. That is, when light is irradiated to the photodiode PD, a signal having a level corresponding to the irradiated light is generated. The drive transistor M3 amplifies a signal generated through the photodiode PD (hereinafter referred to as an image signal voltage), and the amplified image signal voltage operates in response to the low line select signal SEL. It is transmitted to the corresponding column line CL through M2.

Thereafter, when the reset signal RST is enabled to the high level, the reset transistor M1 is turned on. Accordingly, the power supply voltage VDD is applied to the floating diffusion region FD and reset to the predetermined level. The drive transistor M3 amplifies the potential (hereinafter referred to as a reset voltage) reset to a predetermined level, and the amplified reset voltage is applied through the select transistor M2 which operates in response to the low line select signal SEL. Transmitted to the column line CL.

On the other hand, the image signal voltage is represented by 'Vsignal-Voffset', the reset voltage is represented by 'Vreset-Voffset'.

The CDS 220 is composed of one capacitor C and four NMOS transistors M5 to M8 in the same manner as the CDS 120 shown in the first embodiment. However, since the CDS 220 according to the second embodiment needs to read the signal of the unit pixel 210 having the 3-T configuration, a drain voltage of 1 to 2 V is applied to the drain of the switching transistor M6 due to its characteristics. do. That is, in the case of the unit pixel 210 having the 3-T configuration, the image signal voltage is first read before the reset voltage is read.

Hereinafter, a read operation of the CDS according to Embodiment 2 of the present invention will be described with reference to FIG. 7.

Referring to FIG. 7, the pull-up transistor M6 is turned on by the control signal Cont enabled at the low level during the signal read period, and is connected to the node A connected to the second electrode of the capacitor C. Referring to FIG. Approaches the drain voltage VM. The drain voltage VM is approximately 1 to 2V. In this state, in this state, when the switching transistor M5 is turned on by 'SHS', the image signal voltage outputted to the column line CL, that is, 'Vsignal-Voffset' is the first of the capacitor C. Delivered to the electrode. Accordingly, 'VM- (Vsignal-Voffset)' is sampled and stored in the capacitor C.

Thereafter, in the reset read period, the reset transistor M1 is turned on by the reset signal RST enabled to the high level, and the power supply voltage VDD is applied to the floating diffusion region FD. Accordingly, the floating diffusion region FD is reset to a potential level corresponding to the power supply voltage VDD. Then, the drive transistor M3 is turned on by the potential of the floating diffusion region FD reset to the predetermined potential level, and in this state, the select transistor M2 is selected by the low line select signal SEL and turned. When turned on, a reset voltage including an offset voltage is output to the column line CL. In this state, when the switching transistor M6 is turned on by 'SHS', the reset voltage output to the column line CL is input to the first electrode of the capacitor C. At this time, the node A connected to the second electrode of the capacitor C maintains the floating state because the switching transistor M6 is turned off by the control signal Cont. Accordingly, the second electrode of the capacitor C is changed to 'VM- (Vsignal-Vreset)' by the coupling effect. That is, at the node A, 'VM- (Vsignal-Vreset)' with the offset voltage Voffset removed appears. This operation is performed simultaneously in any same column line, and the difference of the image signal voltage at the reset voltage is shown at the node A, so that the correlated double sampling for the pixel is performed.

Thereafter, in the sampling period, the column line selection signal Col is enabled to a high level, and thus the switching transistor M8 is turned on to remove the potential of the node A, that is, the offset voltage Voffset. Vreset-Vsignal) 'is output through the buffer amplifier 230. Here, the buffer amplifier 230 is shown as being connected to one CDS 220, but this is for convenience of description and is actually connected to all column lines implemented in the chip. That is, only the analog signal of the CDS 220 selected by the column line selection signal Col is output to the buffer amplifier 230. However, depending on the design, one CDS 220 may be installed.

Of course, in the second embodiment as in the first embodiment, the offset removing unit shown in FIGS. 4 and 5 may be installed at the rear end to remove the offset voltage generated in the CDS 220.

On the other hand, the transistors M5 and M10 shown in FIGS. 2, 4 and 5 and not described are pull-down transistors, and are always turned on by the bias signals Vb1 and Vb2 so that the column line CL ) And ground terminal. In particular, since the transistor M5 is turned on during the read operation, the current path between the first electrode of the capacitor C and the ground voltage can be controlled through the switching transistor M6. The same is true of the transistors M4 and M9 shown in FIG.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, in the CMOS image sensor, by implementing the CDS for removing the fixed pattern job with one capacitor and four transistors, the circuit is simple, high integration is possible, and stable pattern noise is stably prepared. Can be removed.

Further, according to the present invention, the offset voltage generated from the CDS can be stably removed by adding an offset remover for removing the offset voltage generated in the CDS at the rear end of the CDS in column units.

Claims (22)

A first switching unit configured to receive a reset signal and an image signal output from a pixel unit in which a plurality of pixels are arranged in a matrix form, and to transmit the reset signal and the image signal in response to the first control signal; A first electrode is connected to the first switching unit to receive the reset signal and the image signal transmitted through the first switching unit through the first electrode, the reset signal according to the potential of the node connected to the second electrode A first capacitor sampling a difference signal between the video signal and the video signal; A pull-up transistor connected between the node and a voltage supply terminal, the pull-up transistor configured to pull up the potential of the node to a predetermined voltage or to maintain a floating state in response to a second control signal; A source follower buffer amplifier for amplifying and outputting the difference signal sampled to the first capacitor; And A second switching unit outputting an output of the buffer amplifier in response to a selection signal for selecting the column line Correlated double sampling circuit comprising a. The method of claim 1, And the unit pixel has a 4-T structure. The method of claim 2, The pull-up transistor is a power supply voltage supplied from the voltage supply terminal by being turned on by the second control signal when the reset signal is input to the first electrode of the first capacitor through the first switching unit. A correlated double sampling circuit for pulling up the node. The method of claim 3, wherein And the pull-up transistor is turned off by the second control signal when the image signal is input to the first electrode of the first capacitor through the first switching unit to float the node. The method of claim 4, wherein The first capacitor samples and stores a difference signal between the power supply voltage input to the second electrode and the reset signal input to the first electrode while the pull-up transistor is turned on, and the pull-up And a correlation double sampling circuit for sampling the difference signal between the reset signal sampled while the transistor is turned off and the image signal input to the first electrode. The method of claim 1, And the unit pixel has a 3-T structure. The method of claim 6, The pull-up transistor is turned on by the second control signal when the image signal is input to the first electrode of the first capacitor through the first switching unit and is supplied with the voltage supplied from the voltage supply terminal. Correlated double sampling circuitry that pulls up nodes. The method of claim 7, wherein And the pull-up transistor is turned off by the second control signal when the reset signal is input to the first electrode of the first capacitor through the first switching unit to float the node. The method of claim 8, The first capacitor samples and stores a difference signal between the voltage input to the second electrode and the image signal input to the first electrode while the pull-up transistor is turned on, and the pull-up transistor And a sampling signal of a difference signal between the image signal sampled and the reset signal input to the first electrode while is turned off. The method of claim 9, Correlated double sampling circuit having a voltage supplied from the voltage supply stage having 1 ~ 2V. The method according to any one of claims 1 to 10, 2. The correlated double sampling circuit of claim 1, wherein the first switching unit, the second switching unit, and the buffer amplifier unit comprise an NMOS transistor, and the pull-up transistor comprises a PMOS transistor. The method of claim 11, And the NMOS transistor of the first switching unit is turned on while the reset signal and the image signal are read into the column line by the first control signal. The method of claim 12, And a PMOS transistor of the pull-up transistor is turned on while the reset signal is read into the column line by the second control signal. A correlated double sampling circuit of any one of claims 1 to 10; And It is connected to the output terminal of the correlated double sampling circuit, and includes an offset remover for removing the offset voltage generated by the buffer amplifier of the correlated double sampling circuit, And the correlated double sampling circuit is connected one per column line in the plurality of column lines. The method of claim 14, wherein the offset remover, A third switching unit connected to the second switching unit of the correlated double sampling circuit and transferring a first output signal of the correlated double sampling circuit transmitted from the second switching unit according to a third control signal; A second capacitor connected between the third switching unit and a ground voltage terminal to receive and sample the first output signal transmitted through the third switching unit through a first electrode; A fourth switching unit connected to the second switching unit and transferring a second output signal of the correlated double sampling circuit transmitted from the second switching unit according to a fourth control signal; A third capacitor connected between the fourth switching unit and the ground voltage terminal to receive and sample the second output signal transmitted through the fourth switching unit through a first electrode; And The first electrode of the second capacitor and an inverting input terminal are connected, the first electrode of the third capacitor and a non-inverting input terminal are connected, and the first and second capacitors are stored in the second and third capacitors and input through the input terminal. A comparator for outputting a difference signal between an output signal and the second output signal CMOS image sensor comprising a. The method of claim 15, And the first output signal is a difference signal between the video signal and the reset signal, and the second output signal is a signal corresponding to a voltage pulled up to the node by the pull-up transistor. The method of claim 16, And the third switching unit transfers the first output signal to the first electrode of the second capacitor while the first control signal has a low level and the second control signal has a high level. The method of claim 17, And the fourth switching unit transfers the second output signal to the second electrode of the third capacitor while the first control signal has a low level and the second control signal has a low level. The method of claim 17, And a pull-down transistor connected between the column line, the point connected to the first switching unit, and a ground voltage terminal to operate according to a bias signal. The method of claim 14, wherein the offset remover, A second capacitor having a first electrode connected to the second switching unit of the correlated double sampling circuit, and receiving first and second output signals output from the second switching unit to the first electrode; An operational amplifier connected to the second electrode of the second capacitor and an inverting input terminal and amplifying and outputting a difference signal between a signal input to the inverting input terminal and a reference signal input to the non-inverting input terminal; Connected between a second electrode of the second capacitor and an output terminal of the operational amplifier, and operated by a third control signal while the first output signal is input so that the output of the operational amplifier corresponds to the reference signal; A third switching unit configured to control the output and to be inoperative by the third control signal while the second output signal is input to control the output of the operational amplifier to be a difference signal between the reference signal and the first output signal. ; And A first electrode is connected to the inverting input terminal of the operational amplifier, a second electrode is connected to the output terminal of the operational amplifier and connected in parallel with the third switching unit, and while the second output signal is inputted from the second capacitor A third capacitor to store the transferred charge CMOS image sensor comprising a. The method of claim 20, And the first output signal is a difference signal between the video signal and the reset signal, and the second output signal is a signal corresponding to a voltage pulled up to the node by the pull-up transistor. The method of claim 21, The third switching unit operates while the first control signal has a low level, the second control signal has a high level, the first control signal has a low level, and the second control signal has a low level. CMOS image sensor inactive while having.

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