KR100773904B1 - LAN switch - Google Patents

Abstract

The present invention provides an input and output media access controller for connecting to an external physical layer unit to perform transmission and reception of Ethernet frames; Input and output GFP controllers that connect to external Synchronous Optical Network (SONET) / Synchronous Digital Hierarchy (SDH) units to send and receive GFP (Link Generic Frame Procedure) / LAPS (Link Access Procedure for Synchronous Digital Hierarchy) frames. ; An input and output data queue configured to store input and output frames inputted and outputted from the input and output media access controller and the input and output GFP controller in an internal frame form; Analyze the input frame from the input data queue to determine discarding or marking, and transfer the non-discarded input frame to the data memory controller below, and transmit control information on the transferred data to the following input control queue and external control memory. An input packet processor for storing in the; An input control queue and an input packet queue for temporarily storing a control frame for storing an input frame from the input packet processor into an external data memory; A data memory control unit for storing an input frame from the input packet processor in an external data memory and outputting a data frame stored in the external data memory requested by an output packet processor; An output packet processor configured to sequentially read the control information stored in the external control memory and to request the data memory control unit to output the frame data in the external data memory through the output control queue described below; ; The present invention provides a LAN switch including a control frame for reading an output frame from the external data memory, an output control queue for temporarily storing the data frame, and an output packet queue.

LAN switch, Generic Frame Procedure (GFP), Link Access Procedure for SDH (LAPS), Ethernet

Description

LAN switch {LAN switch}

1 is a configuration diagram of a LAN switch according to the present invention;

2 is an example of a timing diagram of a reduced medium independent interface (RMII) receiving side applied to the present invention;

3 is another example of an RMII receiving side timing diagram applied to the present invention;

4 is another example of a timing diagram of an RMII receiving side applied to the present invention;

5 is an example of a timing diagram of an RMII transmission side applied to the present invention;

6 is another example of a timing diagram of an RMII transmission side applied to the present invention;

7 is a block diagram of a data queue DQ applied to the present invention;

8 is a diagram showing a data configuration of a data queue DQ applied to the present invention;

9 is a diagram illustrating a data configuration of a status & length field (SLF) field of a data queue (DQ) according to the present invention;

10 is a timing diagram of a data queue interface (DQI) to which the present invention is applied.

11 is a framing alignment state diagram applied to the present invention (framing alignment state diagram)

12 is a block diagram of a buffer queue BQ applied to the present invention;

FIG. 13 is a diagram showing the data configuration of a buffer queue BQ applied to the present invention; FIG.

14 is a timing diagram for a buffer queue interface (BQI) applied to the present invention;

15 is a data alignment state diagram for the buffer queue (BQ) / free queue (FQ) applied to the present invention,

16 is a block diagram of a pre-queue applied to the present invention;

17 is a block diagram of a completion queue (CQ) applied to the present invention;

18 is a view showing a structural unit of a completion queue (CQ) applied to the present invention,

19 is a view showing a message constituting a completion queue (CQ) applied to the present invention,

20 is a timing diagram for a completion queue interface applied to the present invention.

<Description of Symbols for Main Parts of Drawings>

1: input media access controller

2: Input GFP (Generic Frame Procedure) Controller

3: input control packet processor 4: input data queue

5: input packet processor 6: input control queue

7: input packet queue 8: packet buffer controller

9: output control queue 10: output packet queue

11: output packet processor 12: output data queue

13: output media access controller 14: output GFP controller

15: output control packet processor 16: main controller interface controller

17: timer controller 18: clock generator

The present invention relates to a LAN (Local Area Network) switch, which is a high-speed switch for transmitting packets between data link segments of a communication system, and more particularly, to a user connection capable of differentially providing a service on an application basis of a user. The present invention relates to a LAN switch that supports Ethernet / Generic Frame Procedure (GFP) / Link Access Procedure for SDH (Synchronous Digital Hierarchy) connections and provides a Quality of Service (QoS) function suitable for a high-speed switch. .

Conventionally, most LAN switches transmit traffic based on a Media Access Control (MAC) address. These various LAN switches are collectively referred to as frame switches. LAN switches are classified as cut-through packet switching or cumulative transport packet switching, depending on the method used to transport the traffic. Multilayer switches are an intelligent subset of LAN switches.

LAN switches do not consume router ports, do not require a new network interface card (NIC), and improve LAN segment performance. As switching ports are added to the LAN, overall throughput increases and networking performance increases. LAN switching sends the appropriate port to the destination when each LAN is inserted into the switch, compared to the list of known addresses for the destination MAC address.

These LAN switches are based on Ethernet. Recently, ITU-T G.7041 provides signals such as xGbE (x Gigabit Ethernet), ESCON (Enterprise System Connection), Fiber Channel (FC), and Digital Video Broadcasting (DVB) for effective transmission over a telecommunication network. The Generic Framing Procedure (GFP) has been standardized for mapping to NETwork / SDH (Synchronous Digital Hierarchy) signals or Optical Channel Data Units (OCDUs) from Optical Transpor Hierarchy (OTH).

Accordingly, there is a demand for the development of a LAN switch capable of accommodating Ethernet frame, GFP frame, and LAPS frame data to provide mutual switching service between Ethernet / GFP / LAPS frames.

Accordingly, the present invention has been made to meet the above-mentioned demands of the prior art, and supports an Ethernet / GFP / LAPS connection that is suitable for a user-connected high-speed switch capable of differentially providing a service on a per-application basis of a user, and has a QoS function. The purpose is to provide a LAN switch that provides a.

In order to achieve the above object, a LAN switch according to the present invention comprises: an input and output media access controller for connecting to an external physical layer unit and performing transmission and reception of an Ethernet frame; An input and output GFP controller connected to an external SONET / SDH unit to transmit and receive a GFP / LAPS frame; An input and output data queue configured to store input and output frames input and output by the input and output media access controller and the input and output GFP controller in an internal frame form; Analyze the input frame from the input data queue to determine discarding or marking, and transfer the non-discarded input frame to the data memory controller below, and transmit control information on the transferred data to the following input control queue and external control memory. An input packet processor for storing in the; An input control queue and an input packet queue for temporarily storing a control frame for storing an input frame from the input packet processor into an external data memory; A data memory control unit for storing an input frame from the input packet processor in an external data memory and outputting a data frame stored in the external data memory requested by an output packet processor; An output packet processor sequentially reading out control information stored in the external control memory and requesting the data memory control unit to output the frame data in the external data memory through the output control queue described below; And a control frame for reading an output frame from the external data memory, an output control queue for temporarily storing the data frame, and an output packet queue.

Hereinafter, a LAN switch according to the present invention will be described in detail with reference to the accompanying drawings.

The entire block of a LAN switch according to the invention is shown in FIG.

The LAN switch according to the present invention includes an input media access controller (iMAC) 1, an input ingress generic frame procedure (iGFP) controller 2, an input control packet processor (iCPP) (3), Ingress Datai Queue (iDQ) (4), Ingress Packet Processor (iPP) (5), Ingress Control Queue (iCQ) (6), Input Packet Queue (Ingress Packet Queue; iPQ) (7), Packet Buffer Controller (8), Egress Control Queue (eCQ) (9), Egress Packet Queue (ePQ) (10) , An output packet processor (ePP) 11, an output data queue (eDQ) 12, an input media access controller (iMAC) 13, and an output GFP (Egress) Generic Frame Procedure (eGFP) Controller 14, Egress Control Packet Processor (eCPP) 15, Main Control Unit (CPU) The CPU Interface Controller (CIC) 16, the Timer Controller (TIC) 17, the Clock Generator (CLK) 18, the Control Memory 19 and the Data Memory 20 It is configured to include.

The input media access controller 1 receives an Ethernet frame of 10 Mbps or 100 Mbps from an Ethernet physical layer chip by connecting to an Ethernet medium layer chip compliant with the IEEE 802.3 standard and a reduced medium independent interface (RMII) standard, and receives an Ethernet frame. Converts the data into an internal frame form and delivers the data to an Ingress Data Queue (iDQ) 4.

The input GFP controller 2 includes an external Synchronous Optical Network (SONET) / Synchronous Digital Hierarchy (SDH) unit and an ITU-T G.7041 Generic Frame Procedure Interface (GFP) standard / ITU-T X.86 Link Access Procedure. for SDH (Synchronous Digital Hierarchy)] standard, receives GFP / LAPS frame, extracts Ethernet frame, converts received Ethernet frame into internal frame, and delivers it to input data queue (iDQ) (4). do. In addition, control is performed according to the ITU-T G.7041 standard to check for abnormal conditions, and when an abnormality is detected, an alarm is issued to a CPU (not shown).

The input control packet processor 3 is connected to a main controller (CPU) (not shown) to receive control data, convert the received data into an internal frame, and transmit the received data to an input data queue (iDQ) 4. do.

The input data queue 4 temporarily stores internal frames from the input media access controller 1, the input GFP controller 2, and the input control packet processor 3, and then transfers the internal frames to the input packet processor 5. In charge of.

The input packet processor 5 accesses the input data queue 4 and the DQI (Data Queue Interface) standard, reads internal frames stored in the input data queue 4 sequentially, and analyzes the received frames. It decides whether to discard or not and delivers normal data that has not been discarded to the corresponding destination. Data that is not discarded (hereinafter referred to as 'effective frame') is transferred to an Ingress Packet Queue (iPQ) 7, and control information on the transferred data is connected to an external packet control memory interface (PCMI) standard. It is stored in the control memory 19. Meanwhile, the control-processed frame is transmitted to the input packet queue 7 connected in the BQI (Buffer Queue Interface) standard, and the control information for the frame is an input control queue connected in the FQI (Free Queue Interface) standard. Queue; pass it to iCQ) (6). The valid frames that have been received are classified into four levels of priority according to the contents of the header, and the FQIDs (Free Queue IDs) of the frames are stored in a corresponding priority CQ (Complete Queue) in the external control memory 19.

The input control queue 6 is responsible for temporarily storing control information received from the input packet processor 5 and then transferring the control information to the packet buffer controller (PBC) 8.

The input packet queue 7 is responsible for temporarily storing the frames received from the input packet processor 5 and then transferring them to the packet buffer controller 8.

The packet buffer controller 8 analyzes the control information received from the input control queue 6 to determine whether to discard the frames stored in the input packet queue 7, and stores valid frames in the external data memory 20. . In addition, the control information received from the output control queue 9 is analyzed to read data stored in an appropriate location of the external data memory 20 and transmit the data to the output packet queue 10.

The output packet processor 11 sequentially reads output frame control information stored in a complete queue (CQ) stored in the external control memory 19, and transfers the output frame control information to the output control queue 9 connected to the FQI standard. The data stored in the output packet queue 10 received from the packet buffer controller 8 is read, converted into appropriate headers, and transferred to the output data queue 12 connected to the DQI (Data Queue Interface) standard.

The output control queue 9 is responsible for temporarily storing the control information received from the output packet processor 11 and then transferring the control information to the packet buffer controller 8.

The output packet queue 10 temporarily stores frames received from the packet buffer controller 8 and delivers the output packets to the output packet processor 11.

The output data queue 12 stores frames received from the output packet processor 11 and transmits the received frames to the output media access controller 13, the output GFP controller 14, and the output control packet processor 15. In charge of function.

The output media access controller 13 makes RMII standard connection with an Ethernet physical layer chip compliant with the IEEE 802.3 standard, and transmits 10 Mbps or 100 Mbps data to internal frames received from the output data queue 12 to the Ethernet physical layer chip. It performs the function.

The output GFP controller 14 transmits a GFP / LAPS frame by connecting an external SONET / SDH unit to an ITU-T G.7041 GFP (Generic Frame Procedure Interface) standard or an ITU-T X.86 LAPS standard. The output GFP controller 14 connects the data queue 12 to the Data Queue Interface (DQI) standard, converts the internal frames sequentially stored into Ethernet frames, and inserts a GFP / LAPS header into the converted Ethernet frames. do. In addition, the SDH processor connects to the GFPI (Generic Framing Procedure Interface) standard and transmits a GFP frame.

The output control packet processor 15 is connected to a main control unit (CPU) (not shown) and performs a function of transferring data to be transmitted to the main control unit received from the output data queue 12.

The main controller (CPU) interface controller 16 is connected to a main controller (CPU) not shown to perform data transmission and reception and alarm control. The timer controller 17 performs a function of generating various timers supplied to all blocks of the present invention. The clock generator 18 is responsible for generating various clocks supplied to all the blocks of the invention.

The control memory 19 is a memory for storing control information on input / output packets and is configured with an external SRAM memory. The data memory 20 is composed of an external DRAM memory that stores input packets.

Internal and external connection standards of the LAN switch according to the present invention are as follows.

1) RMII (Reduced Media Independent Interface) connection

The RMII standard is a frame transmission method between an Ethernet physical layer chip and a switch chip. The RMII standard converts data in byte units into 2 bit units and transmits them. The RMII receiving side connection converts a frame input from an external physical layer chip into a 2-bit stream and delivers it to the input media access controller (iMAC) 1. At this time, a control signal for indicating an effective data area exists. The RMII receiving side access signal is shown in Table 1 below, and examples of timing diagrams are shown in FIGS. 2 to 4.

[Table 1] RMII receiver signal

signal width In / Out  Explanation  Ref_Clk  One  In Reference Clock The external clock is the operating clock of the bus. The RMII specification uses a 50 MHz frequency with an accuracy of +/- 100 ppm. Crs_Dv One In Carrier Sense / Receive Data Valid If the receiving media is not IDLE, it has a value of '1' regardless of Ref_Clk. If a carrier does not exist, it has a value of '0' in synchronization with Ref_Clk.     RxD (1: 0)     2     In Receive Data Receive data synchronized with Ref_Clk. RxD has the following meaning in conjunction with Crs_Dv signal. Crs_Dv RxD (1: 0) Explanation '0' "00" IDLE '0' ≠ "00" Out-of-band signal 'One' "00" J / K signal 'One' "01" Preamble 'One' "10" Receive Error 'One' "11" SFD 'One' "xx" Frame Data (After SFD)

The RMII transmission side connection converts the frame data output from the input media access controller (iMAC) 1 into a 2-bit stream and delivers it to an external physical layer chip. At this time, a control signal for indicating an effective data area exists. The RMII transmission side connection signals are shown in Table 2, and examples of the timing diagrams are shown in Figs.

[Table 2] RMII Transmitter Signal

signal width In / Out Explanation  Tx_En  One  Out Transmit Enable TxD (1: 0) When MAC layer data exists on the bus, it has a value of '1' in synchronization with Ref_Clk.    TxD (1: 0)    2    Out Transmit Data Transmission data synchronized with Ref_Clk. TxD has the following meaning in conjunction with Tx_En signal. Tx_En RxD (1: 0) Description '0' “00” IDLE '0' ≠ “00” Out-of-band signal '1' “01” Preamble '1' “11” SFD '1' “xx” Frame Data (After SFD)

2) Data Queue Interface (DQI) Connection

The DQI connection is for converting and storing external Ethernet frame data into internal frame data or vice versa. The DQI connection includes connection signals as shown in FIG.

The data queue DQ is a 33-bit data storage device operated in a FIFO (First In First Out) method and has a data configuration as shown in FIG. 8. Ethernet frames in bytes are extended in 4 bytes and stored in the data queue (DQ). At this time, Ethernet frames are sequentially mapped from the MSB area of 4 bytes. The minimum storage capacity of the data queue DQ is 34 x 4 bytes.

In order to extract the starting point of a frame stored in the data queue DQ, a packet end flag (PEF) indicating the end of the frame is allocated to the most significant bit. That is, the most significant bit of the last 4-byte area of the frame is applied as '1' to indicate the end of the frame. In addition, a SLF (Status & Length Field) indicating the reception status and the length information of the frame stored in the data queue DQ is stored after the last 4-byte unit of the data area. The PEF value of this area is also applied as '1'. The data structure of the SLF is shown in FIG. 9 and the meaning of each field is shown in Table 3 below.

[Table 3] SLF field data

field width location Explanation  AE  One  31 Alignment Error If the received frame contains extra bits instead of bytes, it is applied as '1'.  FE  One  30 FCS Error Applies as '1' when received frame is FCS (Frame Check Sequence) error.  SE  One  29 Short Event Applies as '1' when the received frame length is less than 64 bytes.  LE  One  28 Long Event Applies to '1' when the length of received frame is more than 1518 bytes. LF 11 10-0 Length Field Indicates the length in bytes of the received frame.

The data queue DQ has a FULL / EMPTY flag. Each flag is represented by the number of SLF fields stored in the data queue DQ. When three SLF fields exist in the data queue DQ or data is stored as much as the maximum capacity of the data queue DQ, the FULL flag is applied, and when the SLF field does not exist, the EMPTY flag is applied as '1'.

Table 4 below shows connection signals of the data queue DQ, and FIG. 10 shows timing diagrams of the data queue DQ.

[Table 4] DQ connection signal

signal width In / Out Explanation Wr_CLK One IN DQ Write Clock Clock for writing data to DQ.  Data_In  33  IN DQ Data Input Consists of a 1-bit PEF field and a 32-bit data field. A stable value must be maintained at the rise of Wr_Clk.  WR  One  IN DQ Write Applies as '1' to write data to DQ. A stable value must be maintained at the rise of Wr_Clk.  FULL  One  OUT DQ Full flag It is applied as '1' when three SLF fields exist in DQ or data is stored as much as the maximum capacity of DQ. The value is changed at the rise of Wr_Clk. Rd_Clk One IN DQ Read Clock Clock for reading DQ data.  Data_Out  33  OUT DQ Data Output It consists of 1 bit PEF field and 32 bit data field. The value is changed at the rise of Rd_Clk.  RD  One  IN DQ Read It is applied as '1' to read DQ data. A stable value must be maintained at the rising edge of Rd_Clk.  EMPTY  One  OUT DQ Empty flag If there is no SLF field in DQ, it is applied as '1'. The value is changed at the rise of Rd_Clk.  INIT  One  IN DQ Initialize Applies to '1' to initialize DQ. The INIT signal operates independently of the clocks.

The data queue DQ detects a frame using a PEF field. After the reset or after the PEF value '1' is continuously detected, the start point of the frame. 11 is a framing alignment state diagram illustrating a state transition for frame detection.

3) BQI (Buffer Queue Interface) Connection

A buffer queue interface (BQI) connection is an internal connection standard for storing Ethernet frame data processed by a specific module and includes connection signals as shown in FIG. 12. The buffer queue BQ is a 33-bit data storage device operated in a FIFO (First In First Out) method and has a configuration as shown in FIG. 13. The minimum storage capacity of the buffer queue BQ is 32 x 4 bytes.

Data stored in the buffer queue (BQ) is stored in a certain area of the packet buffer designated by the free queue (FQ). In general, a free queue (FQ) is allocated for each buffer queue (BQ) data in units of 64 bytes or in units of less than or equal to the last 64 bytes of a packet. Therefore, the buffer queue BQ has a BEF (Buffer End Flag) bit that designates a boundary of the free queue FQ. The BEF bit is allocated to the top of the buffer queue (BQ) data, and '1' is applied when the last buffer queue (BQ) data in the free queue (FQ) unit is stored.

The buffer queue BQ has a FULL / EMPTY flag. Each flag is represented by the number of BEF = '1' stored in the buffer queue BQ. If three BEFs are '1' in the buffer queue BQ, the FULL flag is applied. If not, the EMPTY flag is applied as '1'. Table 5 shows connection signals of the buffer queue BQ, and FIG. 14 shows a timing diagram of the buffer queue interface.

[Table 5] Buffer queue (BQ) connection signal

signal width In / Out Explanation Wr_CLK One IN BQ Write Clock Clock for writing data to BQ.  Data_In  33  IN BQ Data Input Consists of a 1-bit BEF field and a 32-bit data field. A stable value must be maintained at the rise of Wr_Clk.  WR  One  IN BQ Write Applies as '1' to write data to BQ. A stable value must be maintained at the rise of Wr_Clk.  FULL  One  OUT BQ Full flag It is applied as '1' when there are three BEF = '1' in BQ or when data is stored as maximum capacity of BQ. The value is changed at the rise of Wr_Clk. Rd_Clk One IN BQ Read Clock Clock for reading BQ data.  Data_Out  33  OUT BQ Data Output It consists of 1 bit BEF field and 32 bit data field. The value is changed at the rise of Rd_Clk.  RD  One  IN BQ Read It is applied as '1' to read data of BQ. A stable value must be maintained at the rising edge of Rd_Clk.  EMPTY  One  OUT BQ Empty flag If BEF = '1' does not exist in BQ, it is applied as '1'. The value is changed at the rise of Rd_Clk.  INIT  One  IN BQ Initialize Authorized as '1' to initialize BQ. The INIT signal operates independently of the clocks.

As shown in FIG. 14, data synchronization between the buffer queue BQ and the free queue FQ is achieved using the BEF field of the buffer queue BQ and the LEN (Length) field (see FIG. 13) of the free queue FQ. If the BEF value is '1' when the buffer queue BQ is read by as much as the LEN (Length) value of the prequeue FQ, the synchronization state is correct. FIG. 15 is a diagram illustrating buffer queue BQ / free queue FQ data alignment showing a state transition for data synchronization detection between buffer queue BQ and free queue FQ.

4) Free Queue Interface (FQI) Connection

Free Queue Interface (FQI) connection is an internal connection standard for storing a corresponding free queue (FQ) of Ethernet frame data processed by a specific module, and is composed of connection signals as shown in FIG. 16. The prequeue FQ is a 19-bit data storage device operated in FIFO (First In First Out) scheme and has a configuration as shown in FIG. 13. The detailed description of each field is shown in Table 6.

[Table 6] Free cue (FQ) data

field width location Explanation  DF  One  18 When the Discard Flag is applied as '1', the BQ data is read and discarded by the value of the LEN field.    LEN    4    17-14 Length indicates the number of 32-bit entries of the BQ to which the same FQI is applied. LEN # 32bit Entry 0000 1 ... ... 1 111 16 FQI 14 13-0 FQ Identifier Indicates the FQ ID.

5) Complete Queue Interface (CQI) connection

Complete Queue Interface (CQI) connection is an internal connection standard for storing a free queue (FQ) list of Ethernet frame data processed by a specific module, and is composed of connection signals as shown in FIG. 17. The completion queue (CQ) is a 32-bit data storage device that operates in First In First Out (FIFO). The minimum storage capacity is 32 x 4 bytes. The completion queue (CQ) holds a list of frame queues (FQs) of frames that have been received. The completion queue CQ is composed of a combination of four types of 16-bit data structures, the configuration of which is shown in FIG. The detailed description of each field is shown in Table 7.

Table 7 Completion Queue (CQ) Messages

field width location Explanation FEF One 15 FQI End Flag If it is the last structural unit of CQ, it is applied as '1'.   L5, L4, L3, L2, L1, L0   One   14, 13, 12 Length of Last Data This is the number of bytes of data stored in the FQI included in the last message. LEN #Byte 000000 1 ... ... 111 111 63        Destination port        12        11-0 Bit-mapped Destination Port Indicates the destination port of the data stored in the FQI. DP Port 100000000000 CPU #B 010000000000 HUB #A 001000000000 WEST # 9 000100000000 EAST # 8 000010000000 PORT # 7 000001000000 PORT # 6 000000100000 PORT # 5 000000010000 PORT # 4 000000001000 PORT # 3 000000000100 PORT # 2 000000000010 PORT # 1 000000000001 PORT # 0 111111111111 ALL PORTs DRAM Addr 4 3-0 DRAM Address Lower 4 bits of DRAM address. FQI 14 13-0 Free Queue Identifier Represents the FQ ID. VLAN ID 12 11-0 Virtual LAN Identifier Indicates the VLAN ID.  P  One  14 Virtual LAN Priority Indicates the priority of the frame. Frames with a value of 1 have a higher priority.

The above four units may be combined to form a completion queue (CQ) message as shown in FIG. 19. The completion queue CQ has a FULL / EMPTY flag. Each flag is represented by the number of 32-bit completion queue (CQ) messages stored in the completion queue (CQ). Table 8 shows connection signals of the completion queue CQ, and FIG. 20 shows a timing diagram of the completion queue CQ.

[Table 8] Completion queue (CQ) connection signal

signal width In / Out Explanation Wr_CLK One IN CQ Write Clock Clock for writing data to BQ. Data_In 32 IN CQ Data Input Consists of 32-bit CQ messages. A stable value must be maintained at the rise of Wr_Clk. WR One IN CQ Write Applies as '1' to write data to CQ. A stable value must be maintained at the rise of Wr_Clk. FULL One OUT CQ Full flag Applies to '1' when data is saved as maximum capacity of CQ. The value is changed at the rise of Wr_Clk. Rd_Clk One IN CQ Read Clock Clock for reading CQ data. Data_Out 32 OUT CQ Data Output Consists of 32-bit CQ messages. The value is changed at the rise of Rd_Clk. RD One IN CQ Read It is applied as '1' to read data of CQ. A stable value must be maintained at the rising edge of Rd_Clk. EMPTY One OUT CQ Empty flag If there is no data in CQ, it is applied as '1'. The value is changed at the rise of Rd_Clk. INIT One IN CQ Initialize Applies to '1' to initialize CQ. The INIT signal operates independently of the clocks.

The operation of the LAN switch according to the present invention configured as described above will be described.

The input media access controller (iMAC) 1 receives an Ethernet frame from an external Ethernet physical layer chip connected to the RMII standard, checks the configuration / length / CRC error, etc. of the frame, and checks the received Ethernet frame. The data is converted into the data queue (DQ) connection data format as shown in the figure and stored in the input data queue (iDQ) 4. The input media access controller (iMAC) 1 maps the frame check result to the SLF field as shown in FIG. 9 and inserts it into the end of the received frame.

The input GFP (iGFP) controller 2 connects with an external SONET / SDH unit to receive a frame according to the ITU-T G.7041 / X.86 standard, extracts an Ethernet frame, and converts the received Ethernet frame into an internal frame form. To the input data queue (iDQ) 4. In addition, control is performed according to the ITU-T G.7041 standard to check for abnormal conditions, and when an abnormality is detected, an alarm is issued to a CPU (not shown). The input GFP controller 2 maps the frame check result to the SLF field shown in FIG. 9 and inserts the frame check result into the end of the received frame.

The input packet processor (iPP) 5 reads data queue (DQ) access data frames sequentially stored in the input data queue (iDQ), analyzes them in units of entries, and determines whether to discard them. It delivers to the destination. Data that is not discarded (valid frames) is transferred to the input packet queue (iPQ) 7, and control information on the transferred data is stored in an external control memory 19 connected to the Packet Control Memory Interface (PCMI) standard. do. In addition, the input packet processor 5 transfers the control-processed frame to an input packet queue (iPQ) 7 connected according to the Buffer Queue Interface (BQI) standard, and control information on the frame is transmitted to the free queue interface (FQI). ) Is transmitted to the input control queue (iCQ) 6 connected in accordance with the standard. The valid frames that have been received are classified into four levels of priority according to the contents of the header, and the FQIDs (Free Queue IDs) of the frames are stored in the corresponding Complete Queue (CQ) in the external control memory 19. do. Control information stored in the completion queue (CQ) has a data format as shown in FIG.

The packet buffer controller 8 analyzes control information received from the input control queue iCQ to determine whether to discard the frames stored in the input packet queue iPQ, and stores valid frames in the external data memory 20. In addition, the control information received from the output control queue (eCQ) 9 is analyzed, and the external data memory at an appropriate position is read and transferred to the output packet queue (ePQ) 10.

The output packet processor (ePP) 11 sequentially reads output frame control information stored in the completion queue CQ stored in the external control memory 19, and is connected to the pre-queue interface (FQI) standard. (9), the data stored in the output packet queue (ePQ) 10 received from the packet buffer controller 8, the appropriate header conversion, and then the output data queue connected to the Data Queue Interface (DQI) standard. (eDQ) 12.

The output media access controller (eMAC) 13 receives data from the output data queue (eDQ) 12 connected to the data queue interface (DQI) standard, adds the appropriate headers, and generates a CRC code to generate an external Ethernet physical layer chip. Send an Ethernet frame.

The output GFP controller (eGFP) 14 receives data from the output data queue (eDQ) 12 connected with the data queue interface specification, adds the appropriate headers and frames according to the ITU-T G.7041 / X.86 standard. And convert it to external SONET / SDH part. It also checks for abnormal conditions by performing control according to the ITU-T G.7041 standard and generates an alarm to the CPU when an abnormality is found.

On the other hand, the present invention is not limited to the above-described specific embodiments can be carried out by various modifications and modifications within the scope not departing from the gist of the present invention, the modifications and modifications in the appended claims If included, it is obvious that it belongs to the present invention.

As described above, according to the present invention, Ethernet frame, GFP frame, and LAPS frame data may be accommodated to provide mutual switching service between Ethernet / GFP / LAPS frames.

In addition, according to the present invention, it is possible to efficiently provide a switching service between frames while using a small resource (namely, a limited memory).

In addition, according to the present invention, it is possible to provide a QoS service and a rate limiting service with a small resource (small size design logic).

In addition, according to the present invention, it is possible to provide a switching service applicable to an MSPP (Multi Service Provisioning Platform) device.

In addition, according to the present invention, it is possible to implement a small size MSPP device.

Claims (24)

An input and output media access controller which is connected to an external physical layer and performs transmission and reception of Ethernet frames; Input and output GFP controllers that transmit and receive GFP (Ingress Generic Frame Procedure) / LAPS (Link Access Procedure for Synchronous Digital Hierarchy) frames by connecting to external Synchronous Optical Network (SONET) / Synchronous Digital Hierarchy (SDH) units. Wow; An input and output data queue configured to store input and output frames inputted and outputted from the input and output media access controller and the input and output GFP controller in an internal frame form; Analyze input frames from the input data queue to determine discarding or marking, and transfer the non-discarded input frames to the data memory control unit below, and transmit control information on the transferred data to the input control queue and external control memory. An input packet processor for storing;  An input control queue and an input packet queue for temporarily storing a control frame for storing an input frame from the input packet processor into an external data memory; A data memory control unit for storing an input frame from the input packet processor in an external data memory and outputting a data frame stored in the external data memory requested by an output packet processor; An output packet processor sequentially reading out control information stored in the external control memory and requesting the data memory control unit to output the frame data in the external data memory through the output control queue described below;  And a control frame for reading an output frame from the external data memory, an output control queue for temporarily storing the data frame, and an output packet queue. The method of claim 1, The input media access controller makes an RMII (Reduced Medium Independent Interface) standard connection with the Ethernet network layer, and checks the configuration / length / CRC error of the frame and converts the received Ethernet frame into an internal frame. Delivering to an input data queue, wherein the output media access controller converts an output frame from the output data queue into an Ethernet frame and outputs the converted frame. The method of claim 2, The input media access controller maps the frame check result to a Status & Length Field (SLF) field and inserts the result at the end of a received frame. The SLF field may include an alignment error field indicating whether a received frame includes extra bits instead of bytes; An FCS error field indicating whether a received frame is an FCS (Frame Check Sequence) error; A Short Event field indicating whether a length of a received frame is 64 bytes or less; A Long Event field indicating whether a length of a received frame is 1518 bytes or more; And a length field indicating the length in bytes of the received frame. The method of claim 1, The input GFP controller receives an GFP / LAPS frame according to the ITU-T G.7041 / X.86 standard, extracts an Ethernet frame, converts the received Ethernet frame into an internal frame form by connecting to an external SONET / SDH unit. To the input data queue, The output GFP controller converts a data frame from the output data queue into a GFP / LAPS frame according to the ITU-T G.7041 / X.86 standard and transmits the data frame to an external SONET / SDH unit. And the input and output GFP controllers check an abnormal state of a reception frame and a transmission frame by performing control according to the ITU-T G.7041 standard and generate an alarm to a main controller (CPU) when an error occurs. The method of claim 4, wherein The input GFP controller maps the check result of the GFP / LAPS frame to a Status & Length Field (SLF) field and inserts it into the end of the received Ethernet frame. The SLF field may include an alignment error field indicating whether a received frame includes extra bits instead of bytes; An FCS error field indicating whether a received frame is an FCS (Frame Check Sequence) error; A Short Event field indicating whether a length of a received frame is 64 bytes or less; A Long Event field indicating whether a length of a received frame is 1518 bytes or more; And a length field indicating the length in bytes of the received frame. The method according to any one of claims 1 to 5, Input and output control connected to the main control unit (CPU) to convert the control data input from the main control unit in the form of an internal frame to the input data queue, and to transmit the control report data received from the output data queue to the main control unit LAN switch further comprises a packet processor. The method of claim 3, The input packet processor accesses the input data queue using the Data Queue Interface (DQI) standard, reads internal frames stored in the input data queue sequentially in units of entries, analyzes the received frames, and determines whether to discard the received frames. An input frame is delivered to the input packet queue connected in the Buffer Queue Interface (BQI) standard, and control information on the transmitted data is stored in the external control memory connected in the Packet Control Memory Interface (PCMI) standard. And a transfer to the input control queue connected in accordance with a Free Queue Interface) standard. The method of claim 7, wherein The input packet processor classifies the non-discarded frames, which have been received, into four levels of priority according to the contents of the header, and free queue IDs of the frames are completed in the corresponding priority in the external control memory. LAN switch, characterized in that stored in the queue (Complete Queue). The method of claim 7, wherein The data memory controller analyzes control information received from the input control queue to determine whether to discard the frames stored in the input packet queue, stores valid frames in the external data memory, and receives the control received from the output control queue. Analyzing information and reading data stored in a predetermined position of the external data memory and transferring the data to the output packet queue. The method of claim 9, The output packet processor sequentially reads output frame control information stored in a complete queue stored in the external control memory, transfers the output frame control information to the output control queue connected to the FQI standard, and transmits the output received from the data memory controller. LAN data, characterized in that for reading the data stored in the packet queue, the appropriate header conversion and transfer to the output data queue connected to the DQI standard. The method of claim 10, And a packet end flag (PEF) indicating the end of the frame to the most significant bit in order to extract a start point of a frame stored in the input and output data queues. The method of claim 11, LAN switch, characterized in that the end of the frame by applying the most significant bit of the last 4 byte area of the frame stored in the input and output data queue to '1'. The method of claim 12, The SLF field is stored after the last 4-byte unit of the frame stored in the input data queue. The method of claim 13, And the input and output data queues have a FULL flag and an EMPTY flag, and the FULL flag and the EMPTY flag are set by the number of SLF fields. The method of claim 14, And the input and output data queues detect a frame using the PEF field. The method of claim 7, wherein In the BQI access standard, data stored in the buffer queue (BQ) is stored in a predetermined area of the packet buffer designated by the FQ (Free Queue). The method of claim 16, And a free queue (FQ) is allocated to every 64 byte data of the buffer queue (BQ) or to the last 64 bytes or less of the packet. The method of claim 17, The buffer queue BQ has a buffer end flag (BEF) bit that designates a boundary of the prequeue FQ, and the BEF bit is assigned to the top of the buffer queue BQ data, and the prequeue FQ. LAN switch, characterized in that '1' is applied when the last buffer queue (BQ) data of the unit is stored. The method of claim 18, The buffer queue (BQ) has a FULL flag and an EMPTY flag, and the FULL flag and the EMPTY flag are set according to the number of BEF fields. The method of claim 19, The data of the prequeue FQ includes a length field indicating the number of entries of the buffer queue BQ to which the same prequeue interface FQI is applied, and whether the buffer queue data is read and discarded by the value of the length field. And a pre-queue identifier field indicating an identification code of the pre-queue. The method of claim 20, And a data synchronization between the buffer queue (BQ) and the free queue (FQ) using the BEF field of the buffer queue (BQ) and the length field of the free queue (FQ). The method of claim 8, The input packet processor stores a pre-queue (FQ) list of processed Ethernet frame data using a Complete Queue Interface connection standard, and the completion queue (CQ) is a frame queue of a received frame. FQ) LAN switch for storing lists. The method of claim 22, Completion queue message constituting the completion queue (CQ), A pre-queue interface end flag (FQI Flag) field indicating a last structural unit of the completion queue CQ; A field indicating the number of bytes of data stored in the FQI included in the last message; A field indicating a destination port of data stored in the FQI; A field indicating a DRAM address; A field indicating a free cue identifier; A field indicating a virtual LAN identifier; And a field indicating a virtual LAN priority. The method of claim 22, The completion queue (CQ) has a FULL / EMPTY flag, each of which is represented by the number of completion queue (CQ) messages stored in the completion queue (CQ).

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