KR100766374B1 - Apparatus and Method for Generating Sense Amp Strobe Signal of Semiconductor Memory - Google Patents

Abstract

The present invention is a pulse width adjusting means for receiving a predetermined pulse signal to adjust the pulse width of the predetermined pulse signal to match the at least one first control signal, and the pulse signal output from the pulse width adjusting means at least one first And signal generating means for generating a sense amplifier strobe signal by transitioning to a timing corresponding to the two control signals.

Sense Amplifiers, Latency, Test Modes

Description

Apparatus and Method for Generating Sense Amp Strobe Signal of Semiconductor Memory}

1 is a block diagram showing a configuration related to a data bus sense amplifier of a general semiconductor memory;

2 is a circuit diagram showing the configuration of a sense amplifier strobe signal generation device of a semiconductor memory according to the prior art;

3 is a circuit diagram illustrating an internal configuration of the delay of FIG. 2;

4 is a circuit diagram showing the configuration of a sense amplifier strobe signal generation device of a semiconductor memory according to the present invention;

5 is a circuit diagram illustrating an internal configuration of a first delay unit of FIG. 4;

6 is a circuit diagram illustrating an internal configuration of a first delay time setting unit of FIG. 4;

7 is a waveform diagram of each part of the sense amplifier strobe signal generation device of the semiconductor memory according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100: pulse width adjusting unit 110: first delay unit

111: delay element array 112: delay element activation unit

120: first delay time setting unit 121: latch

200: signal generator 210: second delay unit

220: second delay time setting unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memories, and more particularly, to an apparatus and method for generating a sense amplifier strobe signal of a semiconductor memory.

In general, as shown in FIG. 1, in a read operation, a semiconductor memory detects and amplifies data of a memory cell through a bit line sense amplifier (BLSA) and loads the data on a data bus DBT / DBB. The data loaded on the DBT / DBB is sensed and amplified by the data bus sense amp (DBSA), loaded onto the global data bus (GIO), and output to the outside of the semiconductor memory through the pad through a predetermined processing procedure.

The DBSA performs data sensing and amplification according to a sense amplifier strobe signal (hereinafter referred to as DBSAEN).

The enable timing of the DBSAEN designates the operation time of the DBSA, and the pulse width designates the driving time of the DBSA. Therefore, DBSAEN is an important factor that determines the read operation characteristics of the semiconductor memory.

As shown in FIG. 2, a device for generating a sense amplifier strobe signal of a semiconductor memory according to the related art includes an inverter IV1 and an inverter IV1 that receive a read pulse generated according to a read command. Delay 10 for delaying the output, NAND gate ND1 receiving the output of the inverter IV1 and the output of the delay 10, Delay for outputting the DBSAEN by delaying the output of the NAND gate ND1 And 20.

The delays 10 and 20 have the same configuration, and as shown in FIG. 3, several nodes and output terminals of the connection nodes of the inverter array are connected through the switches 11 to 13 to have different delay times. A delay path was configured and one of the switches was turned on to set the corresponding delay time. At this time, the switches 11 to 13 are formed of a metal material.

The conventional technique configured as described above generates the DBSAEN by delaying the input RDP through the delays 10 and 20 and generates the DBSAEN by the delay time set for each of the delays 10 and 20. Able timing is adjusted.

However, the conventional device for generating a sense amplifier strobe signal of a semiconductor memory has the following problems.

First, when it is necessary to adjust the pulse width and enable timing of the DBSAEN, it is necessary to perform a revision operation on the metal switch, which is time-consuming and expensive.

Second, the delay adjustment range is so limited that only coarse adjustments are possible, but fine DBSAEN pulse widths and enable timing adjustments are not possible.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide an apparatus and method for generating a sense amplifier strobe signal of a semiconductor memory, which enables the timing of a sense amplifier strobe signal to be easily adjusted.

Another object of the present invention is to provide an apparatus and method for generating a sense amplifier strobe signal of a semiconductor memory, which enables fine adjustment of sense amplifier strobe signal timing.

According to another aspect of the present invention, there is provided a sense amplifier strobe signal generation device including: pulse width adjusting means for receiving a predetermined pulse signal and adjusting a pulse width of the predetermined pulse signal to match at least one first control signal; And signal generation means for generating a sense amplifier strobe signal by transitioning the pulse signal output from the pulse width adjusting means to a timing corresponding to at least one second control signal.

According to another aspect of the present invention, there is provided an apparatus for generating a sense amplifier strobe signal, comprising: pulse width adjusting means for receiving a predetermined pulse signal and adjusting a pulse width of the predetermined pulse signal to match a first delay time setting signal; And signal generating means for generating a sense amplifier strobe signal by transitioning the pulse signal output from the pulse width adjusting means to a timing corresponding to the second delay time setting signal.

In the method of generating a sense amplifier strobe signal of a semiconductor memory according to the present invention, the method of generating a sense amplifier strobe signal of a semiconductor memory having first and second delay units may include delay elements of the first delay unit according to at least one first control signal. Selectively activating and delaying the predetermined pulse signal by a corresponding time; Adjusting the pulse width of the sense amplifier strobe signal by using the predetermined pulse signal and the delayed predetermined pulse signal; And selectively activating a delay element of the second delay unit according to at least one second control signal and delaying an enable timing of the sense amplifier strobe signal whose pulse width is adjusted by a corresponding time. It is done.

According to the present invention, a method of generating a sense amplifier strobe signal of a semiconductor memory includes a first delay unit and a second delay unit including a plurality of delay elements, and a delay of each of the first delay unit and the second delay unit according to a fuse connection state. A method for generating a sense amplifier strobe signal of a semiconductor memory having a first delay time setting unit and a second delay time setting unit for outputting a first delay time setting signal and a second delay time setting signal for selectively activating an element, Selectively activating the delay elements of the first delay element array to correspond to a first test mode signal and delaying a predetermined pulse signal by a corresponding time; Adjusting the pulse width of the sense amplifier strobe signal by using the predetermined pulse signal and the delayed predetermined pulse signal; Selectively activating the delay elements of the second delay element array to correspond to a second test mode signal and delaying the enable timing of the sense amplifier strobe signal whose pulse width is adjusted by a corresponding time; And storing a value equal to one of a combination of each of the first test mode signal and the second test mode signal in the first delay time setting unit and the second delay time setting unit.

Hereinafter, an embodiment of an apparatus and method for generating a sense amplifier strobe signal of a semiconductor memory according to the present invention will be described with reference to the accompanying drawings.

4 is a circuit diagram illustrating a configuration of a sense amplifier strobe signal generation device of a semiconductor memory according to the present invention, FIG. 5 is a circuit diagram illustrating an internal configuration of a first delay unit of FIG. 4, and FIG. 6 is a first delay time setting unit of FIG. 4. Fig. 7 is a waveform diagram of each part of the sense amplifier strobe signal generation device of the semiconductor memory according to the present invention.

According to an embodiment of the apparatus for generating a sense amplifier strobe signal of a semiconductor memory according to the present invention, as shown in FIG. 4, a predetermined pulse signal, that is, a read pulse generated according to a read command (hereinafter referred to as RDP) is received at least. A pulse width adjusting unit 100 for adjusting a pulse width of the predetermined pulse signal to match one first control signal, and timing corresponding to at least one second control signal with a pulse signal output from the pulse width adjusting unit 100; And a signal generator 200 for generating a sense amplifier strobe signal (hereinafter referred to as DBSAEN).

The first control signal includes at least one of a first test mode signal (hereinafter, TM1 <0: 3>) and a first delay time setting signal (hereinafter, F1 <0: 3>).

The second control signal includes at least one of a second test mode signal (hereinafter referred to as TM2 <0: 3>) and a second delay time setting signal (hereinafter referred to as F2 <0: 3>).

The pulse width adjusting unit 100 is configured to adjust the pulse width of the DBSAEN by outputting high when any one of the RDP and the RDP delayed by a predetermined time is high. That is, the inverter IV11 receiving the RDP and the output of the inverter IV11 by the delay time according to the delay element activated according to the TM1 <0: 3> or the F1 <0: 3> among a plurality of delay elements. A first delay unit 110 for delaying, a first delay time setting unit 120 for outputting the F1 <0: 3> according to the internal fuses FUSE0 to FUSE3, and an output of the inverter IV11; And a NAND gate ND11 that receives the output of the first delay unit 110.

The signal generator 200 may include a NAND gate ND11 of the pulse width adjusting unit 100 by a delay time according to a delay element activated according to the TM2 <0: 3> or F2 <0: 3> among a plurality of delay elements. The second delay unit 210 for delaying the output of the PSAEN and generating the DBSAEN, and the second delay time setting unit 220 for outputting the F2 <0: 3> according to an internal fuse (hereinafter, FUSE0 to FUSE3). ).

The first delay unit 110 and the second delay unit 210 are different only from the input control signal, the internal configuration is the same. Accordingly, when the internal configuration of the first delay unit 110 is described, as illustrated in FIG. 5, the first inverter IV20 connected to the input terminal, the second inverter IV21 connected to the output terminal, and the first inverter IV20 are connected to each other. Delay element array 111 comprising a plurality of capacitors (C11, C12, C21, C22, C31, C32, C41, C42) connected to the signal line connecting the output and the input of the second inverter (IV21), TM1 < Delay element activation unit for selectively activating a plurality of capacitors (C11, C12, C21, C22, C31, C32, C41, C42) of the delay element array 111 according to 0: 3> or F1 <0: 3> (112).

The delay element array 111 may include first capacitor groups C11, C21, C31, and C41 connected in parallel to both sides of a signal line connecting an output of the first inverter IV20 and an input of the second inverter IV21. Two capacitor groups C12, C22, C32, C42. The first capacitor groups C11, C21, C31, and C41 form a capacitor by connecting the source and the drain of the PMOS transistor, and the second capacitor group C12, C22, C32, and C42 form the source and drain of the NMOS transistor. To connect the capacitor.

The first capacitor group C11, C21, C31, and C41 and the second capacitor group C12, C22, C32, and C42 are paired with capacitors facing each other in series. That is, C11 and C12, C21 and C22, C31 and C32, C41 and C42 each form a pair, and the capacitor pairs are equally activated or deactivated. At this time, the capacitor pairs C41 and C42 are formed to have the largest charging capacity compared to the other capacitors.

The delay element activating unit 112 is the same order signal pairs TM1 <0: 3> and F1 <0: 3> (TM1 <0> and F1 <0>, TM1 <1> and F1 <1>, respectively). When any one of TM1 <2> and F1 <2>) is enabled, the corresponding capacitor pair is activated simultaneously, and the corresponding capacitor when both TM1 <3> and F1 <3> are disabled. It is configured to activate the pair simultaneously and if one of the TM1 <3> and F1 <3> is enabled, it is configured to simultaneously deactivate the corresponding capacitor pair.

That is, the first NOR gate NR21 that receives TM1 <0> and F1 <0>, the third inverter IV22 that receives the output of the first NOR gate NR21, and the third inverter IV22 Fourth inverter IV23 that receives an output, a second NOR gate NR22 that receives TM1 <1> and F1 <1>, and a fifth inverter IV24 that receives an output of the second Noah gate NR22. A sixth inverter IV25 that receives the output of the fifth inverter IV24, a third NOR gate NR23 that receives TM1 <2> and F1 <2>, and an output of the third NOR gate NR23 A seventh inverter IV26 receiving the input, an eighth inverter IV27 receiving the output of the seventh inverter IV26, a fourth NOR gate NR24 receiving the TM1 <3> and F1 <3>, and The ninth inverter IV28 receives the output of the fourth NOR gate NR24 and the tenth inverter IV29 receives the output of the ninth inverter IV28. In addition, the outputs of the third inverter IV22 and the fourth inverter IV23 are connected to the gates of the capacitor pairs C12 and C11. The outputs of the fifth inverter IV24 and the sixth inverter IV25 are connected to the gates of the capacitor pairs C22 and C21. Outputs of the seventh inverter IV26 and the eighth inverter IV27 are connected to gates of the capacitor pairs C32 and C31. The outputs of the ninth inverter IV28 and the tenth inverter IV29 are connected to gates of the capacitor pairs C41 and C42.

As illustrated in FIG. 6, the first delay time setting unit 120 includes circuits for generating F1 <0> to F1 <3>, respectively, and the circuits are the same. Therefore, when describing a configuration of a circuit generating one of F1 <0>, one end of FUSE0 connected to the power supply terminal VDD, the drain is connected to the other end of the FUSE0, the source is grounded, and the reset signal RST is applied to the gate. A first transistor (M31) receiving the input includes a latch 121 for outputting the F1 <0> of the connection node level of the FUSE0 and the first transistor (M31). The latch 121 is an inverter IV31 connected to the connection node of the FUSE0 and the first transistor M31, a drain is connected to an input terminal of the inverter IV31, a source is grounded, and a gate of the inverter IV31 is connected. The second transistor M32 receives an output. If the FUSE0 is not cut, the high signal according to the power supply VDD level is inverted through the latch 121 so that F1 <0> remains low. On the other hand, if the FUSE0 is cut, the first transistor M31 is turned on by the reset (RST) pulse input during the initial operation of the semiconductor memory. Thus, the low signal according to the ground level VSS is inverted through the latch 121. F1 <0> remains high. In this way, the levels of F1 <1>, F1 <2> and F1 <3> are also determined according to the cutting states of FUSE1, FUSE2 and FUSE3.

In this case, the capacitors of the delay element array 111 may be selectively operated by F1 <0: 3> generated according to 16 combinations, in which none of FUSE0 to FUSE3 is cut and all are cut. The number of fuses can be changed to increase or decrease the number of possible delays. That is, when none of FUSE0 to FUSE3 is cut, two capacitors C41 and C42 are activated and the rest are deactivated. Delay time when only C41 and C42 are activated may be set as default, and the delay time may be increased by a predetermined time unit (for example, pico second) by selectively activating another capacitor. In addition, the delay time can be reduced by the predetermined time unit by deactivating C41 and C42 and selectively activating another capacitor.

The second delay time setting unit 220 differs only in a control signal input from the first delay time setting unit 120, and its internal configuration is the same.

Meanwhile, in the above-described configuration of the exemplary embodiment of the present invention, the delay element array 111 of FIG. 5 has described an example using a method of simultaneously activating a capacitor pair consisting of an NMOS transistor and a PMOS transistor. However, this is to reduce the layout size increase by using only one of the N and P regions of the semiconductor. However, the same operation can be performed by implementing the delay element array 111 using only one of the N region and the P region. That is, it is also possible to use only one of the first capacitor group (C11, C21, C31, C41) or the second capacitor group (C12, C22, C32, C42). In this case, the configuration of the delay time activator 112 is changed. For example, if only the second capacitor groups C12, C22, C32, and C42 of the delay element array 111 are used, the fourth, sixth, and eighth related to the first capacitor groups C11, C21, C31, and C41 are used. W and 10 inverters (IV23, IV25, IV27, and IV29) and their respective output lines may be constructed without circuits.

In addition, the embodiment of the present invention describes an example in which the test mode signals TM1 <0: 3> and TM2 <0: 3> are applied. However, the TM1 <0: 3> and the TM2 <0: 3> are examples that allow the F1 <0: 3> and the F2 <0: 3> to be set more accurately and easily through testing. However, without using the test mode signal and using only F1 <0: 3> and F2 <0: 3>, it is possible to adjust the pulse width and enable timing of the DBSAEN to a desired level. In this case, the delay element activator 112 of FIG. 5 may be configured with an inverter corresponding to the number of bits of each of F1 <0: 3> and F2 <0: 3>. This is because in order to simultaneously activate or deactivate the capacitor pair of the delay element array 111, the signals of the levels F1 <0: 3> and F2 <0: 3> and vice versa are required.

Referring to the operation of the embodiment of the present invention configured as described above are as follows.

4 and 7, the RDP generated according to the read command is inverted like A through the inverter IV11 of the pulse width adjusting unit 100, and the output of the inverter IV11 is first delayed. The unit 110 delays the time corresponding to TM1 <0: 3> or F1 <0: 3> and outputs the same as B. FIG. A and B are input to the NAND gate ND11 to output a waveform C whose pulse width is adjusted.

When the output C of the pulse width adjusting unit 100 is delayed by a time corresponding to TM2 <0: 3> and F2 <0: 3> through the second delay unit 210 of the signal generator 200, DBSAEN is delayed. Is enabled.

The pulse width of the DBSAEN is determined by the delay time of the first delay unit 110 and the enable timing of the DBSAEN is determined by the delay time of the second delay unit 210. The operation of the second delay unit 210 is the same.

The first delay unit 110 may increase or decrease the delay time by the F1 <0: 3>. Therefore, F1 <0: 3> by cutting FUSE0 to FUSE3 of the first delay time setting unit 120 may be input to the first delay unit 110 so as to meet a desired delay time.

The second delay unit 210 may also increase or decrease the delay time by F2 <0: 3>. Therefore, F2 <0: 3> by cutting FUSE0 to FUSE3 of the second delay time setting unit 220 may be input to the second delay unit 210 to meet a desired delay time.

The TM1 <0: 3> and TM2 <0: 3> are added to proceed the test mode to find the optimal delay time before the determination of F1 <0: 3> and F2 <0: 3>. That is, TM1 <0: 3> may selectively activate the capacitors of the first delay unit 110 in the same manner as F1 <0: 3>, and TM2 <0: 3> may be equal to F2 <0: 3>. Likewise, the capacitors of the second delay unit 210 may be selectively activated.

Therefore, after setting the operation state of the semiconductor memory to the test mode, the TM1 <0: 3> and TM2 <0: 3> are changed independently, and according to the DBSAEN to test the normal operation of the data output, the optimal DBSAEN Find the pulse width and enable timing of

This test process determines the optimal pulse width and enable timing of the DBSAEN, so that F1 <0: 3> and F2 <0: 3> equal to the corresponding TM1 <0: 3> and TM2 <0: 3> values. The FUSE0 to FUSE3 of the first delay time setting unit 120 and the second delay time setting unit 220 may be cut so as to output the same.

As described above, the 16 delay time combinations allow the pulse width and enable timing of the sense amplifier strobe signal to be broader and more detailed than in the prior art.

Although the above-described embodiment of the present invention describes an embodiment of the sense amplifier strobe signal generator using the number of delay time cases according to 16 combinations, the delay time combination case is increased by increasing the number of capacitors and changing the circuit configuration associated therewith. It is also possible to provide a sense amplifier strobe signal generator that allows for a wider and more detailed pulse width and enable timing adjustment by increasing the number of.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The apparatus and method for generating a sense amplifier strobe signal of a semiconductor memory according to the present invention have the following effects.

First, simple fuse cutting without revisions can adjust the pulse width and enable timing of the sense amplifier strobe signal, saving time and money.

Second, the pulse width and enable timing of the sense amplifier strobe signal can be adjusted very finely, thereby improving the performance and reliability of the semiconductor memory.

Claims (53)

Pulse width adjusting means for receiving a read pulse signal generated according to a read command and adjusting a pulse width of the read pulse signal to match at least one first control signal; And And a signal generating means for generating a sense amplifier strobe signal by transitioning the read pulse signal output from the pulse width adjusting means to a timing corresponding to at least one second control signal. delete The method of claim 1, And the first control signal comprises at least one of a first test mode signal and a first delay time setting signal. The method of claim 1, The pulse width adjusting means And outputting a signal at which the same level as the signal level of the enable period is maintained during the enable period of the read pulse signal delayed by a predetermined time according to the enable period of the read pulse signal and the first control signal. Sense amplifier strobe signal generator of a semiconductor memory. The method of claim 1, The pulse width adjusting means An inverter receiving the read pulse, A delay unit configured to delay an output of the inverter by a delay time according to a delay element activated according to the at least one first control signal among a plurality of delay elements; A first delay time setting unit configured to output one of the at least one first control signal according to a connection state of an internal fuse; and And a NAND gate configured to receive an output of the inverter and an output of the first delay unit. The method of claim 5, The delay unit A delay element array including a plurality of delay elements connected to an input / output signal line, and And a delay element activator for selectively activating the plurality of delay elements in accordance with the at least one first control signal. The method of claim 6, The plurality of delay elements And at least one capacitor group connected to one side or both sides of the signal line in parallel. The method of claim 7, wherein The at least one capacitor group is And a first capacitor group including a plurality of capacitors formed by connecting a source and a drain of a PMOS transistor, and a second capacitor group including a plurality of capacitors formed by connecting a source and a drain of an NMOS transistor. Amplifier strobe signal generator. The method of claim 8, And the first capacitor group and the second capacitor group are coupled to each other in series to form a pair, and are activated or deactivated in the same manner. The method of claim 9, And at least one pair of the capacitor pairs has a larger charging capacity than the other capacitor pairs. The method of claim 6, The delay element activation unit And enabling or inactivating a delay element corresponding to any one of the at least one pair of the same sequence signals of the at least one first control signal. The method of claim 6, The delay element activation unit And a plurality of logic circuits provided for each of the same ordered signal pairs of the at least one first control signal, wherein the logic circuit is configured to receive an output of the NOR gate and the output of the Noa gate. And an inverter, and a second inverter receiving an output of the first inverter. The method of claim 6, The delay element activation unit And a plurality of logic circuits provided for each of the same ordered signal pairs of the at least one first control signal, wherein the logic circuit receives a Noa gate receiving the same ordered signal pair and an output of the Noah gate. Sense amplifier strobe signal generation device of a semiconductor memory, characterized in that it comprises an inverter. The method of claim 5, The first delay time setting unit And a plurality of logic circuits provided as many as one bit among the first control signals, wherein the logic circuit includes a fuse connected to a power supply terminal at one end thereof, a drain connected to the other end of the fuse, a source is grounded, and a gate And a latch configured to receive a reset signal, and a latch configured to receive a connection node level of the fuse and the first transistor. 2. The method of claim 14, The latch is An inverter connected to the fuse and a connection node of the first transistor, and a second transistor having a drain connected to an input terminal of the inverter, a source of which is grounded, and receiving an output of the inverter from a gate of the semiconductor memory. Sense amplifier strobe signal generator. The method of claim 1, And the second control signal comprises at least one of a second test mode signal and a second delay time setting signal. The method of claim 1, The signal generating means A delay unit for generating the sense amplifier strobe signal by delaying the output of the pulse width adjusting means by a delay time according to the delay element activated according to the at least one second control signal among a plurality of delay elements; And a second delay time setting unit configured to output one of the at least one second control signal according to a connection state of an internal fuse. The method of claim 17, The delay unit A delay element array including a plurality of delay elements connected to an input / output signal line, and And a delay element activator for selectively activating the plurality of delay elements in accordance with the at least one second control signal. The method of claim 18, The plurality of delay elements And at least one capacitor group connected to one side or both sides of the signal line in parallel. The method of claim 19, The at least one capacitor group is A first capacitor group including a plurality of capacitors formed by connecting a source and a drain of a PMOS transistor, and a second capacitor group including a plurality of capacitors formed by connecting a source and a drain of an NMOS transistor. Sense amplifier strobe signal generator. The method of claim 20, And the first capacitor group and the second capacitor group are coupled to each other in series to form a pair, and are activated or deactivated in the same manner. The method of claim 21, And at least one pair of the capacitor pairs has a larger charging capacity than the other capacitor pairs. The method of claim 18, The delay element activation unit And at least one of the same sequence signal pair of the at least one control signal is configured to activate or deactivate a delay element corresponding to the at least one control signal. The method of claim 18, The delay element activation unit And a plurality of logic circuits provided for each of the same ordered signal pairs of the at least one first control signal, wherein the logic circuit is configured to receive an output of the NOR gate and the output of the Noa gate. And an inverter, and a second inverter receiving an output of the first inverter. The method of claim 18, The delay element activation unit And a plurality of logic circuits provided for each of the same ordered signal pairs of the at least one first control signal, wherein the logic circuit receives a Noa gate receiving the same ordered signal pair and an output of the Noah gate. Sense amplifier strobe signal generation device of a semiconductor memory, characterized in that it comprises an inverter. The method of claim 17, The second delay time setting unit And a plurality of logic circuits provided as many as one bit among the second control signals, wherein the logic circuit includes a fuse connected at one end to a power supply terminal, a drain connected to the other end of the fuse, a source is grounded, and a gate And a latch configured to receive a reset signal, and a latch configured to receive a connection node level of the fuse and the first transistor. 2. Pulse width adjusting means for receiving a read pulse signal generated according to a read command and adjusting a pulse width of the read pulse signal to match a first delay time setting signal; And And a signal generating means for generating a sense amplifier strobe signal by transitioning the pulse signal output from the pulse width adjusting means to a timing corresponding to a second delay time setting signal. delete The method of claim 27, The pulse width adjusting means And output a signal at which the same level as the signal level of the enable period is maintained during the enable period of the read pulse signal delayed by a predetermined time according to the enable period of the read pulse signal and the first delay time setting signal. A sense amplifier strobe signal generation device of a semiconductor memory. The method of claim 27, The pulse width adjusting means An inverter receiving the read pulse, A delay unit configured to delay an output of the inverter by a delay time according to a delay element activated according to the first delay time setting signal among a plurality of delay elements; A first delay time setting unit outputting the first delay time setting signal according to a connection state of an internal fuse; and And a NAND gate receiving the output of the inverter and the output of the delay unit. The method of claim 30, The delay unit A delay element array including a plurality of delay elements connected to an input / output signal line, and And a delay element activator for selectively activating the plurality of delay elements in accordance with the first delay time setting signal. The method of claim 31, wherein The plurality of delay elements And at least one capacitor group connected to one side or both sides of the signal line in parallel. The method of claim 32, The at least one capacitor group is A first capacitor group including a plurality of capacitors formed by connecting a source and a drain of a PMOS transistor, and a second capacitor group including a plurality of capacitors formed by connecting a source and a drain of an NMOS transistor. Sense amplifier strobe signal generator. The method of claim 33, wherein And the first capacitor group and the second capacitor group are coupled to each other in series to form a pair, and are activated or deactivated in the same manner. The method of claim 34, wherein And at least one pair of the capacitor pairs has a larger charging capacity than the other capacitor pairs. The method of claim 31, wherein The delay element activation unit And an inverter provided with the number of bits of the first delay time setting signal. The method of claim 30, The first delay time setting unit And a plurality of logic circuits provided as many as the number of bits of the first delay time setting signal. The logic circuit is a fuse connected to one end of the power supply, A first transistor having a drain connected to the other end of the fuse, a source grounded, and receiving a reset signal at a gate thereof; and And a latch configured to receive a level of a connection node of the fuse and the first transistor. The method of claim 27, The signal generating means A delay unit for generating the sense amplifier strobe signal by delaying the output of the pulse width adjusting means by a delay time according to the delay element activated according to the second delay time setting signal among a plurality of delay elements; And a second delay time setting unit outputting the second delay time setting signal according to a connection state of an internal fuse. The method of claim 38, The delay unit A delay element array including a plurality of delay elements connected to an input / output signal line, and And a delay element activator for selectively activating the plurality of delay elements in accordance with the second delay time setting signal. The method of claim 39, The plurality of delay elements A first capacitor group including a plurality of capacitors formed by connecting a source and a drain of a PMOS transistor, and a second capacitor group including a plurality of capacitors formed by connecting a source and a drain of an NMOS transistor; 2. A sense amplifier strobe signal generator of a semiconductor memory, wherein capacitors facing each other in a group of two capacitors are connected in series to be equally activated or deactivated. The method of claim 39, The delay element activation unit And an inverter provided with the number of bits of the second delay time setting signal. The method of claim 38, The second delay time setting unit It includes a plurality of logic circuits provided by the number of bits (Bit) of the second delay time setting signal, The logic circuit is a fuse connected to one end of the power supply, A first transistor having a drain connected to the other end of the fuse, a source grounded, and receiving a reset signal at a gate thereof; and And a latch configured to receive a level of a connection node of the fuse and the first transistor. A method of generating a sense amplifier strobe signal of a semiconductor memory having first and second delay units, Selectively activating a delay element of the first delay unit according to at least one first control signal and delaying a read pulse signal generated according to a read command by a corresponding time; Adjusting a pulse width of the sense amplifier strobe signal using the read pulse signal and the delayed read pulse signal; And Selectively activating a delay element of the second delay unit according to at least one second control signal and delaying an enable timing of the sense amplifier strobe signal whose pulse width is adjusted by a corresponding time. Sense amplifier strobe signal generation method. delete The method of claim 43, The at least one first control signal may include at least one of a first delay time setting signal generated according to a first test mode signal and a fuse connection state. The method of claim 43, Delaying the read pulse signal according to at least one first control signal And delaying the read pulse signal when any one of the at least one first control signal is enabled. The method of claim 43, Adjusting the pulse width of the sense amplifier strobe signal using the read pulse signal and the delayed read pulse signal And maintaining the same level as the signal level of the enable period during the enable period of the read pulse signal and the enable period of the delayed read pulse signal. The method of claim 43, And wherein the second control signal comprises at least one of a second delay time setting signal generated according to a second test mode signal and a fuse connection state. The method of claim 43, Delaying the sense amplifier strobe signal in accordance with at least one second control signal And delaying the sense amplifier strobe signal having the pulse width adjusted when at least one of the at least one second control signal is enabled. A first delay unit and a second delay unit each including a plurality of delay elements, a first delay time setting signal for selectively activating the delay elements of each of the first delay unit and the second delay unit according to a fuse connection state; A method for generating a sense amplifier strobe signal of a semiconductor memory having a first delay time setting unit and a second delay time setting unit for outputting a second delay time setting signal, Selectively activating a delay element of the first delay element array to correspond to a first test mode signal and delaying a predetermined pulse signal by a corresponding time; Adjusting the pulse width of the sense amplifier strobe signal by using the predetermined pulse signal and the delayed predetermined pulse signal; Selectively activating the delay elements of the second delay element array to correspond to a second test mode signal and delaying the enable timing of the sense amplifier strobe signal whose pulse width is adjusted by a corresponding time; And Generating a sense amplifier strobe signal of the semiconductor memory including storing a value equal to one of a combination of each of the first test mode signal and the second test mode signal to the first delay time setting unit and the second delay time setting unit; Way. 51. The method of claim 50, And said predetermined pulse signal is a read pulse input according to a read command. 51. The method of claim 50, Adjusting the pulse width of the sense amplifier strobe signal by using the predetermined pulse signal and the delayed predetermined pulse signal And maintaining and outputting the same level as the signal level of the enable period during the enable period of the predetermined pulse signal and the enable period of the delayed predetermined pulse signal. 51. The method of claim 50, The step of storing the same value as one of the combination of each of the first test mode signal and the second test mode signal in the first delay time setting unit and the second delay time setting unit Cutting the fuse of the first delay time setting unit and the second delay time setting unit corresponding to one of the combinations of the first test mode signal and the second test mode signal, and latching the output level accordingly; A method of generating a sense amplifier strobe signal of a semiconductor memory.

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