KR100743625B1 - Internal voltage generator - Google Patents

Abstract

The charge pumping part of the present invention, that is, the internal voltage generator is configured to block a connection path between the ground voltage and the internal voltage in order to prevent the internal voltage from being changed due to the variation of the surrounding ground voltage (driving voltage) after the internal voltage is stabilized. It generates the element and its blocking signal to block the fluctuation of the internal voltage.

Description

Internal voltage generator

1 is a block diagram schematically illustrating an operation of a general internal voltage generator.

The operation of the charge pumping unit of FIG. 2 is as follows.

3 is a block diagram illustrating the concept of an internal voltage generator according to the present invention.

FIG. 4 is an embodiment of the pumping controller 305 shown in FIG. 3.

FIG. 5 is a waveform diagram illustrating pulse waveforms of signals a1 and b1 generated from the circuit shown in FIG. 4.

FIG. 6 is a waveform diagram illustrating a pulse waveform of signals a2 and b2 generated from the circuit shown in FIG. 4.

FIG. 7 is an embodiment of the charge pumping unit 306 processed in the block diagram in FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to an internal voltage generator for generating an internal voltage of a semiconductor device.

In general, most semiconductor devices include an internal voltage generator for generating a voltage necessary for the operation of an internal circuit of the semiconductor device in addition to a power supply voltage supplied from the outside to drive the semiconductor device.

These internal voltage generators generally generate higher or lower voltages than externally supplied power supply voltages, and these internal voltages are generally generated using a well-known charge pumping ice type.

1 is a block diagram schematically illustrating an operation of a general internal voltage generator.

As shown, the internal voltage generator includes an internal voltage level detector for comparing the internal voltage VBB with a predetermined reference voltage Vr1, and a ring oscillator operating when the output signal ppe of the internal voltage level detector is enabled. A pumping control unit for outputting a control signal for controlling the operation of the charge pumping unit in response to the output signal of the ring oscillator and the ring oscillator, and a pumping operation according to the control signal of the pumping control unit to perform an internal voltage (VBB) of a predetermined level. It is provided with a charge pumping unit for generating a. Here, the internal voltage VBB means an internal voltage lower than the ground voltage. However, the internal voltage generator of this structure is equally applied to the high voltage generator higher than the power supply voltage.

Since the basic operation of the internal voltage generator shown in FIG. 1 is well known to those skilled in the art, a detailed description thereof will be omitted.

The present invention pays particular attention to the function of the charge pumping unit among the components of the internal voltage generator shown in FIG. 1, and an example of a charge pumping unit conventionally used will be described below.

2 is an example of a conventional charge pumping unit. For reference, in general, the charge pumping unit generates a final internal voltage and thus should be regarded as belonging to the internal voltage generator in a broad sense. Thus, the charge pumping portion described herein is in fact also an example of an internal voltage generator. For reference, the signals p1, p2, g1, and g2 of FIG. 2 represent control signals output from the pumping controller of FIG. 1.

The operation of the charge pumping unit of FIG. 2 is as follows.

At the moment when the signal p1 transitions from the supply voltage VCC to ground VSS, the node p1boot bootstraps and transitions from VSS to -VCC, at which point the signal p2 transitions from VSS to VCC. Node (p2boot) is bootstrapped and transitions from -VCC to VSS. In this case, the charge of the node p1boot at the -VCC level is applied to the node out which outputs the internal voltage VBB through the transistor N1. During this period of time, the node p1boot and the output node out are in equilibrium by charge distribution. After that, when the signal g2 transitions from VCC to VSS and the node g2boot bootstrap and becomes -VCC at VSS, the transistor P2 is turned on to pre-charge the node p2boot to VSS. When the signal g2 transitions from VSS to VCC and the node g2boot becomes -VCC and the transistor P2 is turned off and the pre-charging is completed, the signal p1 transitions from VSS to VCC. p1boot becomes VCC and signal p2 transitions from VCC to VSS to make node p2boot a -VCC. This time, charge distribution operation between node p2boot and output node through transistor P2 Is done.

After some time again, when the node p2boot and the output node reach the equilibrium state by the charge distribution operation, the signal g1 transitions from VCC to VSS and the node g1boot boots. When strapped to -VCC at VSS, transistor P1 is turned on to pre-charge node p1boot to VSS, and signal g1 transitions from VSS to VCC again, node g1boot becomes VSS and transistor P1. ) Is turned off to complete the pre-charge to prepare for the next operation.

By the way, in the conventional case, while the internal voltage VBB reaches the target value and the predetermined time is maintained, the node g1boot maintains -Vt, the node g2boot maintains Vt, and the node p2boot maintains VBB. When the VSS voltage increases instantaneously, the transistor P2 is turned on while the internal voltage VBB of the output node out deviates from the target value.

That is, there is a problem that leakage current may be generated due to the turn-on of the transistor P2.

The present invention has been proposed in order to solve the above-mentioned conventional problems, and the charge pumping unit that can block the fluctuation of the internal voltage due to the fluctuation of the ambient voltage while the internal voltage reaches a target value and maintains a stable state, that is, To provide an internal voltage generator.

In the internal voltage generator according to the present invention, the internal voltage generator generates an internal voltage VBB having a different level from the first voltage from the first voltage VSS by a pumping operation. The first transistor 701 connected between the node p1boot, the second transistor 702 connected between the first node out and the third node p2boot, the second node p1boot and the first node A third transistor 703 connected between a first voltage, a fourth transistor 704 connected between the third node p2boot and the first voltage, a first control signal p1 and the second node p1boot A first capacitor 713 connected between the second capacitor 713, a second capacitor 714 connected between the second control signal p2 and the third node p2boot, a third control signal g1 and the third transistor. Of the third capacitor 705, the fourth control signal g2, and the fourth transistor 704 connected between the gates of 703; A fourth capacitor 706 connected between the gate, a fifth transistor 709 connected between the gate of the third transistor 703 and the first voltage, a gate of the fourth transistor 704 and the first transistor; A sixth transistor 712 connected between the voltage, a first switching unit 707 connected between the gate of the third transistor 703 and the second voltage VCC, and a gate of the fourth transistor 704. An internal voltage generator unit having a second switching unit 710 connected between the second voltage VCC is provided.

In the present embodiment, the first voltage is ground, the second voltage is a power supply voltage, and the internal voltage is lower than the ground voltage.

In this embodiment, the internal voltage is reached to a predetermined target value by using logic level signals applied to the first to fourth control signals.

In the present exemplary embodiment, when the first voltage rises after the internal voltage reaches a target value, the first and second switching units are turned on to turn on the third and fourth transistors. The fifth and sixth transistors are turned on to initialize the gate voltages of the third transistor and the gate voltages of the fourth transistors to the first voltage.

(Example)

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

3 is a block diagram illustrating the concept of an internal voltage generator according to the present invention.

As illustrated, the internal voltage generator includes a reference voltage generator 301, a level shifter 302 for displacing the level of a reference voltage Vref of a predetermined level, which is an output signal of the reference voltage generator 301, and a level shifter ( A pulse of a predetermined period in response to the internal voltage detector 303 for comparing the reference voltage Vr1 of the predetermined level, which is the output voltage of the 302, and the internal voltage VBB, and the output signal ppe of the internal voltage detector 303; A plurality of control signals are generated in response to a ring oscillator 304 generating a signal osc, an output signal osc of the ring oscillator 304, and an output signal ppe of the internal voltage detector 303. And a charge pumping unit 306 for outputting the internal voltage VBB in response to the output signals a1, b1, a2, and b2 of the pumping control unit 305.

Various embodiments of the reference voltage generator 301, the level shifter 302, the internal voltage detector 303, and the ring oscillator 304 are well known to those skilled in the art and these are not themselves covered in the gist of the present invention. In the following, specific embodiments of the pumping controller 305 and the charge pumping unit 306 will be described.

FIG. 4 is an embodiment of the pumping controller 305 shown in FIG. 3.

As shown, inverter 401 receives signal g1 and outputs signal c4. The odd number of inverter chains 402 receives a signal ppe and outputs a signal c3. Inverter 403 receives signal g2. The odd number of inverter chains 404 receives the signal ppe and outputs a signal c1. The NAND gate 405 receives the signal c4 and the signal ppe and the signal c3. The NAND gate 406 receives the output signal and the signal ppe and the signal c3 of the inverter 403. The NOR gate 407 outputs a signal ppe and a signal c1. The inverter 408 inverts the output signal of the NAND gate 405 and outputs a signal a2. The inverter 409 inverts the output signal of the NAND gate 406 and outputs a signal b2. The inverter 410 inverts the output signal of the NOR gate 407 and outputs a signal c2. Noah gate 411 receives signals g1 and c2. The inverter 412 receives the output signal of the NOR gate 411 and outputs a signal a1. Noah gate 413 receives signals g2 and c2. The inverter 414 receives the output signal of the NOR gate 413 and outputs a signal b1.

FIG. 5 is a waveform diagram illustrating the pulse waveforms of the signals a1 and b1 generated from the circuit shown in FIG. 4, and FIG. 6 shows the pulse waveforms of the signals a2 and b2 generated from the circuit shown in FIG. 4. It is a waveform diagram explaining.

FIG. 7 is an embodiment of the charge pumping unit 306 processed in the block diagram in FIG. 3.

As shown, the charge pumping unit includes an NMOS transistor 701 connected between an output node out of the internal voltage VBB and a node p1boot, a PMOS transistor 703 connected between a node p1boot and ground, NMOS transistor 702 connected between output node out and node p2boot, PMOS transistor 704 connected between node p2boot and ground, node g1boot, which is the gate of PMOS transistor 703, and ground A capacitor 709 connected therebetween, an NMOS transistor 708 connected between a node g1boot and ground, a switching unit 707 connected between a node g1boot and a power supply voltage VCC, and a node g1; A capacitor 705 connected between the node g1boot, a capacitor 712 connected between the node g2boot, which is the gate of the PMOS transistor 704, and ground, and an NMOS transistor 711 connected between the node g2boot and the ground. And a switching unit 710 connected between the node g2boot and the power supply voltage VCC, the node g2 and the node g2boot. A capacitor 706 connected therebetween, a capacitor 713 connected between the node p1boot and the node p1, and a capacitor 714 connected between the node p2boot and the node p2. Here, the nodes p1, p2, g1, and g2 are nodes to which the signals p1, p2, g1, and g2 generated by the pumping control unit 305 are applied as described with reference to FIG. 1. In some cases, it is indicated by a signal.

In FIG. 7, the switching unit 707 is controlled by the signal a1, the switching unit 710 is controlled by the signal b1, and the signal a2 is applied to the gate of the NMOS transistor 708. The signal b2 is applied to the gate of the NMOS transistor 711. In addition, the node p1boot is connected to the gate of the NMOS transistor 702, and the node p2boot is connected to the gate of the NMOS transistor 701.

Hereinafter, the operation of FIG. 7 will be described.

Compared to FIG. 2, since the newly added component in FIG. 7 operates after the internal voltage VBB is stabilized, the basic operation up to that point is substantially the same as that described in FIG. 2, and thus, a repetitive description is omitted. Hereinafter, the internal voltage VBB is omitted. The following describes how to block the change of the internal voltage (VBB) due to the change in the ground voltage after stabilization.

After a predetermined time elapses after the internal voltage VBB reaches the target value by the pumping operation, the node g1boot becomes -Vt, the node g2boot becomes Vt, and the node p2boot becomes VBB. In this state, in the conventional circuit of FIG. 2, when the VSS voltage becomes high and the gate-source voltage Vgs of the transistor 704 spreads above Vt, a VBB leakage current is generated. To block this, you need to raise the level of the nodes (g1boot, g2boot). To this end, in the present invention, the switching units 707 and 710 are connected to the nodes g1boot and g2boot, and the signal ppe input to the pumping controller of FIG. 4 is at a high level and the signals g1 and g2 are at a high level. In this case, the signals a1 and b1 are turned low to turn on the switching units 707 and 710. In this case, the transistors 703 and 704 can be prevented from turning on even when the level of the nodes g1boot and g2boot rises to increase the VSS. Therefore, generation of the VBB leakage current can be interrupted in advance, so that the VBB voltage level can be kept stable.

In addition, when the charge pumping unit performs a normal operation, the potentials of the nodes g1boot and g2boot should be set to the original ground voltages. In this case, the pumping controller 305 sets the potentials of the nodes g1boot and g2boot to the ground voltage by making the signals a2 and b2 high by using the signals ppe, g1 and g2. When the signals g1 and g2 become VSS by the operation of the charge pumping unit 306, the voltages of the nodes g1boot and g2boot can be made -VCC. Since the normal pumping operation is the same as described previously, further description is omitted.

The charge pumping part of the present invention, that is, the internal voltage generator is configured to block a connection path between the ground voltage and the internal voltage in order to block the internal voltage from fluctuating due to the variation of the surrounding ground voltage (driving voltage) after the internal voltage is stabilized. It generates the element and its blocking signal to block the fluctuation of the internal voltage.

Claims (5)

In the internal voltage generator for generating an internal voltage (VBB) having a level different from the first voltage from the first voltage (VSS) by a pumping operation, A first transistor 701 connected between a first node out and a second node p1boot, a second transistor 702 connected between the first node out and a third node p2boot, and A third transistor 703 connected between a second node p1boot and the first voltage, a fourth transistor 704 connected between the third node p2boot and the first voltage, A first capacitor 713 connected between a first control signal p1 and the second node p1boot and a second capacitor 714 connected between a second control signal p2 and the third node p2boot And a third capacitor 705 connected between the third control signal g1 and the gate of the third transistor 703, and connected between the fourth control signal g2 and the gate of the fourth transistor 704. A fourth capacitor 706, A fifth transistor 709 connected between the gate of the third transistor 703 and the first voltage, a sixth transistor 712 connected between the gate of the fourth transistor 704 and the first voltage; A first switching unit 707 connected between the gate of the third transistor 703 and the second voltage VCC, and a second connected between the gate of the fourth transistor 704 and the second voltage VCC. Internal voltage generator having a switching unit (710). The method of claim 1, The first voltage VSS is ground, the second voltage VCC is a power supply voltage, and the internal voltage is a voltage lower than the ground voltage. The method of claim 2, And the internal voltage is reached to a predetermined target value by using logic level signals applied to the first to fourth control signals. The method of claim 3, wherein After the internal voltage reaches a target value, when the first voltage rises, the first and second switching units 707 and 708 are turned on to turn on the third and fourth transistors 703 and 704. Internal voltage generator, characterized in that. The method of claim 3, wherein And turning on the fifth and sixth transistors (709, 712) to initialize the gate voltage of the third transistor and the gate voltage of the fourth transistor (704) to the first voltage.

Images