KR100739560B1 - Channel equalizer for VSB/QAM - Google Patents

Abstract

VSB / QAM Versatile Channel Equalizer, especially for channel equalization of received signals, depending on whether the received signal is a VSB signal, a QAM signal, and whether it is symbol or fine intervals, real channel equalization or complex channel equalization By generating filter coefficients and controlling the flow of the signal in each case, it is possible to perform channel equalization for VSB and QAM signals with a single equalizer, thus greatly reducing the hardware area for implementing the equalizer. have. In addition, when operating as a fine interval equalizer with N = 2, it is possible to share two tap coefficients in one tap, so that the tap coefficients of the fine interval channel equalizer and the symbol interval channel equalizer can be used equally, minimizing the increase of hardware. can do.

VSB / QAM combined, symbol / fine spacing, channel equalization

Description

USB / AMA dual purpose channel equalizer {Channel equalizer for VSB / QAM}

1 is a block diagram showing a typical VSB signal generation process

2 is a block diagram illustrating a general QAM signal generation process

3 is a block diagram of a typical symbol spacing real channel equalizer for VSB

4 is a block diagram of a typical finely spaced real channel equalizer for VSB

5 is a block diagram of a typical symbol interval complex channel equalizer for VSB

Fig. 6 is a block diagram of a typical finely spaced complex channel equalizer for VSB.

7 is a block diagram of a typical symbol interval complex channel equalizer for QAM

8 is a block diagram of a typical fine-spaced complex channel equalizer for QAM

9 is a block diagram of a VSB / QAM dual-purpose channel equalizer according to the present invention

10 is a signal flow diagram when the VSB / QAM dual purpose channel equalizer of FIG. 9 is used as a symbol spacing real channel equalizer for VSB.

11 is a signal flow diagram when the VSB / QAM dual purpose channel equalizer of FIG. 9 is used as a finely spaced real channel equalizer for VSB.

12 is an operation timing diagram of an I channel signal selector of FIG. 11.

13 is a signal flow diagram when the VSB / QAM dual purpose channel equalizer of FIG. 9 is used as a symbol spacing complex channel equalizer for VSB.                 

14 is a signal flow diagram when the VSB / QAM dual purpose channel equalizer of FIG. 9 is used as a finely spaced complex channel equalizer for VSB.

15 is a signal flow diagram when the VSB / QAM dual purpose channel equalizer of FIG. 9 is used as a symbol spacing complex channel equalizer for QAM.

16 is a signal flow diagram when the VSB / QAM dual purpose channel equalizer of FIG. 9 is used as a finely spaced complex channel equalizer for QAM.

Explanation of symbols for main parts of the drawings

101, 102-1 to 102-3: Data delay unit 103-1 to 103-4: Coefficient calculator

104: decision feedback equalizer 105: adder

106: I channel signal output section 107: Q channel signal output section

The present invention relates to a versatile adaptive channel equalizer that can be commonly used in digital VSB receivers and quadrature amplitude modulation (QAM) receivers. In general, amplitude modulation of a baseband signal to a single carrier yields an output signal having the same information on the upper and lower bands around the carrier on the frequency spectrum. It is not desirable to transmit this output signal in the transmission channel as it is in terms of frequency band utilization efficiency. Therefore, a modulation scheme for transmitting only one sideband of an upper sideband or a lower sideband is required. The method is a single side band (SSB) or a VSB modulation scheme. These two schemes are very similar. In the VSB scheme, additional transmission of some of the remaining sidebands is significantly different from SSB scheme in order to facilitate demodulation at the receiver side.

Meanwhile, digital TV reception technology, which is currently being developed in response to various media (terrestrial wave, cable), is gradually being developed as an integrated system structure, and has a single receiver to receive digital TV transmission signals regardless of the media. Efforts are being made.

Digital TV transmission methods according to such media are largely classified into VSB transmission method using terrestrial wave and QAM transmission method using cable.

In this case, the VSB transmission method loads a desired signal only on a real channel. That is, the input signal is carried only on the I channel. Therefore, Hilbert transforms the I channel signal to produce a Q channel signal. Therefore, the Q channel signal is dependent on the I channel signal.

In the QAM transmission method, a desired signal is loaded on a real channel and an imaginary channel, respectively. That is, different input signals are loaded on the I channel and the Q channel, respectively. Therefore, the I channel signal and the Q channel signal are independent of each other.

FIG. 1 is a block diagram illustrating the generation of such a VSB signal. The VSB baseband input signal x (t) is called an I channel signal.

반송파를 곱하여 가산기(102)로 출력한다.At this time, the I-channel signal is output to the multiplier 101 and to the Hilbert transformer 103. The multiplier 101 cos the I channel signal.

The carriers are multiplied and output to the adder 102.

반송파를 곱하여 가산기(102)로 출력한다.On the other hand, the Hilbert converter 103 inverts the I channel signal by 90 degrees and outputs the result to the multiplier 104. In this case, the I channel signal x ^h (t) inverted 90 degrees by the Hilbert transform unit 103 is commonly referred to as a Q channel signal. The multiplier 104 adds sin to the Q channel signal.

The carriers are multiplied and output to the adder 102.

반송파로 변조된 I 채널 신호와

반송파로 변조된 Q 채널 신호를 더하여 전송하는데, 상기 가산기(102)의 출력 신호 v(t)는 다음의 수학식 1과 같다.The adder 102

Carrier-modulated I-channel signals

A carrier modulated Q channel signal is added and transmitted. The output signal v (t) of the adder 102 is expressed by Equation 1 below.

In this case, the modulated I, Q channel signals are related to each other in the frequency spectrum, except for a part of the center, the lower band has the same value as the I and Q channel signals, and the upper band has the same magnitude and opposite signs. Has a value of. Therefore, when I and Q channel components are added to each other, only a part of the lower wave and the upper wave remain. That is, the bandwidth of the signal is cut in half.

2 is a block diagram illustrating the generation of the QAM signal, in which the QAM baseband input signal x (t) is sent to the I channel and y (t) is sent to the Q channel.

반송파를 곱하여 가산기(203)로 출력하고, 곱셈기(202)는 상기 Q 채널 신호 y(t)에

반송파를 곱하 여 가산기(203)로 출력한다.At this time, the multiplier 201 is applied to the I channel signal x (t).

The carrier wave is multiplied and output to the adder 203, and the multiplier 202 is applied to the Q channel signal y (t).

It multiplies the carrier wave and outputs it to the adder 203.

반송파로 변조된 I 채널 신호와

반송파로 변조된 Q 채널 신호를 더하여 전송하는데, 상기 가산기(203)의 출력 신호 v'(t)는 다음의 수학식 2와 같다.The adder 203 is

Carrier-modulated I-channel signals

A carrier modulated Q channel signal is added and transmitted. The output signal v '(t) of the adder 203 is expressed by Equation 2 below.

In this case, since the above-described QAM transmission method transmits both sidebands together, it requires twice the bandwidth of the VSB transmission method. However, within this double bandwidth, there are independent signals, x (t) and y (t), so the amount of information is also doubled. That is, the QAM transmission method and the VSB transmission method have the same amount of information in the same bandwidth. In addition, since x (t) and y (t) are modulated by carriers that are orthogonal to each other, it is possible to recover the original signal using this orthogonality without any difficulty on the receiving side.

On the other hand, the signal transmitted from the transmitting end is caused various distortions through the transmission channel. Factors that cause the distortion include Gaussian thermal noise, addition due to fading, or distortion due to multiplication noise, frequency variation, nonlinearity, time dispersion, and the like. Such distortion appears as a deterioration in image quality due to distortion in an existing analog TV system, but in a digital transmission system, a bit detection error occurs at a receiving side, and data restoration is impossible or unexpected. In particular, multiple paths due to time delay and phase change of a transmission signal cause severe intersymbol interference, which is a major cause of bit detection error. The technique of reducing the bit detection error at the receiving side by compensating for distortion caused by the abnormal channel is called channel equalization. That is, the channel equalizer removes the ghost when the original signal is changed in magnitude and phase due to channel distortion and a time delayed ghost signal is received together with the original signal during signal transmission. However, since the channel is variable by various factors such as the location, distance, terrain, buildings, weather, etc. of the transceiver, an equalization technique that can be adaptively substituted for the variable channel is required. This technique is called adaptive channel equalization.

In this case, the digital VSB receiver generally uses a symbol interval real adaptive channel equalizer as shown in FIG. 3.

3, N data delays 11-1 to 11-N for delaying the input data x (n) by one symbol, the input data x (n) and the data delays 11-1 to 11 are shown. N + 1 coefficient arithmetic units 12-0 to 12-N for performing coefficient updating by using each output of N and the error value e (n), and each of the coefficient arithmetic units 12-0 to 12-N. An output of the slicer 14 at the output of the adder 13, a slicer 14 estimating an error value e (n) using the output of the adder 13, and an output of the adder 13 The adder 15 calculates an error value e (n) by subtracting the multiplier. In this case, a multiplier 16 for multiplying the output of the adder 15 by the step size μ may be connected to the output terminal of the adder 15. .

Here, the N data delay units 11-1 to 11-N and the N + 1 coefficient calculating units 12-0 to 12-N may include a feed forward filter equalization that cancels the influence of a close ghost; FFE).

Each of the configurations of the coefficient calculating units 12-0 to 12-N is the same, and among the first coefficient calculating units 12-0, for example, the input data x (n) and the error value e (n) are calculated. A multiplier (01) for multiplying, an adder (02) for outputting updated filter coefficients by adding the previous coefficient (c ₁ ) fed back to the output of the multiplier (01), and the adder (02) after storing the output of the adder (02) A multiplier (04) which feeds back to the previous coefficient c ₁ , multiplies the input data x (n) by the updated filter coefficient output through the delay unit 03 and outputs the multiplier to the adder 13. It consists of.

In FIG. 3 configured as described above, input data x (n) is an I channel signal input to the symbol interval real channel equalizer, and x (n-i) is an i symbol delayed value through a data delay.

At this time, the output y (n) of the VSB symbol interval real channel equalizer of FIG.

Where y (n) is the channel equalizer, i.e. the output of adder 13,

        x (n) is the input data,

        c (n) is the channel equalizer coefficient at the current time,                         

        c (n + 1) is the channel equalizer coefficient of the next time, that is, the updated filter coefficient,

        e (n) is the error value,

        μ is the step size.

The step size μ is used to improve the speed of convergence. In other words, in the initial stage, before the adaptive channel equalizer still converges, a large value of step size μ is used to update the coefficient of the equalizer to achieve fast convergence. Use size μ.

In order to update the coefficient of the filter by substituting the error value e (n) obtained by the difference between the signal input from the adder 15 to the slicer 14 and the signal sliced and output from the slicer 14 A multiplier for multiplying e (n) by the input value of the filter is required in each coefficient calculating section 12-0 to 12-N. For example, the multiplier 01 corresponds to the first coefficient calculating unit 12-0.

In addition, the error value e (n) and the output of the slicer 14 are input to a Decision Feedback Equalizer (DFE) 17, which cancels out the influence of distant ghosts, and filtered by the DFE 17. The signal is output to the adder 13 and added. In this case, the DFE may receive only the determined data.

On the other hand, if the phase θ of the ghost is not 0, the demodulated signal has x ^h (t-τ) which is a Hilbert transformed component of the signal x (t-τ) delayed by the delay time τ.

However, these ghost components may not be sufficiently removed by the real channel equalizer and the channel equalizer may not be able to sufficiently follow the channel change.

Accordingly, in order to improve the performance of the receiver, a symbol interval complex channel equalizer for VSB such as FIG. 5 using not only an I channel signal but also a Q channel signal may be used.

Although FIG. 3 performs channel equalization only for the I channel signal, FIG. 5 performs channel equalization not only for the I channel signal but also for the imaginary part of the Q channel signal.

A major difference in configuration with the symbol spacing real channel equalizer of FIG. 3 is that the computation part for the imaginary part is further added. That is, FIG. 5 further adds a filter having the same structure as that of FIG. 3 to channel equalize the Q channel signal. At this time, the output of each coefficient calculating section filtering the I channel signal and the output of each coefficient calculating section filtering the Q channel signal are added to the adder and then output to the slicer. The output of the slicer is output to the DFE and simultaneously to the adder to obtain an error value.

In this case, each of the data delay units of the symbol interval real or complex channel equalizers and the delay units, that is, flip-flops, of the coefficient calculating unit operates by receiving a symbol clock generated in a symbol period. On the other hand, a typical symbol spacing channel equalizer is equipped with a filter tap of a sufficient length and easily removes interference between symbols by appropriately compensating for distortion of a channel caused by a long time ghost in an external environment. Short ghosts can't be rewarded. In addition, if the symbol time recovery circuit does not operate completely, there is a disadvantage in that performance is deteriorated by symbol time noise.                         

Therefore, there is a need to use a finely spaced channel equalizer in some cases.

In other words, if the input sample takes data oversampled at N times the symbol rate (N> 1.0) and uses N times the finely spaced channel equalizer with N tap coefficients at one symbol position, Degradation is not severe, and relatively short ghosts can be relatively removed compared to symbol interval equalizers.

FIG. 4 is a block diagram illustrating an example of a finely spaced real channel equalizer for a typical VSB. The difference from FIG. 3 is that each delay of the data delay unit and the coefficient operation unit, that is, flip-flops, operates at an N times symbol clock. will be. In FIG. 4, when N is set to 2, the data delay unit and the coefficient calculating unit of FIG. 4 operate twice as fast as the symbol time. That is, the flip-flops of the data delay unit and the coefficient operation unit operate at two times the symbol frequency (that is, 1/2 symbol period).

Therefore, the output of the adder that adds all the data output from each coefficient calculating section has two data for each symbol. One of these is symbol data, and the other is virtual data between symbols. Therefore, if the output of the adder is directly input to the slicer, the slicer malfunctions. To prevent this, the output of the adder is output to an adder that obtains an error value through a decimator for extracting symbol data from two pieces of data per symbol.

That is, the decimator is a 2: 1 decimator extracting only a symbol sample from two samples. When the output of the adder passes through the decimator, data of only the instant of the symbol time comes out. As a result, the slicer, the multiplier that generates the error value, and the DFE part operate in symbol periods.

In this case, the data input to the channel equalizer is data sampled at twice the symbol frequency.

FIG. 6 is a block diagram illustrating an example of a general spacing complex channel equalizer for VSB. The basic configuration is the same as the symbol spacing complex channel equalizer for VSB of FIG. 5. The difference from FIG. 5 is that the data delay and each coefficient operation unit operate in synchronization with a double symbol clock as shown in FIG. 4, which adds a decimator between the adder and the slicer.

Meanwhile, in the digital QAM receiver, the symbol interval complex channel equalizer as shown in FIG. 7 or the fine interval complex channel equalizer as shown in FIG. 8 is used for the reasons mentioned above. In this case, in the case of the QAM transmission method, since the Q channel includes data independent of the I channel, channel equalization for the imaginary part as well as the real part must be performed. That is, no real channel equalizer is used in the QAM receiver.

In this case, the output of the QAM channel equalizer and the coefficient update equation are as shown in Equation 4 below.

Where y (n) is the channel equalizer output,                         

x _I (n) is the input real data,

x _Q (n) is the input imaginary data,

c _I (n) is the real channel equalizer coefficient at the current time,

c _Q (n) is the imaginary channel equalizer coefficient at the current time,

        c (n + 1) is the channel equalizer coefficient of

e _I (n) is the real error value,

e _Q (n) is the imaginary error value,

        μ is the step size.

The channel equalizer described so far is summarized as follows.

That is, the VSB receiver performs channel equalization using any one of symbol interval real channel equalizer, symbol interval complex channel equalizer, fine interval real channel equalizer, and fine interval complex channel equalizer, and the QAM receiver performs symbol interval complex number. Channel equalization is performed using either a channel equalizer or a finely spaced complex channel equalizer.

However, digital TV reception technology is currently being developed as an integrated system structure integrating various media (ground wave, cable), and each channel equalization described above in an integrated system structure for receiving both VSB modulated signals and QAM modulated signals. The adoption of these features leads to complex hardware, bulky systems, and increased costs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to control a signal flow so that one channel equalizer is a symbol interval real channel equalizer for VSB, a fine interval real channel equalizer for VSB, a symbol interval for VSB A multi-channel channel equalizer operated by any one of a complex channel equalizer, a fine-interval complex channel equalizer for VSB, a symbol-interval complex channel equalizer for QAM, and a fine-interval complex channel equalizer for QAM.

Another object of the present invention is to provide an adaptive channel equalizer that suppresses an increase in hardware by sharing two tap coefficients in one tap when operating as a finely spaced channel equalizer.

A multi-purpose channel equalizer according to the present invention for achieving the above object, and outputs a mux for selectively outputting the input I channel data and Q channel data and a delay of one symbol or two symbols of the channel data output through the mux An N data delay comprising: a delay and a mux for selectively outputting the 1 or 2 symbol delayed data, and outputting 1 or 2 symbol delayed I channel data or Q channel data; After multiplying the error value according to the time difference between the I channel or Q channel data output from the data delay unit and the input I channel or Q channel symbol interval, and adding the tap coefficient of previous I or Q channel data fed back to the multiplication result 1 N coefficient calculating units for delaying and outputting a symbol or two symbols; A coefficient output unit for adding all of the tap coefficients of the N I or Q channel data updated and output by the N coefficient calculating units, respectively; In the case of a symbol interval, an I channel error value is obtained from the output of the coefficient output unit. In the case of a fine interval smaller than the symbol interval, the coefficient output is obtained by adding the tap coefficients obtained from the signal delayed by one symbol during the first half period of a symbol period. The I channel error value is obtained by adding the result of adding the tap coefficients obtained from the two symbol delayed signal to the coefficient half and adding the result of adding the tap coefficients during the first half period stored after the input from the coefficient output unit. A channel signal output unit; In the case of a symbol interval, a Q channel error value is obtained from an output of the coefficient output unit. In the case of a fine interval smaller than the symbol interval, the addition result of tap coefficients obtained from the one-signal delayed signal is calculated during the first half period of a symbol period. A Q channel error value is obtained by adding and storing the tap coefficients obtained from the two- symbol delayed signal during the next half period and adding the result of adding the tap coefficients during the first half period stored after the input from the coefficient output unit. And a Q channel signal output unit.

Each data delay unit selects and outputs I channel or Q channel data delayed by 1 symbol in the case of a symbol interval, and I channel or Q channel data delayed by 1 symbol during the first half period of a symbol period when the interval is smaller than the symbol interval. And select and output the I-channel or Q-channel data delayed by 2 symbols during the next half cycle.

The coefficient calculating unit multiplies an error value according to a time difference between input I channel or Q channel data and an input I channel or Q channel symbol interval, and tap coefficients of previous I or Q channel data fed back to the output of the multiplier. A first adder to add, a second adder to add the output of the first adder and a multiplication result of the Q channel data and the Q channel error value when used for QAM, or a multiplication result of the Q channel data and the Q channel error value, and A first delay for delaying the output of the first adder or the second adder by one symbol; a second delay for delaying the output of the first delayer by one symbol; and an output of the first delay in the case of a symbol interval. Select the output of the first delay during the first half of the symbol period, and output the second delay during the next half of the symbol period. Select characterized by multiplying the multiplexer and, I channel data or Q channel data output through the output of the multiplexer and the data fed back to the delay to the multiplier consisting of a multiplier for the output to the output coefficients.

The I-channel signal output unit includes a mux for selectively outputting a result of adding tap coefficients during a first half period or '0' according to an enable signal, and a third adder for adding and outputting the output of the coefficient output unit and the mux output. A delayer for storing the output of the coefficient output unit and outputting the result to the mux, a decimator for extracting only symbol samples from the output of the delayer in the case of fine intervals, a slicer for slicing the output of the delayer or decimator, And a fourth adder for obtaining a difference between the signal before being sliced and the sliced signal and outputting the difference as an I channel error value.

The Q channel signal output unit includes a mux for selectively outputting a result of adding tap coefficients during a first half period or '0' according to an enable signal, and a fifth adder for adding and outputting the output of the coefficient output unit and the mux output. A delayer for storing the output of the coefficient output unit and outputting the result to the mux, a decimator for extracting only symbol samples from the output of the delayer in the case of fine intervals, a slicer for slicing the output of the delayer or decimator, And a sixth adder for obtaining a difference between the signal before being sliced and the sliced signal and outputting the difference as a Q channel error value, wherein the channel equalizer operates only when the channel equalizer is used for QAM.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

9 is a block diagram illustrating a multi-purpose adaptive channel equalizer according to the present invention, in which a delay 101 for delaying an input I channel signal by one symbol, and delaying an input I channel signal or a Q channel signal by one symbol or two symbols N data delays 102-1 to 102-3, the one-channel delayed I-channel signal, or errors in the respective outputs of the data delayers 102-1 to 102-3 and the I and Q channels. An adder 105 for adding up the outputs of the N + 1 coefficient calculating units 103-1 to 103-4 for performing coefficient updating using the values Ierror and Qerror, and the respective coefficient calculating units 103-1 to 103-4. Using the output of the adder 105, the I channel signal output unit 106 for estimating and outputting the error value Ierror of the I channel, and outputting the equalized I channel signal Ioutput, using the output of the adder 105 To estimate and output the error value Qerror of the Q channel, and to output the equalized Q channel signal Qoutput. It is configured to include an output unit 107. In addition, FIG. 9 is provided with a DFE 104 that receives Ierror, Qerror, a sliced I channel signal, and a sliced Q channel signal to cancel a ghost effect.

The channel equalizer of the present invention is intended to be used not only for VSB but also for QAM. In this case, since 4 taps serve as 1 tap in the case of QAM, the channel equalizer having 4 taps is illustrated in FIG. 9 for convenience of description. This is one embodiment and in practice, the channel equalizer for VSB or QAM requires dozens of taps, and the number of coefficient calculation units varies depending on the number of taps. That is, one tap corresponds to one coefficient calculating unit.

Here, the four taps act as one tap, which means that four taps are used simultaneously in one symbol time. That is, all four taps represent the same symbol time. The fact that two taps serve as one tap means that two taps are used simultaneously in one symbol time. This is summarized in Table 1 below.

TABLE 1

Channel Equalizer Uses           FFE           DFE Symbol Interval Real Number for VSB 1 tab-> 1 tab Tab spacing-> symbol spacing 1 tab-> 1 tab Tab spacing-> symbol spacing Fine-grained mistake for VSB 1 tab-> 1 tab Tab spacing-> 1/2 symbol spacing 1 tab-> 1 tab Tab spacing-> symbol spacing Symbol Interval Complex Number for VSB 2 tab-> 1 tab Tab spacing-> symbol spacing 1 tab-> 1 tab Tab spacing-> symbol spacing Precision Interval Complex Number for VSB 2 tab-> 1 tab Tab spacing-> 1/2 symbol spacing 1 tab-> 1 tab Tab spacing-> symbol spacing Symbol Interval Complex Number for QAM 4 tab-> 1 tab Tab spacing-> symbol spacing 4 tab-> 1 tab Tab spacing-> symbol spacing Fine Interval Complex Number for QAM 4 tab-> 1 tab Tab spacing-> 1/2 symbol spacing 4 tab-> 1 tab Tab spacing-> symbol spacing

Referring to Table 1, when the channel equalizer is used as a symbol interval real channel equalizer for VSB, one tap serves as one tap, and the tap interval is a symbol interval. Similarly, when a channel equalizer is used as a fine space real channel equalizer for VSB, one tap serves as one tap, and the tab spacing is 1/2 symbol spacing. This is because the input data of the VSB real-time channel equalizer for the VSB and the flip-flops in the channel equalizer sample and operate at a clock that is twice as fast as the symbol period, that is, 1/2 symbol period.

Therefore, when used as a fine interval channel equalizer, a data delay and a coefficient calculating unit twice as large as those when operating as a symbol interval channel equalizer are required.

The present invention proposes a VSB / QAM dual-purpose channel equalizer and at the same time reduces the size of hardware by using the same number of data delay and coefficient generators as the symbol interval channel equalizer even when used as a fine interval channel equalizer.

To this end, two flip-flops are configured in series in each data delay unit and the coefficient calculating unit to delay the input data by one symbol and to delay the one symbol delayed signal by one symbol, that is, two symbols. In addition, the I and Q channel signal output units 106 and 107 select and output '0' during the first half period of the symbol period, and the mux 106-2 and 107- receive and output the channel equalized signal during the first half period during the next half period. 2) and adders 106-1 and 107-1 for adding the outputs of the muxes 106-2 and 107-2 and the channel equalized outputs and storing them for one symbol, and flip-flops 106-3 and 107-3. .

That is, the mux 201 in the data delay unit 102-1 selects the I channel signal Idata or the Q channel signal Qdata and outputs it to the flip-flop 202, and the flip-flop 202 is the mux 201. Delaying the output of the symbol by one symbol and outputting it to the flip-flop 203 at the rear end and to the mux 204 at the same time. The flip-flop 203 delays the output of the flip-flop 202 of the front end by one symbol and outputs the result to the mux 204. That is, the mux 204 receives a signal delayed by one symbol in the flip-flop 202 or a signal delayed by two symbols while passing through two flip-flops 202 and 203 connected in series. In this case, the MUX 204 selects a signal delayed by one symbol in the flip-flop 202 in the case of a symbol interval, and outputs a data delay 102-2 and an updated coefficient to a next stage. Output to multiplier 608 of 2). On the other hand, in the case of fine interval, the flip-flop 202 selects a signal delayed by one symbol during the first half period of the symbol period, and the flip-flop 204 selects a signal delayed by two symbols during the next half period of the symbol clock. The data delay unit 102-2 of the next stage and the multiplier 608 of the coefficient calculating unit 103-2 for outputting the updated coefficient are output. Incidentally, the aforementioned data delays 102-2 and 102-3 also have the same configuration as the above-described data delayer 102-1.

At this time, when the multi-purpose channel equalizer is used as a complex channel equalizer, the mux 401 of the delay unit 101 and the data delay unit 102-3 outputs the I channel signal Idata, and the data delay units 102-1 and 102-. 2) select-output the Q channel signal Qdata.

In the meantime, the MUX 501 selects an Ierror or Qerror signal and outputs the result to the multiplier 502. The multiplier 502 outputs an I-channel signal delayed by one symbol in the flip-flop 101 and the signal. The signal output through the mux 501 is multiplied and output to the adder 503.

The adder 503 adds the output of the multiplier 502 and the filter coefficient of the current time fed back to the adder 504 and the mux 505. The adder 504 multiplies the Q channel signal by the I error value (Qdata * Ierror) and the output of the adder 503 and outputs the result to the mux 505. The mux 505 selects the output of the adder 503 when the channel equalizer is used for VSB, and selects the output of the adder 504 when the channel equalizer is used for VSB and outputs it to the flip-flop 506. The flip-flop 506 delays the output of the mux 506 by one symbol and outputs the result to the flip-flop 507 and the mux 508 at the rear end. The flip-flop 507 delays the output of the flip-flop 506 of the front end by one symbol and outputs it to the mux 508. The mux 508 selects a signal delayed by one symbol in the flip-flop 506 during the first half period of a symbol period in the case of a symbol interval or a fine interval, and in the next half period of the symbol period in the case of a fine interval, the flip-flop ( Signals delayed by two symbols are sequentially selected through the signals 506 and 507 and output to the multiplier 509 and the adder 503. The multiplier 509 multiplies the output of the mux 508 by an I-channel signal delayed by one symbol in the flip-flop 101 and outputs the multiplier 105 to the adder 105.

On the other hand, the mux 601 of the coefficient calculation unit 103-2 selects an Ierror or Qerror signal and outputs the result to the multiplier 602, and the multiplier 602 is output through the data delay unit 102-1. Alternatively, the multiplier multiplies the Q channel signal by the signal output through the mux 601 and outputs the multiplied signal to the adder 603. At this time, if the Q channel error value Qerror is output from the mux 601, the Q channel signal Qdata is output from the data delayer 102-1, and the output of the multiplier 602 is Qdata * Qerror, the Qdata * Qerror signal is The adder 803 of the coefficient calculating unit 103-4 is output.

The adder 603 adds the output of the multiplier 602 and the filter coefficient of the current time fed back to the flip-flop 604. The flip-flop 604 delays the output of the adder 603 by one symbol and outputs it to the flip-flop 605 and the mux 606 at the rear end. The flip-flop 605 delays the output of the flip-flop 604 of the front end by one symbol and outputs it to the mux 606. The mux 606 selects a signal delayed by one symbol in the flip-flop 604 during the first half period of the symbol period in the case of the symbol interval or the fine interval, and the flip-flop during the next half period of the symbol period in the case of the fine interval. By sequentially passing through 604 and 605, a 2-symbol delayed signal is selected and output to the mux 607 and the adder 603. The mux 607 selects the output of the mux 606 when the channel equalizer is used for VSB, and outputs the mux 508 of the previous coefficient calculating unit 102-1 when the channel equalizer is used for VSB. Select and output to the multiplier 608.

The multiplier 608 multiplies the output of the MUX 607 by the I or Q channel signal output through the data delay unit 102-1 and outputs the multiplier 105 to the adder 105.

The multiplier 701 of the coefficient calculator 103-3 multiplies the Ierror signal by the I or Q channel signal output through the data delayer 102-2 and outputs the multiplier 702 to the adder 702. In this case, if the Q channel signal Qdata is output from the data delayer 102-2 and the output of the multiplier 701 is Qdata * Ierror, the Qdata * Ierror signal is added to the adder 504 of the coefficient calculating unit 103-1. Is output.

The adder 702 adds the output of the multiplier 701 and the filter coefficient of the current time fed back to the flip-flop 703. The flip-flop 703 delays the output of the adder 702 by one symbol and outputs it to the flip-flop 704 and the mux 705 at the rear end. The flip-flop 704 delays the output of the front flip-flop 703 by one symbol and outputs it to the mux 705. The mux 705 selects a signal delayed by one symbol in the flip-flop 703 during the first half period of a symbol period in the case of a symbol interval or a fine interval, and in the next half period of the symbol period in the case of a fine interval, the flip-flop ( The two-symbol delayed signal is selected while sequentially passing through 703 and 704 and output to the mux 706 and the adder 702. The mux 706 selects the output of the mux 705 when the channel equalizer is used for VSB, and the mux 807 of the coefficient calculating unit 102-4 of the next stage when the channel equalizer is used for the VSB. The output is selected and output to the multiplier 707.

The multiplier 707 multiplies the output of the mux 706 by the I or Q channel signal output through the data delayer 102-2 and outputs the multiplier 105 to the adder 105.

The multiplier 801 of the coefficient calculator 103-4 multiplies the Ierror signal by the I or Q channel signal output through the data delay 103-3 and outputs the multiplier 802 to the adder 802.

The adder 802 adds the output of the multiplier 801 and the filter coefficient of the current time fed back to the adder 803 and the mux 804. The adder 803 adds the Qdata * Qerror signal output from the multiplier 602 of the coefficient calculator 103-2 and the output of the adder 802 to output to the mux 804. The mux 804 selects the output of the adder 802 when the channel equalizer is used for VSB, and selects the output of the adder 803 when the channel equalizer is used for VSB, and outputs it to the flip-flop 805. The flip-flop 805 delays the output of the mux 805 by one symbol and outputs the result to the flip-flop 806 and the mux 807 at the rear end. The flip-flop 806 delays the output of the flip-flop 805 of the front end by one symbol and outputs it to the mux 807. The mux 807 selects a signal delayed by one symbol in the flip-flop 805 during the first half period of a symbol period in the case of a symbol interval or a fine interval, and in the next half period of the symbol period in the case of a fine interval, the flip-flop ( Signals delayed by two symbols are sequentially selected through 805 and 806, and are output to a multiplier 808, an adder 802, and a mux 706 of the coefficient calculating unit 103-3. The multiplier 808 multiplies the output of the MUX 807 by the I or Q channel signal output through the data delayer 102-3 and outputs the multiplier 105 to the adder 105.

The adder 105 adds both the outputs of the coefficient calculators 103-1 to 103-4 and the outputs of the DFE unit 104 to the I channel output unit 106 and the Q channel output unit 107. do.

The adder 106-1 of the I-channel output unit 106 adds the output of the adder 105 and the output of the mux 106-2 to the flip-flop 106-3, and outputs the flip-flop 106. -3) delays the output of the adder 106-1 by one symbol, feeds it back to the mux 106-2, and outputs the same to the decimator 106-4. The mux 106-2 selects '0' during the first half period of the symbol period in the case of the symbol interval or the fine interval, and outputs the result to the adder 106-1. A value output from the flip-flop 106-3, that is, a signal output during the first half period of the symbol period is selected and output to the adder 106-1. The flip-flop 106-3 receives and stores a signal output through the adder 105 during the first half period of the symbol period through the adder 106-1.

Meanwhile, the decimator 106-4 extracts only symbol samples from two samples output from the flip-flop 106-3 and outputs the symbol samples to the slicer 106-5 and the adder 106-6. At this time, the output of the decimator 106-4 becomes the channel equalized I channel signal Ioutput. The slicer 106-5 determines the signal output from the decimator 106-4 as the signal level closest to the distance and outputs the signal to the adder 106-6 to the DFE unit 104. Output For example, the slicer 106-5 selects a value closest to the output of the decimator 106-4 out of eight values if the transmission scheme is 8 VSB, and if the QS is 256 QAM, the decimator ( Select the value closest to the output of 106-4). The adder 106-6 obtains the difference between the input / output signals of the slice and outputs the error value Ierror of the I channel. In this case, a multiplier 106-7 may be connected to an output terminal of the adder 106-6 by multiplying the output of the adder 106-6 by a step size μ.

The Q channel output section 107 also has the same structure as the I channel output section 106 described above, and its role is also the same. However, the Q channel output unit 107 operates only when the channel equalizer is used for the QAM. At this time, even when a channel equalizer is used as a complex channel equalizer for VSB, the Q channel signal output unit 107 does not operate. This is because the Q-channel signal of the VSB transmission method is only a signal obtained by Hilbert transforming the I-channel signal.

10 to 16 show the VSB / QAM combined channel equalizer of FIG. 9, the symbol interval real channel equalizer for VSB, the fine interval real channel equalizer for VSB, the symbol interval complex channel equalizer for VSB, and the fine interval complex channel for VSB. Each signal flow diagram when using either an equalizer, a symbol interval complex channel equalizer for QAM, or a fine interval complex channel equalizer for QAM is shown.

1) Symbol Spacing Real Channel Equalizer for VSB

Figure 10 shows a signal flow diagram when the multi-purpose channel equalizer according to the present invention is used as a symbol spacing real channel equalizer for VSB.

That is, when the multi-purpose channel equalizer is used as a symbol spacing real channel equalizer for VSB, the output equation of the channel equalizer and the update coefficient of the filter coefficient are the same as in Equation 3 above, and the same as in Equation 5 below.

Where y (n) is the channel equalizer output,

        x (n) is the input data,

        c (n) is the channel equalizer coefficient at the current time,

        c (n + 1) is the channel equalizer coefficient of the next time, that is, the updated filter coefficient,                     

        e (n) is the error value,

        μ is the step size.

That is, since one tap serves as one tap, channel equalization of four symbols is performed during four taps. 10, two muxes of each of the data delay units 102-1 to 102-3 select and output only one signal delayed by one symbol. The first multipliers of the coefficient calculating units 103-1 to 103-4 multiply the Ierror signal by the I-channel signals output from the data delayers 102-1 to 102-3 and output them to the next stage adder.

For example, referring to the first coefficient calculator 103-1, the I channel error value Ierror output through the mux 501 is multiplied by the I channel signal in the multiplier 502 and output to the adder 503. In this case, the adder 503 adds the output signal Ierror * Idata of the multiplier 502 and the current filter coefficient C ₁ fed back, and the added signal is output to the flip-flop 506 through the mux 505 to delay 1 symbol. do. The mux 508 selects a signal delayed by one symbol from the flip-flop 506, outputs the signal to the multiplier 509, and feeds it back to the adder 503. This operation is similarly performed in the coefficient calculating units 102-2 to 102-4.

That is, the output signal of the channel equalizer output from the adder 105 during one symbol time is expressed by Equation 6 below.

The enable signal of the mux 106-2 of the I channel signal output unit 106 is always low so that the mux 106-2 always selects '0'.

As a result, it can be seen that the general symbol interval channel equalizer for VSB of FIG. 3 and the multipurpose channel equalizer of FIG. 10 perform the same function.

2) Finely Spaced Real Channel Equalizer for VSB

11 is a signal flow diagram when the multi-purpose channel equalizer according to the present invention is used as a finely spaced real channel equalizer for VSB.

In FIG. 11, only the slicer, the multiplier for generating an error value, the DFE unit, and the decimator operate as the symbol clock, and the remaining portions operate as the clock twice as fast as the symbol clock.

At this time, during the first half period of the symbol period it operates in the same manner as in FIG. During the next half period of the symbol period, a two-symbol delayed signal is selected from each mux of the data delay units 102-1 to 102-3 and the coefficient calculating units 103-1 to 103-4. different.

The operation principle is as follows.

In FIG. 4, assuming that x ₅ , x ₄ , x ₃ , x ₂ , x ₁ , x ₀ are loaded from the left to the right of the input terminal, the flip-flop 106-3 of the front end of the decimator 106-4 is performed. The value of the output A point is x ₅ c _1.1 + x ₄ c _1.2 + x ₃ c _2.1 + x ₂ c _2.2 + x ₁ c _3.1 + x ₀ c _3.2 .

However, in FIG. 11, x ₄ c _1.2 + x ₂ c _2.2 + x ₀ c _3.2 is output through the adder 105 during the first half period of the symbol period, and x ₅ c _1.1 + x ₃ c _2.1 + x ₁ during the next half period. c _3.1 is output and input to the adder 106-1 of the I-channel signal output section 106.

In this case, the enable signal input to the MUX 106-2 becomes low during the first half period of the symbol period and becomes high during the next half period. Accordingly, the mux 106-2 selects '0' during the first half period of the symbol period and outputs the result to the adder 106-1, and the adder 106-1 outputs through the adder 105. ₄ c _1.2 + x ₂ c _2.2 + x ₀ Only _3.2 c is outputted as flip-flop 106-3.

The flip-flop 106-3 delays the signal x ₄ c _1.2 + x ₂ c _2.2 + x ₀ c _3.2 by one symbol and outputs the signal to the decimator 106-4 while feeding back to the mux 106-2. Let's do it. Accordingly, the mux 106-2 selects the signal x ₄ c _1.2 + x ₂ c _2.2 + x ₀ c _3.2 and outputs the signal to the adder 106-1 during the next half period of the symbol period. Accordingly, the adder 106-1 outputs a signal x ₅ c _1.1 + x ₄ c _1.2 + x ₃ c _2.1 + x ₂ c _2.2 + x ₁ c _3.1 + x ₀ c _3.2 .

FIG. 12 is a timing diagram showing an operation state of the above-described I channel signal output unit 106. FIG. 12 shows an example of a double symbol clock, point A front end data, point A data, an enable signal, and a symbol clock. That is, during the first half period of the symbol period, the enable signal is low, and the '0' value is output from the mux 106-2. Therefore, at point A, x ₄ c _1.2 + x ₂ c _2.2 + x ₀ c _3.2 is entered. The enable signal is high during the half cycle, so the mux (106-2) outputs the value x ₅ c _1.1 + x ₃ c _2.1 + x ₁ c _3.1, so at point A, x ₅ c _1.1 + x ₄ c _1.2 + x ₃ c _2.1 + x ₂ c _2.2 + x ₁ c _3.1 + x ₀ c _3.2 is entered. And, since this output is output to the 2: 1 decimator 106-4, the above-described Fig. 4 and Fig. 11 performs the same operation.

However, according to the above-described operation process, FIG. 11 can reduce the number of data delay units and coefficient calculating units twice as much as in FIG. For example, if eight data delay units and eight coefficient operators are required in FIG. 4, only four data delay units and four coefficient operators are required in the case of FIG. 11.

3) Symbol Interval Complex Channel Equalizer for VSB

13 is a signal flow diagram when the multi-purpose channel equalizer according to the present invention is used as a symbol interval complex channel equalizer for VSB.

The operation of the data delay is similar to the operation of the data delay of FIG. 10 described above, except that the data delays 102-1 and 102-2 select Q channel data instead of I channel data, and then one flip-flop and a mux. Delay 1 symbol through the output. At this time, the data delay unit 102-3 receives the I channel signal output from the flip-flop 101 and delays one symbol.

Therefore, the expression of the output of the symbol interval complex channel equalizer for the VSB and the filter coefficient are as shown in Equation 7 below.

Where y _I (n) is the channel equalizer output,

x _I (n) is the input real data,

x _Q (n) is the input imaginary data,

c _I (n) is the real channel equalizer coefficient at the current time,

c _Q n) is the imaginary channel equalizer coefficient of the current time,

        c (n + 1) is the channel equalizer coefficient of

e _I (n) is the real error value,

        μ is the step size.

이 따로 필요없고, 오류값도 실수 오류값 즉, Ierror만이 사용되기 때문이다.As can be seen from Equation 7, the complex update equation of the VSB case and the QAM case is different. The reason is that both are channel equalizers defined on the complex plane, but the Q channel output of the VSB is only Hilbert transformed, not data independent of the I channel.

This is not necessary, and the error value is a real error value, that is, only Ierror is used.

Therefore, the output of the channel equalizer output from the adder 105 during one symbol time may be expressed as Equation 8 below.

Since the remaining operations are similar to those of FIG. 10 described above, detailed descriptions are omitted.                     

4) Fine-spaced complex channel equalizer for VSB

14 is a signal flow diagram when the multi-purpose channel equalizer according to the present invention is used as a finely spaced complex channel equalizer for VSB.

That is, the operation of the I channel signal output section 106 is the same as the signal flow diagram of the finely spaced complex channel equalizer for the VSB of FIG. 11 described above.

The difference from FIG. 11 is that the data retarders 102-1 and 102-2 select Q channel data instead of I channel data and output two symbol delays through two flip-flops and a mux connected in series. In this case, the data delayer 102-3 receives an I channel signal output from the flip-flop 101, delays two symbols, multiplies the Ierror signal, and adds the updated coefficient value to the adder 105. It is output by the output multiplier.

The operation of the coefficient calculating units 103-1 to 103-4 is similar to that of FIG. 11 except that the multipliers of the coefficient calculating units 103-2 and 103-2 receive the Q channel signals through the respective data delay units. Since it is the same, detailed description is omitted.

5) Symbol Interval Complex Channel Equalizer for QAM

15 is a signal flow diagram when the VSB / QAM dual-purpose channel equalizer according to the present invention is used as a QAM symbol interval complex channel equalizer. In the case of FIG. 15, the I channel signal output unit 106 and the Q channel signal output unit 107 are shown. ), Ierror and Qerror signals are obtained.

In this case, the output of the QAM channel equalizer and the coefficient update equation are as shown in Equation 9 below.                     

Where y (n) is the channel equalizer output,

x _I (n) is the input real data,

x _Q (n) is the input imaginary data,

c _I (n) is the real channel equalizer coefficient at the current time,

c _Q n) is the imaginary channel equalizer coefficient of the current time,

        c (n + 1) is the channel equalizer coefficient of

e _I (n) is the real error value,

e _Q (n) is the imaginary error value,

        μ is the step size.

That is, the data delayers 101 and 102-3 select and output the I channel data Idata, and the data delayers 102-1 and 102-2 select and output the Q channel data Qdata.

The multiplier 502 of the coefficient calculating unit 103-1 multiplies the Q channel error value Qerror by Idata output through the data delay unit 101 and outputs the multiplier 503 to the adder 503. The adder 503 adds the previous coefficient C _Q.1 fed back from the mux 508 and the output of the multiplier 502 to output to the adder 504. The adder 504 adds the Qdata * Ierror signal output from the coefficient calculating unit 103-3 and the output of the adder 503, and then through the mux 505, the flip-flop 506, and the mux 508. The multiplier 509 outputs the multiplier 509 and the mux 607 of the adder 503 and the coefficient calculating unit 103-2. The multiplier 509 multiplies the output of the MUX 508 by the Idata output from the data delayer 101 and outputs the multiplier 105 to the adder 105.

The multiplier 602 of the coefficient calculating unit 103-2 outputs Qdata and Q channel error values Qerror output through the mux 201, the flip-flop 202, and the mux 204 of the data delay unit 102-1. It multiplies by and outputs to the adder 803 of the coefficient calculating part 103-4. In addition, the mux 607 multiplies the Q coefficient Qcoef output from the mux 508 of the coefficient calculating unit 103-1 and the Qdata output from the mux 204 of the data delayer 102-1 to add the 105. ) The multiplier 702 of the coefficient calculating unit 103-3 outputs Qdata and I channel error values Ierror output through the mux 301, the flip-flop 302, and the mux 304 of the data delay unit 102-2. It multiplies by and outputs to the adder 503 of the coefficient calculating part 103-1. In addition, the mux 707 multiplies the I coefficient Icoef output from the mux 807 of the coefficient calculating unit 103-4 and the Qdata output from the mux 304 of the data delay unit 102-2 to add the adder 105. )

The multiplier 801 of the coefficient calculating unit 103-4 outputs an I channel error value Ierror and Idata output through the mux 401, the flip-flop 402, and the mux 404 of the data delay unit 102-3. Multiply by and output to the adder 802. The adder 802 adds the previous coefficient C _I.1 fed back from the mux 807 and the output of the multiplier 801 to output to the adder 803. The adder 803 adds the Qdata * Qerror signal output from the coefficient calculating unit 103-2 and the output of the adder 802 and then through the mux 804, the flip-flop 805, and the mux 807. The multiplier 808, the adder 802, and the mux 706 of the coefficient calculating unit 103-3 are output. The multiplier 808 multiplies the output of the MUX 807 by the Idata output from the data delayer 102-3 and outputs the multiplier 105 to the adder 105.

The adder 105 adds all the outputs of the coefficient calculators 103-1 to 103-4 and the DFE 104, and then outputs them to the I-channel signal output unit 106 and the Q-channel signal output unit 107.

The mux 106-2 of the I channel signal output unit 106 always selects '0' and outputs it to the adder 106-1. That is, the adder 106-1 outputs the output of the adder 105 as a channel equalized signal Ioutput through the flip-flop 106-3 and the decimator 106-4 and simultaneously slices and outputs an error value. To the slicer 106-5 and the adder 106-6. The slicer 106-5 slices an input signal and outputs the added signal to the adder 106-6 and the DFE 104, and the adder 106-6 outputs an I channel with a difference between the input and output signals of the slice 106-5. Get the error value Ierror. The I channel error value Ierror is multiplied by the step size μ in the multiplier 106-7.

The Q channel signal output unit 107 has the same operation as the I channel signal output unit 106 except for outputting the channel equalized Q signal Qoutput and the Q channel error value Qerror.

6) Fine spacing complex channel equalizer for QAM

16 is a signal flow diagram when the VSB / QAM dual-purpose channel equalizer according to the present invention is used as a QAM fine-interval complex channel equalizer. In FIG. 16, the I-channel signal output unit 106 and the Q-channel signal output unit 107 are shown. ), Ierror and Qerror signals are obtained.

FIG. 16 operates in the same signal flow as in FIG. 15 during the first half period of a symbol period, and performs channel equalization using a two-symbol delayed signal through two flip-flops connected in series during the next half period of the symbol period.

That is, the muxes 204, 304, and 404 of the data delayers 102-1 through 102-3 selectively output the outputs of the flip-flops 202, 302, and 402 during the first half period of the symbol period, and the flip-flops 203, 303, and 403 during the next half period of the symbol period. Select output to output.

Also, the muxes 508 and 807 of the coefficient calculating units 103-1 and 103-4 selectively output the outputs of the flip-flops 506 and 805 during the first half period of the symbol period, and output the outputs of the flip-flops 507 and 806 during the next half period of the symbol period. Selective output.

The muxes 106-2 and 107-2 of the I-channel signal output section 106 and the Q-channel signal output section 107 select zeros during the first half period of the symbol period and output them to the adders 106-1 and 107-1. During the next half period of the symbol period, a signal stored in the flip-flops 106-3 and 107-3 (that is, a channel equalized signal during the first half period of the symbol period) is selected and output to the adders 106-1 and 107-1.

As described above, according to the VSB / QAM multi-purpose channel equalizer according to the present invention, when equalizing a received signal, the received signal is a VSB signal, a QAM signal, and whether the equalization interval is a symbol interval, a fine interval, or a real channel equalization. By generating the corresponding filter coefficients according to whether they are complex channel equalization and controlling the flow of the signal in each case, real or complex channel equalization of the VSB and QAM signals with a single equalizer is performed at symbol interval or fine interval. can do. Therefore, the hardware area for implementing the channel equalizer can be greatly reduced.

In addition, when operating as a fine interval equalizer with N = 2, it is possible to share two tap coefficients in one tap, so that the tap coefficients of the fine interval channel equalizer and the symbol interval channel equalizer can be used equally, minimizing the increase of hardware. can do.

And, by supporting all the methods of the conventional LMS equalizer can be very useful in the chip development stage.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (5)

It consists of a mux for selectively outputting the input I channel data and the Q channel data, a delay for delaying the output of the channel data output through the mux by 1 symbol or 2 symbols, and a mux for selectively outputting the 1 or 2 symbol delayed data. N data delays for outputting one or two symbol delayed I channel data or Q channel data; After multiplying the error value according to the time difference between the I channel or Q channel data output from the data delay unit and the input I channel or Q channel symbol interval, and adding the tap coefficient of previous I or Q channel data fed back to the multiplication result 1 N coefficient calculating units for delaying and outputting a symbol or two symbols; A coefficient output unit for adding all of the tap coefficients of the N I or Q channel data updated and output by the N coefficient calculating units, respectively; In the case of a symbol interval, an I channel error value is obtained from the output of the coefficient output unit. In the case of a fine interval smaller than the symbol interval, the coefficient output is obtained by adding the tap coefficients obtained from the signal delayed by one symbol during the first half period of a symbol period. The I channel error value is obtained by adding the result of adding tap coefficients obtained from the two- symbol delayed signal during the next half period and adding the result of adding tap coefficients during the first half period stored after inputting from the coefficient output unit. A channel signal output unit; And In the case of a symbol interval, an error value according to a time difference of a Q channel symbol interval is obtained from the output of the coefficient output unit. In the case of a fine interval smaller than the symbol interval, the tap coefficients obtained from the signal delayed by one symbol during the first half period of a symbol period are obtained. The addition result is received from the coefficient output unit and stored, and during the next half cycle, the addition result of the tap coefficients obtained from the two symbol delayed signal is received from the coefficient output unit, and Q is added to the addition result of the tap coefficients stored during the first half cycle. And a QB signal output unit for calculating a channel error value. The method of claim 1, wherein each data delay unit In the case of a symbol interval, I-channel or Q-channel data with one symbol delay is selected and outputted.In the case of a minute interval smaller than the symbol interval, I-channel or Q-channel data with one symbol delayed is selectively outputted during the first half period of the symbol period. VSB / QAM Versatile Channel Equalizer, characterized by selectively outputting two-channel delayed I-channel or Q-channel data for the next half cycle. The method of claim 1, wherein the coefficient calculating unit A multiplier that multiplies the input I channel or Q channel data with the input I channel or Q channel error value, A first adder for adding the tap coefficients of previous I or Q channel data fed back with the output of the multiplier; A second adder which, when used for QAM, adds the multiplication result of the Q channel data and the I channel error value or the multiplication result of the Q channel data and the Q channel error value and the output of the first adder; A first delayer for delaying the output of the first adder or the second adder by one symbol; A second delayer for delaying the output of the first delayer by one symbol again; In the case of symbol interval, the output of the first delay unit is selected. In the case of fine interval, the output of the first delay unit is selected during the first half period of the symbol period, and the output of the second delay unit during the next half period. Select mux and feed back to the multiplier, And a multiplier for multiplying the I-channel data or the Q-channel data output through the output of the mux and outputting the multiplier to the coefficient output unit. The method of claim 1, wherein the I channel signal output unit A mux for selectively outputting the addition result of tap coefficients during the first half-cycle or '0' according to the enable signal; A third adder for adding and outputting the output of the coefficient output unit and the output of the mux, A delay unit for storing the output of the coefficient output unit and outputting the output to the mux; In the case of fine interval smaller than the symbol interval, the decimator extracts only symbol samples from the output of the delayer, A slicer which slices an output of the delay or decimator, And a fourth adder for obtaining a difference between the signal before being sliced and the sliced signal and outputting the difference as an I channel error value. The method of claim 1, wherein the Q channel signal output unit A mux for selectively outputting the addition result of tap coefficients during the first half-cycle or '0' according to the enable signal; A fifth adder for adding the output of the coefficient output unit and the output of the mux to output the sum; A delay unit for storing the output of the coefficient output unit and outputting the output to the mux; A decimator for extracting only symbol samples from an output of the delay unit in case of a fine interval smaller than the symbol interval, A slicer which slices an output of the delay or decimator, And a sixth adder for obtaining a difference between the signal before being sliced and the sliced signal and outputting the difference as a Q channel error value.

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