KR100732257B1 - Page buffer and method of erase varify of flash memory device using thereof - Google Patents

Abstract

The present invention relates to a page buffer and an erase verification method of a flash memory device using the same, and includes a sensing node between an NMOS transistor driven according to a potential of a sensing node and an NMOS transistor driven according to a main latch signal in a page buffer of a dual register structure. Compared to the conventional method of generating an erase verify signal by adding an NMOS transistor driven according to a potential of the transistor, and extracting the potential between the NMOS transistors driven according to the potential of the sensing node as an erase verify signal, thereby inverting the output signal of the main latch. A page buffer and an erase verification method using the same are provided to reduce the erase verification time and reduce the number of circuits required for the erase verification.

Page buffer, erase verification. Verification time

Description

Page buffer and method of erase varify of flash memory device using pretty}             

1 is a block diagram of a page buffer according to an embodiment of the present invention.

2 is an erase verify circuit diagram according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: memory cell array 200: bit line selection unit

110: main latch 120: cache latch

The present invention relates to a NAND type flash memory device, and more particularly, to a page buffer and an erase verify method using the same, by generating an erase verify signal according to a potential of an input terminal of a main latch.

There is an increasing demand for semiconductor memory devices that can be electrically programmed and erased and that do not require a refresh function that rewrites data at regular intervals. In order to develop a large-capacity memory device capable of storing a large amount of data, research on high integration technology of memory devices has been actively conducted. Here, the program refers to an operation of writing data to a memory cell, and the erasing refers to an operation of removing data written to the memory cell.

For high integration of memory devices, a NAND type flash memory device is developed in which a plurality of memory cells are connected in series (that is, a structure in which adjacent cells share drain or source with each other) to form a string. It became. Unlike NOR-type flash memory devices, NAND-type flash memory devices are memory devices that read information sequentially. Programming and erasing of such a NAND type flash memory device is performed by controlling the threshold voltage of the memory cell while injecting or emitting electrons into a floating gate using an F-N tunneling method.

A NAND type flash memory device uses a page buffer to store a large amount of information or to read stored information in a short time. The page buffer receives a large amount of data from an input / output pad and provides the memory cells or stores and outputs data of the memory cells. In general, the page buffer is generally composed of a single register for temporarily storing data. However, in recent years, the NAND-type flash memory device has a dual register to increase program speed when programming a large amount of data.

A voltage of 0 V is applied to a word line for erase verification after an erase operation during operation of a NAND type flash memory device having a page buffer of a dual register structure, and an even bit line or an odd bit line not selected by an address. It is supposed to apply 0V. The bit line selected for erasure verification performs erase verification through three steps of precharge, evaluation, and sensing, similar to a general read operation.

On the other hand, since the NAND-type flash memory device performs programming in units of pages and erases in units of blocks, the program verifying operation executes one page at the same time, but the erase verifying operation is performed by verifying one page and verifying one block. Will have the same effect. By the way, program verification and erasure verification are performed by detecting a signal output in accordance with the potential of the output terminal of the main latch. However, since the level of the signal according to the program verification and the signal according to the erasure verification are opposite to each other, the output signal must be inverted for erasure verification. In addition, unlike program verification, for example, large sized NAND gates, NOR gates, and inverters are required to logically combine 16-bit IO. Thus, multiple logic elements and time are required for erase verification.

An object of the present invention is to provide a page buffer capable of shortening a verification time by generating an erase verify signal according to a potential of an input terminal of a main latch and an erase verify method of a flash memory device using the same.

In accordance with another aspect of the present invention, a page buffer includes: a bit line selector configured to selectively connect an even bit line or an odd bit line connected to a memory cell array with a sensing node according to a bit line selection signal; A first switch operated by a precharge signal to supply a predetermined voltage to the sensing node to precharge the even bit line or the odd bit line; A main latch for storing state data of the selected cell; At least one switch means for operating in accordance with the potential of the sensing node and the main latch signal to adjust the potential of the first terminal of the main register and to store state data of the selected cell in the main latch while simultaneously outputting an erase verify signal; A second switch comprising; A third switch for operating the potential of the second terminal of the main register to output a program verify signal; A cache latch for storing program data according to a control signal during programming; A fourth switch operated by a transfer control signal to transfer data stored in the cache latch to the main register; And a fifth switch operating according to a program signal to transfer program data stored in the main register to the selected memory cell for programming.

The bit line selector may include: first and second NMOS transistors configured to discharge memory cells connected to the even bit line or the odd bit line according to first and second discharge signals; And third and fourth NMOS transistors for respectively connecting the even bit line or the odd bit line and the node according to the first and second bit line selection signals.

The first switch includes a PMOS transistor for supplying a power voltage to the sensing node according to the precharge signal.

The second switch may include first and second NMOS transistors driven according to a potential of the sensing node; And a third NMOS transistor driven according to the main latch signal, and outputs the erase verify signal according to a potential of a first input terminal of the main latch from a connection point of the first and second NMOS transistors.

The erase verification signal maintains a floating state in the case of an erased cell and a low level in the case of an unerased cell.

And an NMOS transistor for initializing the main latch.

The third switch includes an NMOS transistor for outputting the program verify signal in a low level or floating state according to the potential of the second terminal of the main latch.

Meanwhile, an erase verification method of a flash memory device according to an exemplary embodiment may include: initializing a main latch after discharging a bit line selected for a program or erase verification; Evaluating a cell connected to the selected bit line after precharging the selected bit line to a predetermined potential; And storing data according to the state of the selected memory cell in the main latch, and outputting an erase verification signal according to the state of the first terminal of the main latch.

The erase verify signal maintains a floating state when the cell is erased and maintains a low level when the cell is not erased.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a configuration diagram of a page buffer of a NAND type flash memory device according to an exemplary embodiment of the present invention, and includes a cash register for inputting program data from an external source during a program operation, and data from a cache register during a program operation. After receiving and storing the data, the main register may be provided to the memory cell array 100 according to the bit line selector 200 or may include a main register for storing data according to the state of the memory cell during the verify operation.

The NMOS transistors N101 and N102 constituting the bit line selector 200 are driven in accordance with the discharge signals DISCHe and DISCHo, respectively, to drive the voltage according to the signal VIRPWR to the even bit line BLe or the odd bit line. It is applied to the memory cells of the memory cell array 100 connected to BLo. In addition, the NMOS transistors N103 and N104 constituting the bit line selection unit 200 are driven in accordance with the bit line selection signals BSLe and BSLo so that predetermined bit lines BLe and BLo and pages of the memory cell array 100 are driven. Connect the buffer.

The PMOS transistor P101 is driven according to the precharge signal PRECHb to supply predetermined power to the node S0. The main latch 110 stores data according to a state of a predetermined cell of the memory cell array 100, or stores data from the outside supplied through the cache latch 120. The NMOS transistors N105 and N106 are driven according to the potential of the node S00, and the NMOS transistor N107 is driven according to the main latch signal MLCH to invert the potential of the node QBb. Here, the potential between the NMOS transistors N105 and N106, i.e., the potential of the node QBb, is output as the erase verify signal nWDO. In the case of the erased cell, the floating state is maintained, and the erased or programmed cell is maintained. Output at the low level of. The NMOS transistor N108 is driven according to the main latch reset signal MRST to initialize the main latch 110 by bringing the node QB to a ground potential. The NMOS transistor N109 is driven according to the potential of the node QB to output a program verify signal nWD that maintains the power supply voltage Vcc level or the floating state.

The cache latch 120 stores data supplied from the outside during programming. The NMOS transistor N114 is driven according to the potential of the node SO, and the NMOS transistor N115 is driven according to the cache latch signal CLCH to invert the potential of the node QA. The NMOS transistor N110 is driven according to the cache register set signal CSET to initialize the cache latch 120 by bringing the node QAb to the ground potential. The NMOS transistors N111 and N112 are driven according to the signal DI1 that is activated when the data input from the input / output pad YA is "1" during programming to supply "1" data to the node QAb. The NMOS transistor N113 is driven according to the signal nDI that is activated when data input from the input / output pad YA is "0" during programming to supply "0" data to the node QA. The NMOS transistor N116 is driven according to the control signal PDUMP to transfer data stored in the cache latch 120 to the main latch 110.

The NMOS transistor N117 is driven according to the program signal PGM during a program operation so that data to be programmed stored in the main latch 110 is transmitted to the selected bit line. The NMOS transistor N118 is driven according to the signal PBDO to output the potential of the node QB.

The erase verification method using the page buffer according to the present invention configured as described above is as follows.

When the discharge signal DISCHe is applied at a low level and the discharge signal DISCHo is applied at a high level, the NMOS transistor N101 is turned off, and the NMOS transistor N102 is turned on to apply a potential of 0V during a read operation. The holding signal VIRPWR is supplied to the odd bit line BLo. Therefore, the even bit line BLe is selected and the odd bit line BLO is not selected. Then, the main latch reset signal MRST is applied to the high level to turn on the NMOS transistor N108 to initialize the output terminal QB of the main latch 110 to the low level, and then the precharge signal PRECHb to the low level. The PMOS transistor P101 is turned on to maintain the node SO at a high level. After that, the bit line selection signal BSLe is applied to the potential of the first voltage V1 so that the selected bit line BLe is precharged to V1-Vt, and then the bit line selection signal BSLe is applied to the low level. Evaluate the cell. At this time, the word lines are all applied at 0V. Then, the precharge signal PRECHb is applied to the high level to turn off the PMOS transistor P101, and then the bit line selection signal BSLe is applied to the potential of the second voltage V2, and the main latch signal MLCH is applied. Is applied at a high level to turn on the NMOS transistor N107. Therefore, the potential of the node SO changes according to the state of the cell, and thus the potential of the input terminal QBb and the output terminal QB of the main latch 110 changes. That is, in the case of an erased cell, the node SO maintains a low level potential, and in the case of an unerased cell, the node SO maintains a high level potential. Therefore, when the node SO maintains the low level, the NMOS transistors N105 and N106 are turned off and the potentials of the nodes QBb and QB are not changed, so that the node QBb maintains the high level. Thus, the erase verify signal nWDO remains in a floating state. In contrast, when the node SO maintains a high level, the NMOS transistors N105 and N106 are turned on, and since the transistor N107 is turned on, the potential of the node QBb becomes low, and the node QB High level. Therefore, the erase verify signal nWDO is output at a low level. On the other hand, the program verification operation can be performed in the same manner as described above. The power supply voltage Vcc or the program verification signal nWD in the floating state is outputted by the NMOS transistor N019 driven according to the potential of the node QB. Program verification can be performed. That is, in the case of a programmed cell, the node QB remains high so that the NMOS transistor N109 is turned on to output a high level program verify signal nWD. In the case of an unprogrammed cell, the node QB is low. Keeping the state, the program verify signal nWD is plotted.

FIG. 2 is an erase verify circuit diagram according to an embodiment of the present invention, and is configured to logically combine a signal nWDO_E combining an erase verify signal nWDO output from a plurality of page buffers according to a verify enable signal check. An AND gate 201 and an NMOS transistor N201 for charging the erase verify combination signal nWDO_E to the power supply voltage Vcc level in accordance with the verify enable signal check. However, since the NMOS transistor N201 is a transistor composed of a ratio of width and length of the NMOS transistor to 1.2 / 10, the NMOS transistor N201 can charge a node in a floating state at a power supply voltage (Vcc) level, but has a low level node. Does not affect.

When all cells are successfully erased and the erase verify signals nWDO output from the plurality of page buffers are all floating, the erase verify combination signal nWDO_E also maintains the floating state. At this time, when the verify enable signal check is applied at a high level, the NMOS transistor N201 is turned on to charge the erase verify combination signal nWDO_E to a high level. Accordingly, the AND gate 201 combines the high level verify enable signal check and the high level erase verify combination signal nWDO_E to output the high level verify signal WDO to determine that the erase is successful.

However, when all cells are not successfully erased and even one cell is not erased and even one erase verify signal nWDO is output in a low state, the erase verify combination signal nWDO_E maintains a low level. However, even when the verify enable signal check is applied at a high level due to the characteristics of the NMOS transistor N201, the potential of the low level erase verify combination signal nWDO_E is not affected. Accordingly, the AND gate 201 combines the high level verify enable signal check and the high level erase verify combination signal nWDO_E to output the high level verify signal WDO to determine that the erase has failed.

As described above, according to the present invention, an NMOS transistor driven according to the potential of the sensing node is added between the NMOS transistor driven according to the potential of the sensing node and the NMOS transistor driven according to the main latch signal, and according to the potential of the sensing node. By extracting the potential between the driven NMOS transistors as the erase verify signal, the erase verify time can be reduced and the number of circuits required for erase verify can be reduced as compared with the conventional method of generating the erase verify signal by inverting the output signal of the main latch. .

Claims (9)

A bit line selector for selectively connecting even bit lines or odd bit lines respectively connected to the memory cell array with the sensing node according to the bit line selection signal; A first switch operated by a precharge signal to supply a predetermined voltage to the sensing node to precharge the even bit line or the odd bit line; A main latch for storing state data of the selected cell; At least one switch means for operating in accordance with the potential of the sensing node and the main latch signal to adjust the potential of the first terminal of the main register and to store state data of the selected cell in the main latch while simultaneously outputting an erase verify signal; A second switch comprising; A third switch for operating the potential of the second terminal of the main register to output a program verify signal; A cache latch for storing program data according to a control signal during programming; A fourth switch operated by a transfer control signal to transfer data stored in the cache latch to the main register; And And a fifth switch operating in accordance with a program signal to transfer program data stored in said main register to said selected memory cell for programming. The semiconductor device of claim 1, wherein the bit line selector comprises: first and second NMOS transistors configured to discharge memory cells connected to the even bit line or the odd bit line according to first and second discharge signals; And And third and fourth NMOS transistors for coupling the even bit line or the odd bit line and the node according to first and second bit line selection signals, respectively. The page buffer of claim 1, wherein the first switch comprises a PMOS transistor for supplying a power voltage to the sensing node according to the precharge signal. The semiconductor device of claim 1, wherein the second switch comprises: first and second NMOS transistors driven according to a potential of the sensing node; And And a third NMOS transistor driven according to the main latch signal, and outputting the erase verify signal according to a potential of a first input terminal of the main latch from a connection point of the first and second NMOS transistors. 5. The page buffer of claim 4, wherein the erase verify signal maintains a floating state in an erased cell and a low level in an unerased cell. 5. The page buffer of claim 4, further comprising an NMOS transistor for initializing the main latch. The page buffer of claim 1, wherein the third switch includes an NMOS transistor configured to output the program verify signal in a low level or a floating state according to a potential of the second terminal of the main latch. Initializing the main latch after discharging the selected bit line for program or erase verification; Evaluating a cell connected to the selected bit line after precharging the selected bit line to a predetermined potential; And And storing data according to the state of the selected memory cell in the main latch and outputting an erase verify signal according to the state of the first terminal of the main latch. 10. The method of claim 8, wherein the erase verify signal maintains a floating state when the cell is in an erased state and maintains a low level when the cell is in an erased state.

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