KR100731749B1 - Memory Device Including Nano Insulator And Fabricating Method of The Same, And Organic Electro-luminescence Display Device Using The Same - Google Patents

Abstract

The present invention relates to a memory device having a nano insulator according to the present invention including a high dielectric constant nanoparticles having a higher dielectric constant than an insulating layer made of an organic material, a method for manufacturing the same, and an electroluminescent display device using the same. A memory device having a nano insulator includes a substrate, a first electrode formed on the substrate, an insulating layer formed on the first electrode including a dielectric and a nano insulator having a dielectric constant higher than that of the dielectric, and the insulating layer therebetween. And at least one counter electrode formed on the first electrode and an active layer formed on the counter electrode.

Insulation layer, nano, thin film transistor, capacitor, organic electroluminescent display

Description

Memory Device Including Nano Insulator And Fabricating Method of The Same, And Organic Electro-luminescence Display Device Using The Same}

1 is a cross-sectional view illustrating a memory device in accordance with an embodiment of the present invention.

2 is a view for explaining the structure of the nano insulator included in the insulator.

Figure 3 is a flow chart for explaining the manufacturing procedure of the nano insulator according to the embodiment of the present invention.

4A to 4E are manufacturing process diagrams for explaining a manufacturing process of the nano insulator according to the embodiment of the present invention.

5A to 5H are manufacturing process diagrams for explaining a process of manufacturing a memory device using a nano insulator according to an embodiment of the present invention.

6 is a cross-sectional view illustrating a driving transistor formed in a pixel portion of a organic electroluminescent display device having a high dielectric constant nano insulator and a memory element formed in a portion of a subpixel and a non-pixel portion according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1, 20, 30, 41: substrate 3, 49: gate electrode

5, 25, 32: insulator 7: source electrode

9: drain electrode 11, 25: active layer

13, 33: passivation layer 14: lower electrode

9a: upper electrode 15, 24: nano insulator

17, 23: nano-nuclear 19: coating layer

21: nano insulating material 22: TEOS

31 first electrode 34 second and third electrodes

40: pixel defining layer 42: buffer layer

43 gate insulating film 44 interlayer insulating film

45: passivation film 46: planarization film

47: auxiliary electrode 48: semiconductor active layer

51: via hole 53: lower electrode layer

54: upper electrode layer 55: organic layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, a method for manufacturing the same, and an organic electroluminescent display device, and more particularly, to a memory including a nano insulator having an insulating layer formed by including a high dielectric constant nano insulator having a higher dielectric constant than an organic layer. A device, a method of manufacturing the same, and an organic electroluminescent display using the same.

Recently, semiconductor devices have been used in various fields. Such semiconductor devices continue to be highly integrated and high in performance due to the development of silicon compounds, and are being applied to various fields without being limited to the semiconductor and memory fields.

In particular, the memory device of the semiconductor device is formed of one or more thin film transistors (hereinafter referred to as "TFT") and a capacitor (Capacitor) pair using an insulating layer made of an inorganic material such as SiO2 or SiNx on the silicon wafer. .

However, the manufacture of a memory device using an insulating layer made of an inorganic material is difficult to planarize the insulating layer due to the characteristics of the inorganic material, high temperature vacuum deposition equipment is required to form the inorganic insulating layer, and the manufacturing process is very complicated. That is, due to difficulties in manufacturing a general semiconductor device, there is a limit in device manufacturing.

In order to solve this problem, the manufacturing ratio of organic TFTs (hereinafter referred to as "OTFTs") using an insulating layer made of organic materials and memory devices using the same has been greatly increased. In addition, the OTFT or the organic memory device has advantages in that the process is simpler and the manufacturing cost is lower than the manufacturing process of the semiconductor device using the insulating layer made of inorganic material. In addition, the OTFT or the organic memory device can be bent or folded, so that the switching device is applied to a liquid crystal display, an organic electroluminescence display, and an active matrix flat panel display. (switching device), a driving device (device), a memory device (memory device) is in the spotlight. At this time, the organic material constituting the insulating layer applied to the organic memory device should have a high dielectric constant, and the chemical resistance, heat resistance, photosensitivity, adhesion and evenness to the chemicals that the organic material is in contact with the manufacturing process of the memory device Various conditions such as surface shape must be met.

In the organic memory device as described above, the insulating layer made of organic material is a necessary material, and in particular, the dielectric constant of the organic material constituting the insulating layer is a very important factor in determining the performance of the organic memory device. In more detail, an insulating layer made of an organic material used for a capacitor among the memory elements increases a charge capacity per unit area, and an insulator used for a TFT, which is a switching element, is related to a threshold voltage of a TFT to adjust a channel depth. There is a direct connection.

In order to secure the dielectric constant of the insulating layer made of organic material, when the OTFT is made of the organic semiconductor pentacene (Pentacence) and the inorganic layer made of inorganic material, the field effect mobility is close to the a-Si TFT with ~ 5cm ² / Vs. Although the results show that the performance of the OTFT using the organic insulating film is less than that of the a-Si TFT. Therefore, the performance of the memory device manufactured by using the OTFT has a problem compared to the inorganic memory device.

Accordingly, it is an object of the present invention to provide a memory device having a nano insulator according to the present invention including a high dielectric constant nanoparticles having a higher dielectric constant than an insulating layer made of an organic material, a method of manufacturing the same, and an electroluminescent display device using the same. .

In order to achieve the above object, a memory device having a nano insulator of the present invention comprises a substrate; A first electrode formed on the substrate; An insulating layer formed on the first electrode including a dielectric and a nano insulator having a dielectric constant higher than that of the dielectric; At least one counter electrode formed on the first electrode with the insulating layer interposed therebetween; An active layer is formed on the counter electrode.

The dielectric material is preferably made of at least one of PVA and PVP.

A transistor region is defined in the substrate, and the counter electrode formed in the transistor region is a source electrode which is a second electrode of the transistor and a drain electrode which is a third electrode, and the first electrode of the transistor region is a gate of the transistor. It is preferable that it is an electrode.

A capacitor region is defined in the substrate, and the first electrode is a lower electrode of the capacitor, and the opposite electrode is an upper electrode of the capacitor.

The nano insulator preferably includes a nano nucleus and a coating layer outside the nano nucleus, and the nano nucleus is made of SiO ₂ , and the coating layer is formed of TiO ₂ , HfO ₂ , Al ₂ O ₃ , ZrO ₂ , La ₂ O. ₃ , Ta ₂ O ₅ , SrTiO ₃ , BaTiO ₃ , Pr ₂ O _{3 It} may be made of at least one.

A protective film layer may be further provided to cover the second electrode, the third electrode, the active layer, and the insulator.

In addition, the method of manufacturing a memory device having a nano insulator of the present invention comprises the steps of forming a first electrode; Forming an insulating layer by applying a dielectric including the nano insulator on the first electrode; Forming an opposite electrode on the insulating layer.

The dielectric including the nano insulator may include applying a nano insulation material, applying a nucleation material to the nano insulation material to form a nano nucleus, and coating the nano nucleus to form a nano insulator. It can be formed by.

The forming of the insulating layer may further include a dispersion degree adjusting step of applying a hydrophilic material or a hydrophobic material to the nano insulator in order to control the degree of dispersion of the nano insulator in the insulating layer.

The forming of the nanonucleus may use vapor deposition including chemical vapor deposition (CVD) or atomic layer deposition (ALD).

In addition, the organic electroluminescent display device using the memory device with a nano insulator of the present invention is a substrate; A light emitting element formed in the pixel region of the substrate; A first electrode formed in the pixel region or a non-pixel region other than the pixel region for driving the light emitting element; An insulating layer formed on the first electrode including a dielectric and a nano insulator having a dielectric constant higher than that of the dielectric; At least one counter electrode formed on the first electrode with the insulating layer interposed therebetween; A memory device having an active layer formed on the counter electrode is provided.

Other features and operations of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 8.

1 is a cross-sectional view illustrating a memory device according to an exemplary embodiment of the present invention, and illustrates a basic unit of a memory device constituted by one thin film transistor and one capacitor.

Referring to FIG. 1, a memory device having a high dielectric constant nano insulator according to the present invention includes a substrate 1, first electrodes 3 and 14, counter electrodes 7 and 9, an insulating layer 5, and an active layer 11. ) And preferably a passivation layer (13).

In more detail, the memory device is divided into a TR region in which a thin film transistor TR is formed and a CAP region in which a capacitor is formed.

First, the TR region is insulated from the insulating layer 5 formed so as to cover the first electrode, that is, the gate electrode 3 and the first electrode 3 formed on the substrate 1 such as glass or plastic. The counter electrodes 7 and 9 formed on the layer 5, the insulating layer 5, the active layer 11 formed to cover the counter electrodes 7 and 9, and the counter electrodes 7 and 9 and the insulating layer ( 5) and a passivation layer 13 formed on the active layer 11. Here, the first electrode 3 is a gate electrode of the thin film transistor, and the counter electrode is composed of a source electrode and a drain electrode as the second and third electrodes.

The insulating layer 5 is formed using one of polyvinyl alcohol (PVA), polyvinyl pyrrolidone (PVP), and equivalents thereof, and includes a high dielectric constant nano insulator 15. The insulating layer 5 is a threshold voltage for determining the flow of current between the first electrode 3 and the second and third electrodes 7 and 9 of the first to third electrodes 3 and 7, 9. It plays an important role in determining the, and the higher the dielectric constant of the insulating layer 5, the lower the threshold voltage. That is, when the dielectric constant of the insulating layer 5 is high, a large amount of holes or positive charges are induced when a voltage is applied to the first electrode 3, and the channel depth of the thin film transistor is deepened. That is, the threshold voltage is lowered, the effective voltage related to the actual current flow is widened to form a thinner and thinner than the conventional thin film transistor, or more current can flow through the thin film transistor.

Here, although the upper region of the upper electrode and the lower one electrode is represented in the TR region, the basic principles of the structure of the upper first electrode and the lower two electrodes are the same, and thus the description thereof will be omitted.

The CAP region is formed between the first electrode 14, that is, the lower electrode 14 and the second electrode 9a, that is, the upper electrode 9a, and the first electrode 14 and the second electrode 9a. It consists of the passivation layer 13 formed in the form which surrounds the insulating layer 5 and the 2nd electrode 9a, the exposed part of the insulating layer 5, and the 1st electrode 14. As shown in FIG.

The second electrode 9a is supplied with a voltage for charging the capacitor according to the thin film transistor on / off of the TR region, or provides a flow path of the voltage charged in the cap. Similarly, the first electrode 14 is connected to a ground power source, a power line, and other circuits to provide a path through charge and discharge of voltage. In particular, the insulating layer 5 in the CAP region, as already known, plays an important role in determining the charge capacity of the capacitor.

Where C ₀ is the charge capacity, Q is the charge amount, V is the voltage, A is the area of the upper and lower electrodes, d is the distance between the upper and lower electrodes, and E ₀ is the permittivity.

Equation 1 is the most basic formula for defining the capacity of a capacitor, which is common knowledge known to those skilled in the art or anyone with some knowledge of related systems. As can be seen from this equation (1). The charging capacity C ₀ is proportional to the dielectric constant E ₀ . That is, when the width and distance of the first electrode 14 and the second electrode 9a are constant, the higher the dielectric constant of the insulating layer 5, the greater the amount of electricity can be charged.

To this end, in the present invention, a high dielectric constant is realized by forming a nano insulator 15 having a higher dielectric constant than the insulating layer 5 in the insulating layer 5.

2 is a view for explaining the structure of the nano insulator included in the insulating layer (5).

Referring to FIG. 2, the nano insulator 15 according to the present invention is composed of a nano nucleus 17 and a coating layer 19. The nano insulator 15 applies a nano insulation material, that is, a SiO ₂ material, to a substrate, and the like, using a coating material including TEOS (Tetraethly Orthosilicate), water (H ₂ O), and equivalents thereof, such as a nano nucleus 17. Transform into particles. Once the nano nucleus 17 is formed, the SiO ₂ particles, ie, the nano nucleus 17 are uniformed by using a vapor deposition method such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Will be coated. In this case, a material such as TiO ₂ , HfO ₂ , Al ₂ O ₃ , ZrO ₂ , La ₂ O ₃ , Ta ₂ O ₅ , SrTiO ₃ , BaTiO ₃ , Pr ₂ O ₃ may be used as the coating material. The formed nano insulator 15 has a diameter of the nano nucleus 17 of several tens of nanometers (nm) to several hundred nanometers (nm), and the coating layer 19 has a thickness of several nanometers (nm) to several tens of nanometers (nm). It is formed to have.

In addition, when the nano insulator 15 is completed, surface treatment is performed using hydrophilic or hydrophobic materials on the completed nano insulator 15, and the degree of dispersion in the insulator is adjusted using the nano insulator 15.

As described above, when the memory device is fabricated using the insulating layer made of the nano insulator 15 and the organic material, it has the advantages of the organic semiconductor and the field effect mobility similar to that of the inorganic semiconductor. That is, the memory device can be manufactured at a low cost, and the device used for the flat panel display device that needs to be bent can be manufactured.

3 is a flowchart illustrating a manufacturing procedure of the nano insulator according to the embodiment of the present invention.

Referring to FIG. 3, in a first step S1, a nano insulating material for forming nano insulating particles is coated in a work space. Here, the nano-insulating material is preferably applied in a very thin film form in order to form nano-insulating particles.

After the nano-insulating material is applied, in the second step S2, TEOS and H ₂ O are added to the applied nano-insulating material to form the nano-insulating material into nano-nucleus particles.

When the nanonucleus is formed, TiO ₂ , HfO ₂ , Al ₂ O ₃ , ZrO ₂ , La ₂ O ₃ , Ta ₂ O ₅ , SrTiO ₃ , BaTiO ₃ , Pr using the vapor phase deposition method in the third step (S3). _A material such as ₂ O ₃ is coated on the nanonucleus to form a nano insulator. Here, the coating layer is subjected to hydrophilic treatment or hydrophobic treatment to control the degree of dispersion, and is formed so that the nano insulating particles can be stably included in the holding insulating layer.

After the nano insulator is formed, a hydrophilic material or a hydrophobic material is coated on the nano insulator in the fourth step S4 to adjust the degree of dispersion of the nano insulator. Dispersion control of the nano insulator is to ensure uniform performance of the unit memory device or the overall memory device, and is performed to solve the unbalance of dielectric constant due to the concentration of the nano insulator. This hydrophobic or hydrophilic treatment can be carried out after including the nano insulator in the insulating layer, which is a part depending on the process characteristics, the process sequence can be somewhat fluid.

4 is a manufacturing process chart for explaining a manufacturing process of the nano insulator according to the embodiment of the present invention.

Referring to FIG. 4, as shown in FIG. 4A, a nano insulating material 21 for forming a nano insulator 15 is coated on a substrate or a container 20 for a process.

After applying the nano-insulating material 21, as shown in Figure 4b, by reacting TEOS and water 22 to the nano-insulating material 21, the nano-insulating material 21 is granulated as shown in FIG. 23).

When the nanonucleus 23 is formed, a coating layer is formed on the nanonucleus 23 through vapor deposition as shown in FIGS. 4C and 4D to complete the nano insulator 24.

When the nano insulator 24 is completed, the degree of dispersion of the nano insulator 24 is adjusted by hydrophilic or hydrophobic treatment to uniformly distribute the nano insulator 24.

5A through 5H are manufacturing process diagrams for describing a process of manufacturing a memory device using a nano insulator according to an embodiment of the present invention.

Referring to FIG. 5, first, as shown in FIG. 5A, a conductive layer 31a for forming a lower electrode (or a first electrode) is formed on a substrate 30 such as glass or plastic on which a memory element is to be formed. After the conductive film 31a is formed, the first electrode 31 is formed by patterning the conductive film 31a as shown in FIGS. 5B and 5C.

When the first electrode is formed, an insulating layer 32 having a nano insulator is formed to cover the substrate 30 and the first electrode 31 as shown in FIG. 5D. Here, when separating the insulating layer 32 of the TR region and the Cap region, the method may further include patterning the insulating layer 32 and forming a passivation layer between the insulating layer 32.

When the insulating layer 32 is formed, the conductive layer 34a for forming the upper electrode (or the second electrode) is formed on the insulating layer 32 as shown in FIG. 5E and patterned, thereby forming the second layer as shown in FIG. 5F. The electrode 34 is formed.

After forming the second electrode 34, the active layer 35 is formed on the insulating layer 32 and the second electrode 34 in the TR region as shown in FIG. 5G, and the passivation layer is coated on the entire surface as shown in FIG. 5H. Complete the memory device.

The manufacturing method of the memory device described with reference to FIG. 5 is just an example, and it is natural that the manufacturing method is different according to the structure and characteristics of the memory device. It will be appreciated that the technical concept of the present invention is not applied only to the structure of the memory device mentioned through the embodiments, unless all of these examples are described.

6 is a cross-sectional view illustrating a portion of a driving transistor and a subpixel formed in a display portion of an organic electroluminescent display using an insulating layer having a nano insulator according to an embodiment of the present invention, and a memory element formed in a non-pixel portion. .

Referring to FIG. 6, an organic electroluminescent display has a plurality of pixels and a plurality of subpixels constituting one pixel. A single subpixel is surrounded by a scan line, a data line, and a power line Vdd. Each subpixel basically includes a switching transistor TFTsw for switching and a driving transistor TFTdr for driving. At least two thin film transistors, one capacitor Cst, and one organic electroluminescent element OLED. The number of such transistors and capacitors is not necessarily limited thereto, and may include a greater number of transistors and capacitors.

As shown in FIG. 6, in the subpixel and the driving transistor TFTdr of the organic electroluminescent display, a buffer layer 42 is formed on a first substrate 41 made of glass, plastic, or the like, and a thin film transistor TFT is formed thereon. ) And an organic electroluminescent element (OLED) are formed.

The semiconductor active layer 48 of a predetermined pattern is formed on the buffer layer 42 of the substrate 41. A gate insulating film 43 is formed on the semiconductor active layer 48 using SiO ₂ , and a gate electrode 49 is formed on the gate insulating film 43 as a conductive film. In addition, the gate electrode 49 is connected to a gate line (not shown) for applying an on / off signal of the thin film transistor. An inter dielectric layer 44 is formed on the gate electrode 43, and the source / drain electrode 50 contacts the source region and the drain region of the semiconductor active layer 121 through contact holes. Is formed. A passivation film 45 made of SiO ₂ , SiNx, or the like is formed on the source / drain electrode 50, and a planarization film is formed on the passivation film 45 by an organic material such as acrylic, polyimide, BCB, or the like. 46 is formed.

In the passivation film 45 and the planarization film 46, a via hole 51 is formed in the passivation film 45 and the planarization film 46 to the source / drain electrode 50 by a photolithography method or perforation, whereby the lower electrode layer 53 forms the source / drain electrode 50. Is electrically connected). Subsequently, a pixel defined layer 40 is formed of an organic material to cover the lower electrode layer 53. After the predetermined opening is formed in the pixel defining layer 40, the organic layer 55 including the light emitting layer is formed in the region defined by the opening. And the upper electrode layer 54 which is a cathode electrode is formed so that this organic layer 55 may be covered. The organic layer 55 emits light by the injection of holes and electrons at opposite portions of the lower electrode layer 53 and the upper electrode layer 54.

In particular, the gate insulating film 43 and the semiconductor active layer 48 are formed using an insulator having a nano insulator.

As described above, the memory device having the nano-insulator according to the present invention, the manufacturing method thereof, and the electroluminescent display device using the same have a higher dielectric constant than the conventional one, while maintaining the advantages of the organic layer when the organic layer is used. It is possible to have

Accordingly, the memory device having the nano-insulator according to the present invention, a method of manufacturing the same, and an electroluminescent display device using the same according to the present invention have a conventional memory device or electroluminescence due to a smaller size or a larger capacity than the same size. It is possible to provide significantly improved performance over the display device.

In addition, a memory device having a nano insulator according to the present invention, a method of manufacturing the same, and an electroluminescent display device using the same may be controlled by effectively adjusting the dielectric constant of an insulating layer made of an organic material through dispersion of the nano insulator and selection of materials and coating materials. It is easier to obtain a dielectric constant, which provides an advantage of easier fabrication of memory devices and organic electroluminescent displays.

In addition, the memory device having a nano insulator according to the present invention, a method for manufacturing the same, and an electroluminescent display device using the same according to the present invention reduce the power consumption by lowering the threshold voltage by using an insulator having a high dielectric constant nano insulator, the effective voltage range Increasing the amount of flow current provides the advantage of allowing easy control and operation of memory and organic EL and display devices.

Claims (20)

A substrate; A first electrode formed on the substrate; An insulating layer formed on the first electrode including a dielectric and a nano insulator having a dielectric constant higher than that of the dielectric; At least one counter electrode formed on the first electrode with the insulating layer interposed therebetween; And an active layer formed on the counter electrode. The method of claim 1, The dielectric is a memory device having a nano insulator, characterized in that consisting of any one or a plurality of PVA and PVP. The method of claim 1, The substrate defines a transistor region, The counter electrode formed in the transistor region is a source electrode which is a second electrode of the transistor and a drain electrode which is a third electrode, And the first electrode of the transistor region is a gate electrode of the transistor. The method of claim 3, wherein The substrate defines a capacitor region, The first electrode is a lower electrode of the capacitor, The counter electrode is a memory device having a nano insulator, characterized in that the upper electrode of the capacitor. The method of claim 1, The nano insulator comprises a nano nucleus and a coating layer outside the nano nucleus. The method of claim 5, The nanonuclear memory device having a nano insulator, characterized in that made of SiO ₂ . The method of claim 5, The coating layer is any one or a plurality of nano insulators comprising TiO ₂ , HfO ₂ , Al ₂ O ₃ , ZrO ₂ , La ₂ O ₃ , Ta ₂ O ₅ , SrTiO ₃ , BaTiO ₃ , Pr ₂ O ₃ Memory device having a. The method according to any one of claims 1 to 3, The memory device, And a protective film layer formed to cover the second electrode, the third electrode, the active layer, and the insulator. Forming a first electrode; Forming an insulating layer by applying a dielectric including the nano insulator on the first electrode; A method of manufacturing a memory device having a nano insulator, the method comprising forming a counter electrode on the insulating layer. The method of claim 9, The dielectric including the nano insulator, Applying a nano insulating material, Forming a nano nucleus by applying a nucleating material to the nano insulating material; The method of manufacturing a memory device having a nano insulator, characterized in that formed by coating the nano-nucleus to form a nano insulator. The method of claim 10, Forming the insulating layer, In order to control the degree of dispersion of the nano insulator in the insulating layer of the memory device having a nano insulator, characterized in that it further comprises a dispersion degree adjusting step of applying a hydrophilic material or a hydrophobic material to the nano insulator Manufacturing method. The method of claim 11, The nano-nucleus is coated by any one or a plurality of TiO ₂ , HfO ₂ , Al ₂ O ₃ , ZrO ₂ , La ₂ O ₃ , Ta ₂ O ₅ , SrTiO ₃ , BaTiO ₃ , Pr ₂ O ₃ The manufacturing method of the memory element provided with the nano insulator made into it. The method of claim 10, Forming the nano-nucleus, the method of manufacturing a memory device having a nano insulator, characterized in that using vapor deposition including chemical vapor deposition (CVD) or atomic layer deposition (ALD). A substrate; A light emitting element formed in the pixel region of the substrate; An insulating layer formed on the first electrode including a first electrode formed in the pixel region or a non-pixel region other than the pixel region for driving the light emitting device, and a dielectric and a nano insulator having a dielectric constant higher than that of the dielectric. And a memory device having at least one counter electrode formed on the first electrode with the insulating layer interposed therebetween and an active layer formed on the counter electrode. Organic electroluminescent display. The method of claim 13, The nano insulator includes a nano nucleus made of SiO ₂ , and a coating layer surrounding the outside of the nano nucleus, and an organic electroluminescent display device using a memory device having a nano insulator having a nano insulator. The method of claim 15, The nano insulator may be coated by any one or more of TiO ₂ , HfO ₂ , Al ₂ O ₃ , ZrO ₂ , La ₂ O ₃ , Ta ₂ O ₅ , SrTiO ₃ , BaTiO ₃ , Pr ₂ O ₃ . An organic electroluminescent display device using a memory device with a nano insulator. The method according to any one of claims 14 to 16, The semiconductor device is an organic electroluminescence display using a memory device with a nano insulator, further comprising a thin film transistor further comprising a third electrode formed on the first electrode with the insulator interposed therebetween. The method of claim 17, A gate insulating film formed between the first electrode and the substrate; An interlayer insulating film formed to cover the gate insulating film and the first electrode; Further comprising a semiconductor active layer formed between the gate insulating film and the substrate, And at least one of the gate insulating film, the interlayer insulating film, and the semiconductor active layer is formed using the nano insulator insulating layer. The method of claim 18, And the gate insulating film, the interlayer insulating film, or the semiconductor active layer formed by the nano insulator insulating layer is limited to a portion near or above the gate electrode. The method according to any one of claims 14 to 16, The semiconductor device is an organic electroluminescent display using a memory device with a nano insulator, characterized in that the capacitor.

Images