KR100731157B1 - Single-conversion integrated circuit TV tuner - Google Patents

Abstract

The single conversion integrated circuit TV tuner includes a first filter coupled to the RF signal input, and a harmonic rejection mixer coupled to the real output of the first filter. The harmonic rejection mixer has a complex output. The TV tuner further includes a polyphase filter having a complex input coupled to the complex output of the harmonic rejection mixer. Only the real signal is passed from the first filter to the harmonic rejection mixer.

Description

Single-conversion integrated circuit TV tuner

1 is a block diagram of a TV tuner circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of the selectable band pass filter of FIG. 1.

3 is a block diagram of a TV tuner circuit according to a second embodiment of the present invention.

4 is a block diagram of the digital control tracking filter of FIG.

5 is a block diagram of an application of a TV tuner in accordance with the present invention.

The present invention relates to a TV tuner, and more particularly to an integrated circuit TV tuner for single or direct frequency conversion of an RF signal.

Broadband tuners are used in a variety of consumer and commercial systems, such as TVs, VCRs, and more sophisticated devices, including cable modems and cable set-top-boxes.

Functioning as the RF front-end of the wideband signals, the tuner is responsible for receiving all available channels, selecting the desired channel and filtering others. These tuners typically operate in the frequency range of 40 to 900 MHz, and thus have different performance requirements than typical TV tuners. For these tuners, a frequency conversion architecture is essential for the tuner design.

The World Intellectual Property Organization (WIPO) Publication No. WO 02/093732, incorporated herein by reference, describes the latest integrated TV tuner. This type of TV tuner uses double conversion and thus includes two polyphase filters and two mixers.

Another example of an integrated TV tuner has been developed by PHILLIPS. The TDA 8275 silicon IC tuner provides a low Intermediate Frequency (IF) signal for later decoder devices, but relies on a proprietary architecture to do so. That is, universally available decoders or demodulators cannot be used with the TDA 8275.

The main object of the present invention is to provide a single-conversion integrated circuit TV tuner for solving the above problems.

In summary, the present invention includes a first filter coupled to an RF signal input, and a harmonic rejection mixer coupled to a real output of the first filter. Only real signals are passed to the harmonic rejection mixer. The harmonic rejection mixer has a complex output. The invention further includes a polyphase filter having a complex input directly connected to the complex output of the harmonic rejection mixer.

It is a feature of the present invention that a single or direct conversion is performed.

It is a feature of the present invention that off-the-shelf decoders or demodulators can be used.

It is a feature of the present invention that all of the actual components can be placed on one silicon chip.

Other objects of the present invention will become apparent to those skilled in the art after reading the detailed description of the preferred embodiment described in the following various figures and figures.

Although the present invention has been described in connection with terrestrial TV tuners, the present invention can also be applied to other TV tuner applications such as cable TV, set-top-boxes, and digital TV. Moreover, the present invention can be applied to a system using a signal ring such as that of a TV. The present invention provides an on-chip solution for single or direct frequency conversion. The present invention converts TV signals of typical frequencies into programmable intermediate frequencies (IFs) that are compatible with the most commonly available demodulators or decoders.

First Example

1 shows a block diagram of a TV tuner circuit 100 according to the first embodiment of the present invention. The TV tuner circuit 100 is connected to the external antenna 101 at the RF signal input. The circuit 100 includes a low-noise variable-gain amplifier (LNA) 102 coupled to a selectable band-pass filter 103. Selectable band-pass filter 103 is connected to a harmonic rejection mixer 105 having a complex output. The term “complex” is then used to refer to any connection or signal having in-phase (I) and quadrature-phase (Q) components. Next to the harmonic rejection mixer 105 is an IF polyphase filter 106 connected to the Surface Acoustic Wave (SAW) driver 107. The TV tuner circuit 100 is also connected to the mixer 105 and has a frequency divider 108 (e.g., divided by four) with an output of six phases, and a crystal oscillator. It is connected to a reference frequency from 122 and to a Fractional N-Phase Locked Loop (FNPLL) connected to an external loop filter 120. Logic control 111 is provided on the chip to control the selection functions of the TV tuner circuit 100 in accordance with the serial input. Components 102-109 of the TV tuner circuit 100 are disposed on the same silicon chip, while the external antenna 101 and the loop filter 120 do not.

Antenna 101 provides a wideband RF TV signal to amplifier 102. Next, following the band-pass filter 103, a narrowband signal arrives at the mixer 105. In the mixer 105, a relatively narrowband real band RF signal is mixed with the LO signals (0, 45, 90 degrees) output by the frequency divider 108 to generate an I-IF signal, and Q-IF It is mixed with the signals 90, 135, 180 degrees output by the frequency divider 108 to produce a signal. The LO signals have a resolution of approximately 1/8 phase (eg 45 degrees) to synthesize the mixed LO I / Q signals. The mixed signals output from the mixer 150 are combined in the IF polyphase filter 106 and the SAW driver 107 is made available to off-chip devices such as the IF SAW filter. Is passed to.

The low-noise variable gain amplifier (LNA) 102 should be able to handle wideband signals that are common in TV applications. The low-noise variable gain amplifier (LNA) 102 must have sufficient dynamic range to comply with other levels of input signal, such as those found in standard TV signals. Moreover, the amplifier 102 must have relatively constant noise, while maintaining a substantially constant output level, while providing wideband matching.

The integrated selectable band-pass filter 103 limits the number of channels loading the mixer 105. Thus, band-pass filter 103 relaxes the linearity requirement for the rest 105-107 of the signal chain. In addition, the band-pass filter 103 attenuates undesirable signals at image frequencies due to harmonics of LO frequencies. The RF inputs can be separated into multiple sections and are selected by a band select control signal on request. The gain and corner frequencies for the integrated selectable band-pass filter 103 are programmed by either users or internal calibration circuits. This offers another advantage over the prior art.

2 describes an embodiment of a band-pass filter 103. The RF input into band-pass filter 103 is separated into five components that can be selected by a "select" input. The selectable components are certain frequency ranges that depend on the particular application. Equivalently, the RF input to the band-pass filter 103 is composed of three components: high frequency (HF), band-pass frequency (BPF), low frequency (LF), or It can be separated into any other components. These types of band-pass filters are examples, and other known band-pass filters may also be used in the TV tuner circuit 100.

The band-pass filter 103 may be implemented with inductance and / or capacitance, and may be on-chip or off-chip depending on specific conditions.

Harmonic rejection mixer 105 includes double quadrature mixers with three phases for I and three phases for Q, which eliminate third and fifth order LO harmonics. do. Mixer 105 receives the RF inputs and the LO inputs. When the third order LO harmonics are outside the input spectrum, the mixer 105 may be converted to a conventional dual quadrature mixer. Such switching is done using only a single phase LO for either the I or Q LO signals. In a preferred embodiment, the harmonic rejection mixer 105 is directly connected to an integrated selectable band-pass filter 103 and receives only real (phase I) signals at this input. This direct connection and lack of interference of the polyphase filter is another advantage of the present invention over the prior art.

The IF polyphase filter 106 suppresses negative frequencies in the IF signal output by the harmonic rejection mixer 105. An IF tune control input can be used to control the IF polyphase filter 106. IF polyphase filter 106 may have a center frequency of approximately 30-60 MHz to match SAW filters commonly available for US TV applications. Different applications may have different center frequencies.

The SAW driver 107 may be selected to linearly drive a particular external SAW filter and should have a frequency such as 44 MHz for US standard linearity. For variety of applications, the SAW driver 107 must be compatible with off-the-shelf SAW filters.

FNPLL 109 includes a frequency synthesizer having fractional selection and synthesizing LO frequencies for channel selection with respect to signal chains 102-107. Voltage-controlled oscillators (VCOs) of the FNPLL 109 may include integrated spiral inductors and varactors. With integrated helical inductors, the VCO can eliminate off-chip inductors and package bond wire inductors. Thus, any variations associated with such inductors can be reduced. In addition, by programming the FNPLL 109, it allows the selection of high or low IF (depending on design requirements) at the output of the SAW driver 107, which is a significant improvement over the prior art devices, This is especially true for devices with on-chip SAW filters that can only output low IFs. Other commonly known types of PLLs or (eg, non-helical) inductors are also acceptable for use in the TV tuner circuit 100.

The first embodiment can achieve a higher level of integration compared to the prior art. A single (direct) conversion high-IF architecture has substantially reduced complexity and production costs. In addition, the choice of high-IF architecture has reduced the size of on-chip components (eg, resistors and capacitors), thus reducing die size. Moreover, the choice of low-IF architecture is also possible. In addition, this embodiment is compatible with commercially available demodulators (decoders) and off-chip SAW filters. Considering overall performance, it is desirable to use an off-chip IF SAW filter for band selection because of its excellent filtering characteristics. In terms of price and performance, a single conversion to the high IF architecture of the present invention is a good compromise.

2nd Example

3, a block diagram of a TV tuner circuit 300 fully integrated in accordance with a second embodiment of the present invention is shown. The TV tuner circuit 300 uses a front-end digitally control tracking filter that uses on-chip varactors or the like.

The TV tuner circuit 300 is connected to the external antenna 301 at the RF signal input. The circuit 300 includes a digitally-controlled tracking filter 302 coupled to a low-noise variable-gain amplifier 303. The amplifier 303 is coupled to a harmonic rejection mixer 305 having a complex output. Similar to the first embodiment, the harmonic rejection mixer 305 is followed by an IF polyphase filter 306 coupled to the SAW driver 307. The TV tuner circuit 300 is connected to the mixer 305 and has a frequency divider 308 (e.g., divided by four) with an output of six phases, and an external low-pass. It further includes a low pass filter (LPF) 320 and a PLL 309 coupled to a reference frequency. The PLL 309 includes a voltage-controlled oscillator (VCO) 310, a charge pump (CP) 311, and a phase detector (PD) 312. PLL 309 is coupled to tracking filter 302 such that a control signal of PLL 309 is provided to tracking filter 302. Components 302-312 of the TV tuner circuit 300 are disposed on the same silicon chip, while the external antenna 301 and low pass filter 320 are not.

Antenna 301 provides a wideband RF TV signal to digital-controlled tracking filter 302, which passes through low-noise variable-gain amplifier 303. Next, a narrowband signal arrives at the mixer 305. In the mixer 305, the relatively narrowband real RF signal generates the LO signals (0, 45, 90 degrees) and the Q-IF signal output by the frequency divider 308 to generate the I-IF signal. To the LO signals 90, 135, 180 degrees output by the frequency divider 308. LO signals have approximately 1/8 phase (eg 45 degrees) resolution to synthesize a mixed LO I / Q signal. As in the first embodiment, the mixed signals output from the mixer 305 are combined in an IF polyphase filter 306 and applied to off-chip devices such as an IF SAW filter. It is passed to the SAW driver 307 to make it available.

Digitally-controlled tracking filter 302 is located at the front end of this architecture to provide early channel selection. The tracking filter 302 accepts a digital control code derived from the VCO 310 varactor bank digital code. Thus, the input power to the next low noise amplifier 303 is reduced. As a result, in the entire signal chain 302-307, linear conditions and power consumption are significantly reduced. If the tracking filter 302 is sharp enough, it is not necessary to use the mixer 305 and may be replaced with a suitable image removal mixer. 4 shows details of an embodiment of a digitally-controlled tracking filter 302.

4 shows details of an embodiment of a digitally-controlled tracking filter 302. Tracking filter 302 includes two digitally-adjustable variable capacitances C1 and C2 that can be implemented with varactors, varicaps, or similar elements. Inductance L1 is present between capacitance C1 and antenna 301. Inductance L2 is between two capacitances C1 and C2 and is off-chip grounded. Inductances L1 and L2 may be either chip-bonding wires or a combination of bonding wires and off-chip inductors. The tracking filter 302 further includes an amplifier 401 provided at the output of the variable capacitances C1, C2. (Note: In the following equations and in Figure 4, similar variables, for example Zin = Z _in , are the same despite the subscript)

라고 가정하자. 따라서 (L1, C1) 및 (L2, C2)가 동조 주파수에서 설정되고, 입력 저항 Rin을 (도 4에서 도시된 바와 같이) 가정할 때

이다. 따라서,

이다.Referring to FIG. 4, when tuned under matching conditions, for example, when the power supply impedance Zs is approximately equal to the input impedance Zin, the tuned frequency is

Suppose Thus, when (L1, C1) and (L2, C2) are set at the tuning frequency, assuming the input resistance Rin (as shown in Fig. 4).

to be. therefore,

to be.

이므로, Zin=Rin이다.

Since Zin = Rin.

Thus, if the input resistance Rin is set equal to the power supply impedance Zs, the input network can match the tuning frequency.

Referring again to FIG. 3, the low-noise variable-gain amplifier 303 should be able to process the input signals with low noise contribution and low power consumption. It should have sufficient dynamic range to adjust the input signal at other levels, such as those of standard terrestrial TV signals.

As in the first embodiment, the harmonic rejection mixer 305 includes dual quadrature mixers with three phases for I and three phases for Q that reject third and fifth order LO harmonics. The mixer 305 receives RF inputs and LO inputs. Preferably, the mixer 305 can be selected for low-side mixing and converted to a conventional dual-quadrant mixer when the third order LO harmonics are outside the input spectrum. . Such conversion can be done by using only one phase LO for either the I or Q LO signals.

PLL 309 provides frequency synthesis with fractional selection, which provides channel selection for the signal chain. The VCO 310 of the PLL 309 may include integrated spiral inductors and varactors. The digital control signal (n-bit) of the VCO 310 is applied to the front end of the tracking filter 302. As mentioned, the frequency divider 308 divides the output of the PLL by four, so the PLL 309 operates at about four times the LO frequency. In addition, other known types of PLLs or (eg, non-helical) inductors may also be accommodated for use in the TV tuner circuit 300.

This second embodiment can achieve a higher level of integration compared to the prior art. By integrating the on-chip digital control tracking filter into a single high-IF conversion architecture, its power consumption as well as the linear conditions for the rest of the signal chain are substantially reduced. In addition, this embodiment is compatible with commercially available demodulators (decoders) and off-chip SAW filters.

General Considerations

The first and second embodiments use similar components and thus have similar advantages. In addition, many specific elements of one embodiment may be used in another embodiment. Specifically, as the second embodiment may have a selectable band-pass filter 103 instead of the tracking filter 302, the first embodiment may track the filter 302 instead of the selectable band-pass filter 103. It can have Further, the placement in the respective signal chains of the amplifier 102 and the selectable band pass filter 103 and the tracking filter 302 and the variable-gain amplifier 303 may be reversed. In essence, FNPLL 109 and PLL 309 may be used in any embodiment depending on requirements.

5 shows an application of a TV tour 500 in accordance with the present invention. The TV tuner 500 may be a TV tuner 100 or 300. Antenna 501 provides a universal TV signal to TV tuner 500. After a single or direct frequency conversion and processing as described in the above embodiments, the TV tuner 500 outputs the IF signal to the demodulator (or decoder) 550 and demodulator (or decoder) 550. Outputs the demodulated (decoded) signal to display hardware 560. Control of the TV tuner 500 is via a control signal 540, which may include channel selection.

1-5 are schematic diagrams illustrating elements and connections associated with the present invention. Elements not relevant to the present invention have been omitted for the sake of brevity, and the elements shown may be generally connected in ways other than as described. In addition, many of the circuit symbols used are already known, such that the elements represented by the symbols themselves perform well known functions.

Those skilled in the art will appreciate that many variations and modifications can be made while maintaining the teachings of the present invention. Accordingly, what is disclosed above should be construed as limited only by the limitations and boundaries of the appended claims.

As described above, by providing a single-conversion integrated circuit TV tuner according to the present invention, a single or direct conversion can be performed, and there is an effect that off-the-shelf decoders or demodulators can be used.

It also has the advantage that all actual components can be placed on one silicon chip.

Claims (16)

In a single-conversion integrated circuit TV tuner, The single-conversion integrated circuit TV tuner, A first filter coupled to the RF signal input; A harmonic rejection mixer having a real input coupled to the real output of the first filter, and a complex output; And A polyphase filter having a complex input coupled to the complex output of the harmonic rejection mixer, A single-conversion integrated circuit TV tuner, wherein only a real signal is passed from the first filter to the harmonic rejection mixer. 2. The single-conversion integrated circuit TV tuner of claim 1, wherein the first filter is a selectable band-pass filter and directly connected to the harmonic rejection mixer. The method of claim 2, The single-conversion integrated circuit TV tuner, And a variable-gain amplifier coupled between the RF signal input and the selectable band-pass filter. 2. The single-conversion integrated circuit TV tuner of claim 1, wherein the first filter is a digitally controlled tracking filter. The method of claim 4, wherein The single-conversion integrated circuit TV tuner, And a variable-gain amplifier directly connected to said digitally-controlled tracking filter and directly connected to said harmonic rejection mixer. 5. The single-conversion integrated circuit TV tuner of claim 4, wherein the digitally-controlled tracking filter comprises at least two variable capacitances connected in series. 7. The single-conversion integrated circuit TV tuner of claim 6, wherein the variable capacitance comprises a varactor. 7. The digitally controlled tracking filter of claim 6, further comprising a first inductance coupled in series between the RF signal input and the variable capacitances, and a second inductance coupled between the variable capacitances and the ground input. Single-conversion integrated circuit TV tuner. 7. The single-conversion integrated circuit TV of claim 6, wherein the digitally-controlled tracking filter further comprises an amplifier connected in series with the two variable capacitances and connected to a rear end of the two variable capacitances. Tuner. The method of claim 1, The single-conversion integrated circuit TV tuner, And a amplifier coupled between the polyphase filter and the signal output. The method of claim 1, The single-conversion integrated circuit TV tuner, And a local oscillator circuit coupled to the harmonic rejection mixer. 12. The apparatus of claim 11, wherein the local oscillator circuit comprises a phase-locked loop, and a frequency divider, wherein the frequency divider is connected between the phase locked loop and the harmonic rejection mixer to output five output phases. A single-conversion integrated circuit TV tuner, characterized in that it is provided to a harmonic rejection mixer. The single-conversion integrated circuit TV tuner of claim 1, wherein the first filter, the harmonic rejection mixer, and the polyphase filter are disposed on one silicon chip. In a single-conversion integrated circuit TV tuner, A first filter coupled to the RF signal input; A harmonic rejection mixer coupled to the output of the first filter, the harmonic rejection mixer having a real input and a complex output, wherein only a real signal is transmitted from the first filter to the harmonic rejection mixer; A polyphase filter having a complex input coupled to the complex output of the harmonic rejection mixer; An amplifier coupled between the polyphase filter and a signal output; And A local oscillator circuit coupled to the harmonic rejection mixer, The local oscillator circuit comprises a phase-locked loop and a frequency divider, the frequency divider being coupled between the phase locked loop and the harmonic rejection mixer to provide five output phases to the harmonic rejection mixer, Wherein said first filter, said harmonic rejection mixer, said polyphase filter, said amplifier, and said local oscillator circuit are disposed on a silicon chip. 15. The system of claim 14, wherein the first filter is a selectable band-pass filter and directly connected to the harmonic rejection mixer, wherein the single-conversion integrated circuit TV tuner is coupled between the RF signal input and the selectable band-pass filter. A single-conversion integrated circuit TV tuner, further comprising a variable-gain amplifier. 15. The apparatus of claim 14, wherein the first filter is a digitally-controlled tracking filter and the single-conversion integrated circuit TV tuner further comprises a variable-gain amplifier connected directly to the digitally controlled tracking filter and the harmonic rejection mixer. Single-conversion integrated circuit TV tuner.

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