KR100728953B1 - Method of manufacturing semiconductor device - Google Patents

Abstract

The present invention discloses a method for manufacturing a semiconductor device. The disclosed method comprises the steps of: providing an SOI substrate comprising a stacked structure of a silicon substrate, an buried oxide film, and a silicon film; forming a gate having a hard mask nitride film thereon on the silicon film of the SOI substrate; Sequentially forming oxide spacers and nitride spacers on both sidewalls of the gate; etching the silicon layer and the buried oxide layer having a certain thickness on both sides of the gate using the nitride spacer and the hard mask nitride layer as etch barriers; Forming a polysilicon spacer on sidewalls of the nitride spacer and the etched silicon film and the buried oxide film, growing an epi silicon film on the buried oxide film portions on both sides of the gate including the polysilicon spacer, and growing the epi silicon film. Source / drain Young by ion implantation of impurities into the film A includes forming. According to the present invention, a parasitic series resistance increase, parasitic capacitance increase phenomenon, and spiking phenomenon are realized by implementing a fully depleted transistor which increases the thickness of the silicon film in the source / drain junction region by using an SOI substrate and epi silicon growth technology. Can be effectively suppressed, and short channel effects such as threshold voltage reduction phenomenon and DIBL effect can be suppressed.

Description

Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

1A, 1B and 2 are cross-sectional views for each process for explaining a method of manufacturing a semiconductor device according to the prior art.

3A to 3E are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

31 silicon substrate 32 buried oxide film

33 silicon film 34 SOI substrate

35 pad oxide film 36 gate insulating film

37: gate conductive film 38: hard mask nitride film

40: gate 41: oxide film spacer

42 nitride film spacer 43 polysilicon film spacer

44 epi silicon film 45 source / drain junction region

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a recessed gate that can improve the reliability of the device.

As the degree of integration of semiconductor devices increases, the channel length of the transistors also becomes very short. As the channel length becomes shorter, so-called short channel effects are generated in which the control ability of the gate is reduced while the charge sharing between the source / drain junction regions increases. Due to the short channel effect, the threshold voltage (Vt) is drastically lowered, and the DBL (Drain Induced Barrier Lowering) effect occurs, causing problems in device operation.

In addition, as the degree of integration of the device increases, excessive ions are implanted in the source / drain formation region, and the depth of the source / drain junction region becomes shallow, thereby increasing the spiking phenomenon and the parasitic series resistance. The same problem occurs. The spiking phenomenon is a phenomenon in which the source / drain junction region does not properly perform its role due to the reaction between the source / drain junction region and the metal material and the silicon film and the metal material in the junction region, and on the other hand, parasitic series resistance The increase phenomenon is a phenomenon in which the resistance of the silicon film itself is increased due to the thin thickness of the silicon film in the junction region. When the parasitic series resistance increases, the actual voltage difference between the source and the drain decreases, thereby increasing the voltage required to drive the device.

In order to prevent such short channel effects, spiking effects, and increased parasitic series resistance, various process technologies have been developed to increase the effective line width of the channel and form a thick silicon film in the source / drain junction region.

As an example, firstly, a recess is formed in a silicon substrate, and a gate is formed on the groove to thicken the silicon film of the source / drain junction region. Second, a gate is formed in the silicon substrate to form a gate. A buried gate formation technique for thickening the silicon film thickness of the junction region while increasing the effective length is mentioned.

Hereinafter, the above-described conventional recess gate formation technique and buried gate formation technique will be briefly described.

1A to 1D are cross-sectional views illustrating processes of manufacturing a semiconductor device according to a conventional recess gate forming technique.

First, as shown in FIG. 1A, the pad oxide film 2 and the pad nitride film 3 are sequentially deposited on the silicon substrate 1, and a part of the pad oxide film 3 is etched, and then a known LOCOS (Local Oxidation) is known. The oxide film 4 is grown in the gate formation region of the substrate 1 through the process.

Next, as shown in FIG. 1B, a portion of the oxide film 4 is recessed and a gate made of a laminated film of the gate conductive film 5 and the hard mask film 6 on the recessed region ( 10) form. Then, the pad nitride layer 3 is removed, and spacers 7 are formed on both side walls of the gate 10.

Then, an ion is implanted into the source / drain predetermined region on both sides of the gate 10 to form the source / drain junction region 11.

Subsequently, although not shown, a series of known subsequent processes are sequentially performed to manufacture the semiconductor device.

2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with a conventional buried gate forming technique.

As shown in FIG. 2, the gate forming region of the silicon substrate 21 is recessed, and the gate 30 formed of a laminated film of the gate insulating film 22 and the gate conductive film 23 is formed on the recess region. To form.

Then, an ion is implanted into the source / drain predetermined region on both sides of the gate 30 to form the source / drain junction region 31.

Next, the partial region of the upper portion of the gate 30 and the partial region of the substrate 21 on both sides of the gate 30 are etched, and a gate protective material layer 24 formed of an oxide film or a nitride film is formed on the etched region. The gate protection material layer 24 not only protects the gate 30 but also serves to separate the junction region between the source and the drain.

Subsequently, although not shown, a series of known subsequent processes are sequentially performed to manufacture the semiconductor device.

However, the former method of the above two conventional techniques, since the step difference between the channel region and the source / drain junction region depends only on the amount of silicon substrate 1 lost during the growth of the oxide film 4 by the LOCOS process, The level difference between the channel region and the source / drain junction region cannot be sufficiently increased. Therefore, there is a limit in reducing parasitic series resistance and spiking phenomenon. In addition, when the oxide film 4 is grown by the LOCOS process, both ends of the oxide film 4 are formed in a bird's beak shape, thereby limiting the gate line width.

In addition, the latter of the two conventional techniques described above is an effective method for increasing the effective line width of the gate, but the parasitic capacitance is common since the overlap area of the gate / insulation film / silicon film is increased on both sides of the gate. The problem arises that at least 50% increase over transistors with planar channel structures. Accordingly, an RC delay effect is exhibited and is disadvantageous for high speed operation device implementation. In particular, since the thickness of the insulating layer 22 at the gate edge is thin, GIDL (Gate Induced Drain Leakage) characteristics are weak, and a strong electric field is formed at the channel edge, thereby increasing hot-carrier generation.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, a depression type gate that can effectively suppress the short-channel effect and at the same time reduce the parasitic series resistance of the source / drain to ensure the reliability of the device Its purpose is to provide a method of manufacturing a semiconductor device having a.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of: providing an SOI substrate consisting of a laminated structure of a silicon substrate, a buried oxide film and a silicon film; Forming a gate having a hard mask nitride layer on the silicon layer of the SOI substrate; Sequentially forming oxide spacers and nitride spacers on both sidewalls of the gate; Etching the silicon film on both sides of the gate and the buried oxide film having a partial thickness by using the hard mask nitride film including the nitride film spacer as an etching barrier; Forming a polysilicon spacer on sidewalls of the nitride spacer and the etched silicon layer and the buried oxide layer; Growing an epitaxial silicon film on portions of the buried oxide film on both sides of the gate including the polysilicon spacer; And forming a source / drain region by implanting impurities into the grown epi silicon film.

Here, the buried oxide film is formed to a thickness of 1500 ~ 2500∼, the silicon film is formed to a thickness of 100 ~ 500Åm.

The etching of the silicon film on both sides of the gate and the buried oxide film having a certain thickness is performed so that the buried oxide film is etched at 500 to 1000 Å.

After etching the silicon film on both sides of the gate and the buried oxide film having a certain thickness, and before forming the polysilicon spacer, p-type impurities are formed in the NMOS formation region of the substrate and n is formed in the PMOS formation region of the substrate. It further includes the step of implanting oblique ion implantation in the unidirectional direction. Herein, the p-type impurity ion implantation may be performed with boron ions having 1E18 to 5E18 ions / cm 3 dose.

The polysilicon spacer is formed to a thickness of 300 to 500 Å, and is formed of a polysilicon film doped with N-type or P-type impurities at a concentration of 1E20 to 5E20 ions / cm 3.

The growing the epi silicon film may include forming a silicon seed film on the etched oxide film, growing an epi silicon film on the silicon seed film, and exposing a hard mask nitride film of the gate. CMP of the epi silicon film.

According to the present invention, a gate is formed on a silicon-on-insulator (SOI) substrate, and the substrate of the predetermined source / drain formation region on both sides of the gate is recessed, and then a polysilicon spacer is formed on sidewalls of the gate and the recessed substrate. And growing an epi silicon film on the source / drain formation regions on both sides of the gate, and ion implanting the grown epi silicon film to form a source / drain junction region, whereby the silicon film of the channel is thin and source / drain. The thickness of the drain silicon film implements a new type of fully depleted transistor with a thick thickness. Accordingly, the short channel effect, parasitic series resistance and spiking phenomenon can be effectively suppressed.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3E are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3A, after the pad nitride film 35 is formed on the SOI substrate 34 having a stacked structure of the silicon substrate 31, the buried oxide film 32, and the silicon film 33, the threshold voltage is adjusted. Ion implantation process is performed.

In the SOI substrate 34, the buried oxide film 32 is formed to a thickness of 1500 to 2500 GPa, and the silicon film 33 is 500 GPa or less on the buried oxide film 32, preferably, 100 to 500 GPa. The SOI substrate 34 formed in thickness is used.

 3B, the gate insulating film 36, the gate conductive film 37, and the gate hard mask nitride film 38 are formed on the SOI substrate 34 in a state where the pad nitride film 35 is removed. A gate 40 made of a laminated film of is formed.

Here, the gate insulating film 36 is formed of an oxide film having a thickness of 20 to 30 GPa, and the gate conductive film 37 has a thickness of 500 to 1500 GPa and a laminated film composed of a polysilicon film or a double film of a polysilicon film and a metal silicide film. The gate hard mask nitride film 38 is formed to have a thickness of 1000 to 1500 Å.

Then, oxide film spacers 41 and nitride film spacers 42 are sequentially formed on both side walls of the gate 40.

In this case, the oxide film spacer 41 is formed to a thickness of 50 to 100 kPa, and the nitride film spacer 42 is formed to a thickness of 300 to 500 kPa.

Referring to FIG. 3C, the silicon film 33 on both sides of the gate 40 and the buried oxide film 32 having a predetermined thickness are etched using the nitride spacer 42 and the gate hard mask nitride 38 as an etch barrier. .

Here, the etching of the silicon film 33 on both sides of the gate 40 and the buried oxide film 32 having a partial thickness is performed so that the buried oxide film 32 is etched at 500 to 1000 Å.

In the recessed gate forming technique using the conventional LOCOS process, it is very limited to increase the step difference between the channel region and the source / drain junction region. However, in the present invention, as the buried oxide layer 32 of the SOI substrate 34 is etched, the channel is increased. Since a step is generated between the region and the source / drain junction region, not only a large step can be secured, but also the adjustment is very easy. Accordingly, the present invention can effectively reduce the spiking phenomenon and parasitic series resistance compared to the recess gate forming technology using the conventional LOCOS process.

Next, as shown in FIG. 3C, a p-type impurity such as boron (B) is formed in the NMOS formation region of the substrate, and an n-type such as phosphorus (P) or an asic (As) is formed in the PMOS formation region of the substrate. The method may further include the step of implanting oblique ion implants in the unidirectional direction. In this case, the boron ion implantation is performed with 1E18 to 5E18 ions / cm 3 dose.

As described above, when the boron is unidirectionally implanted into the NMOS forming region, the hole level of the NMOS source forming region is lowered, and as a result, the floating body effect can be suppressed.

Next, as shown in 3d, after the doped polysilicon film is deposited on the entire surface of the substrate resultant, the doped polysilicon film is anisotropically etched to form the nitride spacer 42 and the etched silicon film 33. The polysilicon spacers 43 are formed on the sidewalls of the buried oxide film 32.

Here, the polysilicon spacers 43 are formed to have a thickness of 300 to 500 Å, and are formed of a polysilicon film doped with N-type or P-type impurities at a concentration of 1E20 to 5E20 ions / cm 3. In this case, a polysilicon spacer doped with N-type impurities is formed in the NMOS formation region, and a polysilicon spacer doped with P-type impurities is formed in the PMOS formation region.

In the present invention, the parasitic series of source / drain is formed by forming a highly doped polysilicon spacer 43 on the sidewalls of the nitride film spacer 42 and the etched silicon film 33 and the buried oxide film 32 as described above. The resistance can be further reduced. In the conventional investment gate forming technology, the parasitic capacitance is increased by increasing the overlap area of the gate / insulation film / silicon film on both sides of the gate. However, in the present invention, by forming a polysilicon spacer having a high concentration, the dielectric film is thickened. In comparison, parasitic capacitance is reduced.

In addition, an impurity layer (LDD: Lightly Doped Drain) formation effect may be additionally obtained due to impurities diffused from the highly doped polysilicon spacer 43. Accordingly, in the present invention, there is no need to perform a separate LDD formation process, and therefore, there is an effect of simplifying the process.

Next, the epi silicon film 44 is grown on the buried oxide film 32 on both sides of the gate 40 including the polysilicon spacer 43.

In the growing of the epi silicon layer 44, first, a silicon seed layer is formed on the etched buried oxide layer 32, and then the epi silicon layer 44 is formed on the silicon seed layer. And epitaxially CMP the epitaxial silicon film 44 to expose the hard mask nitride film 38 of the gate.

Next, referring to FIG. 3E, impurities are implanted into the grown epitaxial silicon film 44 to form a source / drain junction region 45.

As described above, in the present invention, source / drain junction regions 45 are formed by ion implantation of impurities into the grown epitaxial silicon film 44, but in-situ during growth of the epitaxial silicon film 44 -situ) may contain impurities and form source / drain junction regions 45.

Thereafter, although not shown, the semiconductor device of the present invention is completed by performing a known subsequent process.

As described above, in the present invention, a gate is formed on a silicon-on-insulator (SOI) substrate, the substrates of the predetermined source / drain formation regions on both sides of the gate are recessed, and then the sidewalls of the gate and the recessed substrate are formed. By forming a polysilicon spacer, growing an epi silicon film on the source / drain formation regions on both sides of the gate, and ion-implanting the grown epi silicon film to form a source / drain junction region, the silicon film of the channel is made thin. The thickness of the source / drain silicon film can be implemented with a transistor having a new type of fully depleted gate.

The fully depleted gate is a gate that can be implemented when the silicon film of the channel is thin as in the present invention. The depletion region of the channel region and the source / drain region overlap each other so that the entire region of the channel is depleted. It is a gate. In this transistor having a fully depleted channel, even if the gate length becomes short, the charge sharing between the source and drain junction regions is suppressed, so that short channel effects such as threshold voltage reduction and drain induced barrier lowering (DIBL) effects are suppressed. do.

In addition, in the fully depleted gate of the present invention, the floating body effect which occurs in an element having a partially depleted channel does not occur, so that device driving control is facilitated.

In the present invention, since the silicon film thickness of the source / drain can be formed considerably larger than in the related art, the increase in parasitic series resistance and the spiking phenomenon can be effectively suppressed.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention implements a fully depleted transistor in which the thickness of the silicon film of the source / drain junction region is increased by using an SOI substrate and epi silicon growth technology, thereby increasing parasitic series resistance and increasing parasitic capacitance. The spike phenomenon can be effectively suppressed, and the short channel effect such as the threshold voltage reduction phenomenon and the DIBL effect can be suppressed. Therefore, there is an effect of improving the reliability and driving characteristics of the device.

In addition, by controlling the etching thickness of the buried oxide film of the SOI substrate, the present invention can easily control the difference in the thickness of the silicon film in the channel and the source / drain regions, thereby easily controlling the characteristics of the device.

In addition, the present invention not only reduces parasitic series resistance and parasitic capacitance by forming doped polysilicon spacers on both sidewalls of the gate and the substrate under the gate, but also eliminates the need for a separate LDD forming process. The effect of the process being simplified can be obtained.

In addition, the present invention etches the buried oxide film of the SOI substrate, and then obliquely implants p-type impurities into the NMOS formation region of the substrate and n-type impurities into the PMOS formation region of the substrate to lower the hole level of the source region. In this way, the floating body effect can be further suppressed.

In addition, according to the present invention, after the epi silicon film is grown, the substrate resultant is planarized through the CMP process, so that the process margin can be improved in the subsequent exposure process.

Claims (8)

Providing an SOI substrate comprising a stacked structure of a silicon substrate, an buried oxide film, and a silicon film; Forming a gate having a hard mask nitride layer on the silicon layer of the SOI substrate; Sequentially forming oxide spacers and nitride spacers on both sidewalls of the gate; Etching the silicon film on both sides of the gate and the buried oxide film having a partial thickness using the nitride spacer and the hard mask nitride film as etch barriers; Forming a polysilicon spacer on sidewalls of the nitride spacer and the etched silicon layer and the buried oxide layer; Growing an epitaxial silicon film on portions of the buried oxide film on both sides of the gate including the polysilicon spacer; And And implanting impurities into the grown epitaxial silicon film to form source / drain regions. The method of manufacturing a semiconductor device according to claim 1, wherein the buried oxide film is formed to a thickness of 1500 to 2500 GPa and the silicon film is formed to a thickness of 100 to 500 GPa. The method of claim 1, wherein the etching of the silicon film on both sides of the gate and the buried oxide film having a partial thickness is performed such that the buried oxide film is etched at 500 to 1000 Å. The method of claim 1, wherein after the etching of the silicon film on both sides of the gate and the buried oxide film having a partial thickness, and before the forming of the polysilicon spacer, p-type impurities are formed in the NMOS forming region of the substrate. The method of manufacturing a semiconductor device further comprising the step of implanting oblique ions into the PMOS formation region in a unidirectional direction, respectively. The method of manufacturing a semiconductor device according to claim 4, wherein the p-type impurity ion implantation is performed with boron ions of 1E18 to 5E18 ions / cm 3 dose. The method of claim 1, wherein the polysilicon spacer is formed to a thickness of 300 to 500 kHz. The method of claim 1, wherein the polysilicon spacer is doped with N-type or P-type impurities at a concentration of 1E20 to 5E20 ions / cm 3. The method of claim 1, wherein the growing of the epi silicon film is performed. Forming a silicon seed film on the etched oxide film; Growing an epi silicon film on the silicon seed film; And And CMPing the epi silicon film to expose the hard mask nitride film of the gate.

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