KR100726636B1 - Plasma display device - Google Patents

Abstract

The present invention relates to a plasma display device capable of reducing the occurrence of EMI.

A plasma display device according to the present invention comprises: a plasma display panel for displaying an image; And a sustain pulse supply unit for supplying sustain pulses to the scan electrodes of the plasma display panel. Connected between the sustain pulse supply unit and the scan electrode of the plasma display panel, and connected between a setup voltage supply unit for supplying a rising ramp waveform to the plasma display panel, and a common terminal and a base voltage source of the sustain pulse supply unit and the setup voltage supply unit. And a filter unit for filtering a picking component of the high frequency current generated by the sustain pulse and the rising ramp waveform among the plurality of driving waveforms supplied to the scan electrodes of the plurality of driving waveforms.

Description

Plasma Display {PLASMA DISPLAY DEVICE}

FIG. 1 is a diagram illustrating a subfield pattern of an 8 bit default code for implementing 256 gray levels in a plasma display panel.

2 is a waveform diagram showing a driving waveform of a conventional plasma display panel.

3 is a diagram illustrating a scan driver of a conventional plasma display panel.

4 is a diagram showing EMI generated by a sustain pulse and a rising ramp waveform in a conventional plasma display device.

5 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating a scan driver of the plasma display panel illustrated in FIG. 5.

7 is a diagram illustrating a frequency band in which generation of EMI is prevented by the display device of the present invention.

8 is a diagram illustrating a frequency band in which generation of EMI is prevented by the display device of the present invention.

<Description of Symbols for Main Parts of Drawings>

6, 56: sustain pulse supply part 8, 58: setup voltage supply part

10, 60: set down voltage supply control unit 12, 62: scan voltage supply unit

14, 64: scan reference voltage supply 16, 66: scan IC

18, 68: energy recovery / supply unit 20, 70: sustain voltage supply unit

22, 72: base voltage supply 32: PDP

34: discharge cell 36: data driver

38: scan driver 40: sustain driver

42: timing controller 44: drive voltage generator

74: filter unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to a plasma display device capable of reducing generation of EMI.

Plasma Display Panel (hereinafter referred to as " PDP ") is used to excite and emit phosphors using ultraviolet rays generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne is discharged. Is displayed. Such PDPs are not only thin and large in size, but also have improved image quality due to recent technology development.

 FIG. 1 is a diagram illustrating a subfield pattern of an 8 bit default code for implementing 256 gray levels in a plasma display panel.

Referring to FIG. 1, the PDP performs time division driving by dividing one frame into several subfields having different emission counts in order to implement grayscale of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and a discharge cell for selecting a discharge cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. Each of the eight subfields SF1 to SF8 is divided into a reset period RP, an address period AP, and a sustain period SP as described above. At this time, while the reset period RP and the address period AP of each subfield are the same for each subfield, the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2) in each subfield. 3,4,5,6,7).

2 is a diagram illustrating a driving waveform of a general PDP.

Referring to FIG. 2, each of the subfields SF includes a reset period RP for initializing the discharge cells of the full screen, an address period AP for selecting the discharge cells, and a sustain for discharging the selected discharge cells. It includes a period SP.

In the reset period RP, the rising ramp waveform PR is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform PR causes a weak discharge (setup discharge) to occur in the cells of the full screen, thereby generating wall charges in the cells. After the rising ramp waveform PR is applied in the set-down period SD, the positive sustain voltage Vs lower than the peak voltage of the rising ramp waveform PR to the negative scan voltage Vs is negative. The falling ramp waveform NR falling at a predetermined slope is simultaneously applied to the scan electrodes Y. The falling ramp waveform NR generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges, thereby uniformly retaining wall charges required for address discharges in the cells of the full screen.

In the address period AP, a negative scan pulse SCNP is sequentially applied to the scan electrodes Y, and a positive data pulse DP is applied to the address electrodes. As the voltage difference between the scan pulse SCNP and the data pulse DP and the wall voltage generated in the reset period RP are added, an address discharge is generated in the cell to which the data pulse DP is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive sustain voltage Vs is applied to the sustain electrodes Z during the set down period SD and the address period AP.

In the sustain period SP, a sustain pulse SSUS is applied to the scan electrodes Y and the sustain electrodes Z alternately. Then, the cell selected by the address discharge is in the form of surface discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse SSUS is applied while the wall voltage and the sustain pulse SSUS in the cell are added. Sustain discharge occurs. Here, the sustain pulses SSP have the same voltage value as the sustain voltage Vs.

The scan driving waveforms supplied to the scan electrodes Y among the driving waveforms of the PDP are formed by the scan driver of the plasma display panel shown in FIG. 3.

3 is a diagram illustrating a scan driver of a conventional PDP.

Referring to FIG. 3, a conventional scan driver includes a panel capacitor Cp having a scan electrode Y and a sustain electrode Z, a sustain pulse supply unit 6, a setup voltage supply unit 8, and a setdown voltage supply control unit 10. ), A scan voltage supply unit 12, a scan reference voltage supply unit 14, a scan integrated circuit (hereinafter referred to as an “IC”) 16, a fifth switch SW5, and a seventh switch SW7. do.

The panel capacitor Cp equivalently represents the capacitance formed between the scan electrode Y and the sustain electrode Z of the PDP. The panel capacitor Cp generates sustain discharge by sustain voltages having opposite polarities.

The sustain pulse supply unit 6 supplies the sustain pulse VSP having the sustain voltage level Vs and the ground voltage level GND to the scan electrodes Y1 to Yn during the sustain period SP. ) And ground voltage (GND). In addition, the sustain pulse supply unit 6 recovers energy of the reactive power that does not contribute to the discharge in the PDP from the panel capacitor Cp during the sustain period SP, and recovers the recovered energy to the scan electrodes Y1 to Yn. Supply. To this end, the sustain pulse supply unit 6 includes an energy recovery / supply unit 18, a sustain voltage supply unit 20, and a base voltage supply unit 22. Such a sustain pulse supply part 6 is used for an energy recovery circuit.

The energy recovery / supply unit 18 recovers the energy of reactive power that does not contribute to the discharge in the PDP during the sustain period SP from the panel capacitor Cp, and supplies the recovered energy to the panel capacitor Cp. The energy recovery / supply unit 18 may include a source capacitor Cs for storing the recovered energy, a second node N2 between the source capacitor Cs and the sustain voltage supply unit 20 and the base voltage supply unit 22. An inductor L connected between the first and second in series connected between the source capacitor Cs and the inductor L to form a current path for supplying the energy stored in the source capacitor Cs to the panel capacitor Cp. Between the first switch SW1 and the first diode D1 and the panel capacitor Cp between the first diode D1 and the inductor L to form a current path for recovering energy of reactive power not contributing to the discharge. And a second diode D2 and a second switch SW2 connected in series between the first node N1 and the source capacitor Cs.

The sustain voltage supply unit 20 supplies the sustain voltage Vs to the scan electrode Y of the panel capacitor Cp during the setup period SU and the sustain period SP during the reset period RP. The sustain voltage supply unit 20 includes a sustain voltage source Vs, a third switch SW3 connected between the sustain voltage source Vs, and the second node N2.

The base voltage supply unit 22 supplies the base voltage GND to the scan electrode Y of the panel capacitor Cp during the sustain period SP. The base voltage supply unit 22 includes a base voltage source GND and a fourth switch SW4 connected between the base voltage source GND and the second node N2.

The setup voltage supply unit 8 has a setup voltage Vsetup having a predetermined slope such that the rising ramp waveform PR shown in FIG. 2 is supplied to the scan electrode Y during the setup period SU during the reset period RP. Is supplied to the scan electrode (Y). Such a setup voltage supply 8 is a sixth switch connected between the pre-setup voltage source Vsetup, the setup voltage source Vsetup and the third node N3 between the fifth switch SW5 and the seventh switch SW7. (SW6) and a first variable resistor (R1) connected to the gate terminal of the sixth switch (SW6).

The setdown voltage supply control unit 10 has a setdown voltage having a predetermined slope such that the falling ramp waveform NR as shown in FIG. 2 is supplied to the scan electrode Y during the setdown period SD of the reset period RP. -Vy is supplied to the scan electrode (Y). The set-down voltage supply control unit 10 includes an eighth switch SW8 connected between the scan voltage source -Vy and the fourth node N4 between the seventh switch SW7 and the scan reference voltage supply unit 14. The second variable resistor R2 is connected to the gate terminal of the eighth switch SW8.

The scan voltage supply unit 12 supplies the scan voltage -Vy as shown in FIG. 2 to the scan electrode Y during the address period AP. The scan voltage supply unit 12 includes a ninth switch SW9 connected in parallel with the eighth switch SW8 between the scan voltage source -Vy, the scan voltage source -Vy, and the fourth node N4. do.

The scan reference voltage supply unit 14 supplies the scan reference voltage Vsc as shown in FIG. 2 to the scan electrode Y during the address period AP. The scan reference voltage supply unit 14 may include a tenth switch SW10 and an eleventh switch SW11 connected in series between the scan reference voltage source Vsc, the scan reference voltage source Vsc, and the fourth node N4. Include.

The scan IC 16 includes a twelfth switch SW12 and a fifth connected in a push-pull form between the fifth node N5 and the fourth node N4 between the tenth switch SW10 and the eleventh switch SW11. 13 switch SW13. Here, the twelfth switch SW12 connects the scan electrode Y of the panel capacitor Cp to the fifth node N5 via its own body diode, and the thirteenth switch SW13 has its own The fourth node N4 is connected to the scan electrode Y of the panel capacitor Cp via the body diode.

4 is a diagram illustrating an electromagnetic wave disturbance generated when a conventional plasma display device is driven.

Referring to FIG. 4, the conventional plasma display device scans the panel capacitor Cp during the setup period SU for generating wall charges in the discharge cells 4 and the sustain period SP for generating sustain discharges. Plasma in the frequency band of approximately 30 MHz to 40 MHz depending on the picking component of the high frequency current generated by the high frequency, the rising ramp waveform PR having the high voltage and the sustain pulse SSUS supplied to the electrode Y There is a problem that a lot of electromagnetic interference (hereinafter referred to as "EMI") occurs in the front direction of the display panel.

Accordingly, an object of the present invention is to provide a plasma display device capable of reducing the occurrence of EMI.

In order to achieve the above object, a plasma display device according to the present invention comprises a plasma display panel for displaying an image; And a sustain pulse supply unit for supplying sustain pulses to the scan electrodes of the plasma display panel. Connected between the sustain pulse supply unit and the scan electrode of the plasma display panel, and connected between a setup voltage supply unit for supplying a rising ramp waveform to the plasma display panel, and a common terminal and a base voltage source of the sustain pulse supply unit and the setup voltage supply unit. And a filter unit for filtering a picking component of the high frequency current generated by the sustain pulse and the rising ramp waveform among the plurality of driving waveforms supplied to the scan electrodes of the plurality of driving waveforms.

The filter unit may include at least one film capacitor.

When there are a plurality of film capacitors, the film capacitors may be connected between the common terminal of the sustain pulse supply unit and the setup voltage supply unit and the base voltage source by any one of series or parallel methods.

The film capacitor is characterized in that it has a capacitance of about 0.5kW to 6.0kW.

The film capacitor is characterized by filtering a frequency band of about 20MHz to 60MHz.

A plasma display device according to the present invention includes a data driver for supplying data to the address electrodes of the plasma display panel; A sustain driver for driving the sustain electrode of the plasma display panel; A timing controller for controlling the scan driver, data driver, and sustain driver; And a driving voltage generator configured to generate driving voltages necessary for the scan driver, the data driver, and the sustain driver.

Other objects and advantages other than the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 7.

5 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

Referring to FIG. 5, a plasma display device according to an exemplary embodiment of the present invention includes a PDP 32 for displaying an image, a data driver 36 for supplying data to address electrodes X1 to Xm, and scan electrodes. A scan driver 38 for driving (Y1 to Yn), a sustain driver 40 for driving the sustain electrodes Z, a timing controller 42 for controlling each driver 36, 38, 40, and A driving voltage generator 44 is provided to supply driving voltages necessary for each of the driving units 36, 38, and 40.

The PDP 32 includes an upper plate on which scan electrodes Y1 to Yn and sustain electrodes Z are formed, and a lower plate on which address electrodes X1 to Xm are formed. The upper plate includes an upper dielectric layer (not shown) for accumulating wall charges and a protective film (not shown) for protecting the damage of the upper dielectric layer due to sputtering during plasma discharge (not shown) and the scan electrodes Y1 to Yn and the sustain electrodes. (Z) is laminated on. In the lower plate, a lower dielectric layer (not shown) for accumulating wall charges is formed under the address electrodes X1 to Xm. In the PDP 32, discharge cells 34 are formed in an area where scan electrodes Y1 to Yn, sustain electrodes Z, and address electrodes X1 to Xm cross each other. At this time, each discharge cell 34 is separated by a partition wall (not shown) formed on the lower plate, the red, green and blue phosphors are coated therein. In the PDP 32, the discharge cells 34 are selected by the data pulses DP and the scan pulses SCNP supplied to the address electrodes X1 to Xm and the scan electrodes Y1 to Yn. The sustain discharge is maintained by the sustain pulse SSUS supplied to the scan electrodes Y1 to Yn and the sustain electrodes Z. Accordingly, in the discharge cells 34, phosphors applied to the inside of the discharge cells 34 are emitted by ultraviolet rays generated during the sustain discharge to emit visible light, thereby displaying an image.

The data driver 36 samples and latches data in response to the timing control signal Cx supplied from the timing controller 42 and supplies the data voltage Va of the data to the address electrodes X1 to Xm. .

The scan driver 38 applies the reset pulses PR and NR as shown in FIG. 2 to the scan electrodes Y1 to Yn during the reset period RP in response to the timing control signal Cy supplied from the timing controller 42. Supply. In this case, the scan driver 38 may use a filter unit (not shown) including a film capacitor to prevent electromagnetic interference (“EMI”) from occurring in the front direction of the PDP 32. Picking component of the high frequency current generated by the rising ramp waveform PR having high frequency and high voltage, that is, the noise is filtered and then the rising ramp waveform PR is filtered to the scan electrodes Y1 to Yn. Supply. Thus, the plasma display device of the present invention can prevent the EMI from occurring in the front direction of the PDP 32 during the setup period SU. Detailed description thereof will be described later. Also, the scan driver 38 scans the scan reference voltage Vsc as shown in FIG. 2 during the address period AP in response to the timing control signal Cy supplied from the timing controller 42. The scan pulse SCNP having a negative scan voltage (-Vy) is sequentially supplied to the scan electrodes Y1 to Yn. The scan driver 38 also has a sustain pulse susp having a sustain voltage level Vs and a ground voltage level GND during the sustain period SP in response to a timing control signal Cy supplied from the timing controller 42. ) Is supplied to the scan electrodes Y1 to Yn. At this time, the picking components of the high frequency current, that is, the noise-sustained sustain pulse SUSP are supplied to the scan electrodes Y1 to Yn by a filter unit (not shown) including a film capacitor. Accordingly, the plasma display device of the present invention can prevent the EMI from occurring in the front direction of the PDP 32 during the sustain period SP. Detailed description thereof will be described later.

The sustain driver 40 has a positive sustain voltage of positive polarity on the sustain electrodes Z during the setdown period SD and the address period AP in response to the timing control signal Cz supplied from the timing controller 42. After supplying (Vs), it is alternately operated with the scan driver 38 during the sustain period (SP) to sustain the sustain pulse (SUSP) having a sustain voltage level (Vs) and ground voltage level (GND) To feed.

The timing controller 42 receives the vertical / horizontal synchronization signal and the clock signal to generate the timing control signals Cx, Cy, and Cz necessary for each of the driving units 36, 38, and 40, and the timing control signals Cx, Cy, Each drive unit 36, 38, 40 is controlled by supplying Cz) to the drive units 36, 38, 40. At this time, the data control signal Cx includes a sampling clock for latching data, a latch control signal, a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element. In addition, the scan control signal Cy includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the scan driver 38. The sustain control signal Cz includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the sustain driver 40.

The driving voltage generator 44 includes a setup voltage Vsetup, a negative scan voltage (-Vy), a direct current scan reference voltage Vsc, a positive polarity (+) sustain voltage Vs, and a data voltage Va. And the like are supplied to the data driver 36, the scan driver 38, and the sustain driver 40.

FIG. 6 is a diagram illustrating in detail the scan driver illustrated in FIG. 5.

Referring to FIG. 6, the scan driver of the PDP supplies a sustain pulse having a voltage level of the sustain voltage Vs and the ground voltage GND to the scan electrode Y of the panel capacitor Cp. The sustain pulse supply unit 56 for supplying the setup voltage V58 for supplying the setup voltage Vsetup to the scan electrode Y of the panel capacitor Cp and the sustain electrode for the scan electrode Y of the panel capacitor Cp The set-down voltage supply control unit 60 and the scan electrode Y of the panel capacitor Cp are controlled to supply a falling ramp waveform falling by a predetermined slope from the voltage Vs to the negative scan voltage -Vy. A scan voltage supply unit 62 for supplying a negative scan voltage (−Vy), a scan reference voltage supply unit 64 for supplying a scan reference voltage Vsc to a scan electrode Y of the panel capacitor Cp, Scan electrode Y of scan voltage supply part 62, scan reference voltage supply part 64, and panel capacitor Cp The picking component of the high frequency current among the currents generated by the scan integrated circuit (IC) 66, the sustain pulse (SUSP) and the rising ramp waveform (PR) connected in a push-pull form, that is, And a filter unit 74 for filtering noise, a first switch SW1, and a second switch SW2.

The panel capacitor Cp equivalently represents the capacitance formed between the scan electrode Y and the sustain electrode Z of the PDP 32.

The sustain pulse supply unit 56 maintains the sustain voltage at the scan electrodes Y of the panel capacitor Cp during the reset period RP and the sustain period SP according to the timing control signal Cy supplied from the timing controller 42. (Vs) and ground voltage (GND) are supplied. The sustain pulse supply unit 56 includes an energy recovery / supply unit 68, a sustain voltage supply unit 70, and a base voltage supply unit 72.

The energy recovery / supply unit 68 is connected to the first node N1 between the sustain voltage supply unit 70 and the base voltage supply unit 72 to recover energy of reactive power that does not contribute to discharge in the panel capacitor Cp. In addition, the recovered energy is supplied to the scan electrode (Y) and the sustain electrode (Z) of the panel capacitor (Cp). At this time, the energy recovery / supply unit 68 recovers the energy stored in the panel capacitor Cp by the sustain voltage Vs, and supplies the recovered energy to the scan electrode Y of the panel capacitor Cp. The energy recovery / supply unit 68 is connected between the source capacitor Cs, the source capacitor Cs, and the first node N1 for storing energy recovered from the scan electrode Y of the panel capacitor Cp. Connected in series between the source capacitor Cs and the inductor L to form a current path for supplying the energy stored in the inductor L and the source capacitor Cs to the scan electrode Y of the panel capacitor Cp. The second node N2 between the first diode D1 and the inductor L to form a current path for recovering energy stored in the third switch SW3 and the first diode D1 and the panel capacitor Cp. ) And a second diode D2 and a fourth switch SW4 connected between the source capacitor Cs. Here, the third switch SW3, the first diode D1, the second diode D2, and the fourth switch SW4 are connected in parallel between the source capacitor Cs and the inductor L.

The source capacitor Cs recovers the energy charged in the panel capacitor Cp by the sustain voltage Vs, and supplies the recovered energy to the scan electrode Y of the panel capacitor Cp.

The inductor L stores energy supplied from the panel capacitor Cp and supplies the stored energy to the panel capacitor Cp by LC resonance with the panel capacitor Cp.

The third switch SW3 is connected between the source capacitor Cs and the second node N2 so that energy stored in the source capacitor Cs in response to the third switching control signal supplied from the timing controller 42 is the panel capacitor. A current pass is formed so as to be supplied to the scan electrode Y of (Cp).

The first diode D1 is connected between the third switch SW3 and the second node N2 so that the energy charged in the source capacitor Cs is supplied to the scan electrode Y of the panel capacitor Cp. Prevents reverse current from capacitor Cp.

The fourth switch SW4 is connected between the second node N2 and the source capacitor Cs to store energy stored in the panel capacitor Cp in response to the fourth switching control signal supplied from the timing controller 42. A current path is formed to recover to (Cs).

The second diode D2 is connected between the second node N2 and the fourth switch SW4 so that the inversion from the source capacitor Cs when the energy stored in the panel capacitor Cp is recovered to the source capacitor Cs To prevent leakage.

The sustain voltage supply unit 70 is connected to the first node N1 to supply the sustain voltage Vs to the scan electrode Y of the panel capacitor Cp during the setup period and the sustain period during the reset period. The sustain voltage supply unit 70 includes a sustain voltage source Vs and a fifth switch SW5.

The fifth switch SW5 is connected between the sustain voltage source Vs and the first node N1 to connect the second node N2 to the first node in response to the fifth switching control signal supplied from the timing controller 42. Electrical connection to N1). Therefore, the sustain voltage Vs is transmitted to the first node N1 during the setup period and the sustain period during the reset period.

The base voltage supply unit 72 is connected to the first node N1 to supply the base voltage GND to the scan electrode Y during the sustain period. The base voltage supply unit 72 includes a base voltage source GND and a sixth switch SW6.

The sixth switch SW6 is connected between the first node N1 and the base voltage source GND to connect the base voltage source GND to the first node N1 in response to a sixth switching control signal supplied from the timing controller 42. Electrical connection. As a result, the ground voltage GND is transmitted to the first node N1 during the sustain period.

The energy recovery / supply unit 68, the sustain voltage supply unit 70, and the base voltage supply unit 72 are used as an energy recovery circuit.

The setup voltage supply unit 58 is connected to the third node N3 between the first switch SW and the second switch SW2 to panel the setup voltage Vsetup rising to a predetermined slope during the setup period during the reset period. The scan electrode Y is supplied to the capacitor Cp. To this end, the sustain voltage Vs is supplied from the sustain voltage supply unit 70 to the third node N3 in the setup period during the reset period. The setup voltage supply unit 58 includes a setup voltage source Vsetup, a seventh switch SW7 and a first variable resistor R1.

The seventh switch SW7 is connected between the setup voltage source Vsetup and the third node N3 to set up the setup voltage source Vsetup in response to the seventh switching control signal supplied from the timing controller 42. Electrical connection.

The first variable resistor R1 is connected to the gate terminal of the seventh switch SW7 to adjust the slope of the setup voltage Vsetup supplied from the setup voltage source Vsetup. Accordingly, the setup voltage Vsetup supplied from the setup voltage source Vsetup to the third node N3 has a predetermined slope.

The sustain voltage supply unit 70 and the setup voltage supply unit 58 supply the sustain voltage Vs and the setup voltage Vsetup having a predetermined slope to the third node N3 during the setup period during the reset period. The rising ramp waveform rising from the voltage Vs to the peak voltage Vs + Vsetup at a predetermined slope is supplied to the scan electrode Y of the panel capacitor Cp.

The set-down voltage supply control unit 60 is connected between the second node SW2, the scan reference voltage supply unit 64, and the fourth node N4, which is a common terminal of the scan IC 66, and the scan voltage source (-Vy). During the set down period, the falling ramp waveform falling from the sustain voltage Vs to the scan voltage −Vy by a predetermined slope is controlled to be supplied to the scan electrode Y of the panel capacitor Cp. The set down voltage supply control unit 60 includes an eighth switch SW8 and a second variable resistor R2.

The eighth switch SW8 is connected between the fourth node N4 and the scan voltage source -Vy and is scanned from the scan voltage source -Vy in response to the eighth switching control signal supplied from the timing controller 42. The voltage (-Vy) is transmitted to the fourth node N4. At this time, the scan voltage (-Vy) transmitted to the fourth node N4 has a predetermined slope.

The second variable resistor R2 is connected to the gate terminal of the eighth switch SW8 to control the slope of the scan voltage -Vy supplied from the scan voltage source -Vy. Accordingly, the scan voltage (-Vy) supplied from the scan voltage source (-Vy) during the set down period during the reset period has a predetermined slope. That is, the scan voltage (-Vy) having a predetermined slope is supplied to the fourth node N4 during the setdown period during the reset period.

The scan voltage supply unit 62 is connected in parallel to the set-down voltage supply control unit 60 and the fourth node N4 to scan the scan pulse having the scan voltage level (-Vy) during the address period. Supply to Y). The scan voltage supply unit 62 includes a scan voltage source -Vy and a ninth switch SW9.

The ninth switch SW9 is connected in parallel with the eighth switch SW8 between the fourth node N4 and the scan voltage source -Vy to scan in response to the ninth switching control signal supplied from the timing controller 42. The scan voltage -Vy supplied from the voltage source -Vy is transmitted to the fourth node N4. As a result, the scan voltage (-Vy) is transmitted to the fourth node N4 during the address period and the sustain period.

The scan reference voltage supply unit 64 is connected between the fourth node N4 and the scan IC 66 to supply the scan reference voltage Vsc to the scan electrode Y of the panel capacitor Cp during the address period. The scan reference voltage supply unit 64 may include the tenth switch SW10 and the eleventh switch SW11 connected in series between the scan reference voltage source Vsc, the scan reference voltage source Vsc, and the fourth node N4. Include.

The tenth switch SW10 is connected between the scan reference voltage source Vsc and the scan IC 66 to switch the scan reference voltage source Vsc in response to the tenth switching control signal supplied from the timing controller 42. The fifth node N5, which is a common terminal of SW11 and the scan IC 66, is electrically connected. Accordingly, the scan reference voltage Vsc is supplied to the fifth node N5 during the address period.

The eleventh switch SW11 is connected between the fifth node N5 and the fourth node N4 to respond to the eleventh switching control signal supplied from the timing controller 42 to the fifth node N5 and the fourth node. The node N4 is electrically connected. Accordingly, the voltage supplied to the fifth node N5 is transmitted to the fourth node N4, and the voltage supplied to the fourth node N4 is transmitted to the fifth node N5.

The scan IC 66 includes a twelfth switch SW12 and a thirteenth switch connected in a push-pull form between the fifth node N5 and the fourth node N4 and the scan electrode Y of the panel capacitor Cp. SW13). At this time, the output terminal between the twelfth switch SW12 and the thirteenth switch SW13 is connected to the scan electrode Y of the panel capacitor Cp.

The twelfth switch SW12 is connected between the fifth node N5 and the scan electrode Y of the panel capacitor Cp and is supplied to the fifth node N5 via its body diode. Is supplied to the scan electrode Y of the panel capacitor Cp. In other words, the twelfth switch SW12 is a voltage supplied to the fifth node N5 by electrically connecting the scan electrode Y of the panel capacitor Cp to the fifth node N5 via its body diode. Is supplied to the scan electrode Y of the panel capacitor Cp. At this time, a negative voltage is supplied to the fifth node N5. Accordingly, a voltage as low as a negative voltage supplied to the fifth node N5 is supplied to the scan electrode Y of the panel capacitor Cp.

The thirteenth switch SW13 is connected between the fourth node N4 and the scan electrode Y of the panel capacitor Cp and receives the voltage supplied to the fourth node N4 via its body diode. It is supplied to the scan electrode Y of Cp). In other words, the thirteenth switch SW13 is a voltage supplied to the fourth node N4 by electrically connecting the fourth node N4 to the scan electrode Y of the panel capacitor Cp via its body diode. Is supplied to the scan electrode Y of the panel capacitor Cp. At this time, the positive voltage is supplied to the fourth node N4. Accordingly, the scan electrode Y of the panel capacitor Cp is supplied with a voltage as high as the voltage of the positive polarity supplied to the fourth node N4.

The filter unit 74 is connected between the sustain node supply unit 56 and the third node N3, which is a common terminal of the setup voltage supply unit 58, and the base voltage source GND, so that the sustain voltage supply unit 70 and the setup voltage supply unit ( The picking component of the high frequency current is filtered out of the current generated when the sustain pulse and the rising ramp waveform supplied from 58 are supplied to the scan electrode Y of the panel capacitor Cp. As a result, when the sustain pulse and the rising ramp waveform are supplied to the scan electrode Y of the panel capacitor Cp, EMI can be prevented from occurring in the front direction of the PDP 32. This, the filter unit 74 includes at least one film capacitor (Cf). In this case, when a plurality of film capacitors Cf are included in the filter unit 74, the film capacitors Cf may be disposed between the third node N3 and the base voltage source GND in parallel or in series according to the frequency band of the current to be filtered. Is connected to. That is, when the frequency band of the current to be filtered is widened, the film capacitors Cf are connected in parallel, and when the frequency band of the current to be filtered is narrowed, the film capacitors Cf are connected in series. This is because, when energy is supplied to the panel capacitor Cp, that is, when the sustain voltage Vs is supplied to the panel capacitor Cp, the band gap of the resonance frequency is adjusted according to the capacitance value of the film capacitor Cf. This is because the frequency band to be filtered is adjusted. In the present invention, through such a film capacitor (Cf), in order to filter a frequency band of about 20 MHz to 60 MHz, especially a frequency band of about 30 MHz to 40 MHz, a capacitance of about 0.5 Hz to 6.0 Hz, in particular about 1.0 A film capacitor Cf having a capacitance of about ㎋ to 4.0 ㎋ is used.

The first switch SW1 is connected between the first node N1 and the third node N3 to electrically connect the first node N1 to the third node N3 via its own body diode. . Accordingly, the voltage supplied from the energy recovery / supply unit 68, the sustain voltage supply unit 70, and the base voltage supply unit 72 is transferred from the first node N1 to the third node through the body diode of the first switch SW1. Is passed to node N3. That is, the first switch SW1 forms an energy supply path for supplying energy to the panel capacitor Cp using its own body diode. In addition, the first switch SW1 electrically connects the third node N3 to the first node N1 in response to the first switching control signal supplied from the timing controller 42. Accordingly, energy of reactive power that does not contribute to the discharge in the panel capacitor Cp is transferred from the third node N3 to the first node N1. That is, the first switch SW1 forms an energy recovery path for transferring energy from the panel capacitor Cp to the energy recovery / supply unit 68 in response to the first switching control signal.

The second switch SW2 is connected between the third node N3 and the fourth node N4 to electrically connect the fourth node N4 to the third node N3 via its own body diode. . Accordingly, energy of reactive power that does not contribute to the discharge in the panel capacitor Cp is transferred from the fourth node N4 to the third node N3. That is, the second switch SW2 forms an energy recovery path for transferring energy from the panel capacitor Cp to the energy recovery / supply unit 68 using its own body diode. In addition, the second switch SW2 electrically connects the third node N3 to the fourth node N4 in response to the second switching control signal supplied from the timing controller 42. Accordingly, the voltage supplied to the third node N3, that is, the voltage filtered by the filter unit 74 is transmitted to the fourth node N4. That is, the second switch SW2 forms an energy supply path for supplying energy to the panel capacitor Cp in response to the second switching control signal supplied from the timing controller 42.

The switches SW1 to SW13 use a field effect transistor in which a body diode is embedded.

FIG. 7 is a diagram illustrating EMI generated when a sustain pulse is supplied to the panel capacitor shown in FIG. 6.

Referring to FIG. 7, in the plasma display device of the present invention, the filter unit 74 is disposed between the third node N3, which is a common terminal of the sustain pulse supply unit 56 and the setup voltage supply unit 58, and the base voltage source GND. Installed to reduce the EMI generated in the front direction of the PDP 32 by filtering the picking component of the high frequency current generated when the sustain pulse and the rising ramp waveform are supplied to the scan electrode Y of the panel capacitor Cp. You can. In other words, in the conventional plasma display device, when the sustain pulse SSUS is supplied to the scan electrode Y of the panel capacitor Cp, a high frequency and high voltage sustain pulse SSUS is applied to the front surface of the PDP 32. EMI is generated. However, in the present invention, the filter unit 74 including the film capacitor Cf is disposed in the path through which the sustain pulse SSUS is supplied to filter the picking component of the high frequency current generated by the sustain pulse SSUS, that is, the noise. By doing so, EMI generated in the front direction of the PDP 32 can be reduced.

8 is a diagram illustrating a frequency band in which generation of EMI is prevented by the display device of the present invention.

Referring to FIG. 8, in the conventional plasma display device, when the sustain pulse SSUS is supplied to the scan electrode Y of the panel capacitor Cp, a frequency band of about 20 MHz to 60 MHz, particularly about 30 MHz to 40 MHz It can be seen that a lot of EMI is generated in the front direction of the PDP 32 in the frequency band of about MHz. However, in the plasma display device according to the present invention, the filter portion 74 including the film capacitor Cf having a capacitance of about 0.5 kW to 6.0 mW, in particular, about 1.0 mW to 4.0 mW, includes a sustain pulse supply part ( 56) and a frequency band of about 20 MHz to 60 MHz, particularly about 30 MHz to 40 MHz, provided between the common terminal of the setup voltage supply unit 58 and the ground voltage source GND. EMI filtering can be prevented in the frequency band of approximately 20 MHz to 60 MHz by filtering the picking component of the current having. In particular, when the filter unit 74 including the film capacitor Cf having a capacitance of 4.0 GHz is used, EMI generated in a frequency band of about 30 MHz to 40 MHz is approximately 5 dB 대비 in comparison with a conventional plasma display device. can be reduced by / m.

As described above, the present invention provides a high frequency current generated by the sustain pulse and the rising ramp waveform by providing a filter unit between the common terminal of the sustain pulse supply unit supplying the sustain pulse and the setup voltage supply unit supplying the setup voltage and the base voltage source. By filtering the picking component of, EMI can be prevented from being generated in the front direction of the plasma display panel by the sustain pulse and the rising ramp waveform.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

A plasma display panel for displaying an image; And A sustain pulse supply unit for supplying a sustain pulse to the scan electrode of the plasma display panel; A setup voltage supply unit connected between the sustain pulse supply unit and a scan electrode of the plasma display panel to supply a rising ramp waveform to the plasma display panel; And Connected between a common terminal of the sustain pulse supply unit and the setup voltage supply unit and a base voltage source, a picking component of a high frequency current generated by sustain pulses and rising ramp waveforms among a plurality of driving waveforms supplied to a scan electrode of the plasma display panel; Plasma display device comprising a filter for filtering. delete The method of claim 1, And the filter unit comprises at least one film capacitor. The method of claim 3, wherein And the film capacitor is connected between the common terminal of the sustain pulse supply unit and the setup voltage supply unit and the base voltage source by any one of series or parallel methods. The method of claim 4, wherein And the film capacitor has a capacitance of about 0.5 kW to 6.0 kW. The method of claim 4, wherein And the film capacitor filters a frequency band of approximately 20 MHz to 60 MHz. The method of claim 1, A data driver for supplying data to address electrodes of the plasma display panel; A sustain driver for driving the sustain electrode of the plasma display panel; A timing controller for controlling the scan driver, data driver, and sustain driver; And And a driving voltage generator configured to generate driving voltages necessary for the scan driver, the data driver, and the sustain driver.

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