KR100725093B1 - semiconductor memory device having NOR type flat cell and driving method therefore - Google Patents

Abstract

A method of reading a semiconductor memory device using a hierarchical bit line arrangement and having NOR type flat memory cells is disclosed. In such a method, a plurality of memory cells connected to one main bit line through a bank select transistor are separated by parts, and a bias voltage level applied to a corresponding adjacent ground bit line is differentially applied to each of the separated parts. It is characterized by. Accordingly, it is possible to optimally prevent deterioration of characteristics of the on and off cells, thereby improving read malfunction.

Semiconductor Memory Devices, Noah Type Flat Cells, Ground Bitlines, Bias Voltages

Description

Semiconductor memory device having NOR type flat cell and driving method therefore}             

1 and 2 illustrate a structure of a memory cell array according to the related art.

3 through 6 are diagrams illustrating memory cell array structures according to example embodiments.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device such as a read only memory, and more particularly, to a semiconductor memory device having a NOR type flat cell.

In accordance with the development of semiconductor technology and various needs of users, semiconductor integrated circuit devices are becoming more integrated. Therefore, low voltage operation (Low VCC Operation) and high speed (High Speed) operation is required is essential, many difficulties are required to implement such a device.                         

Figure 1 shows a memory cell array structure according to the prior art. Referring to FIG. 1, a bank architecture of a memory cell array basically applies a hierarchical bit line system. According to the above configuration, the sub bit lines (sub bit lines) are arranged as indicated by reference numerals SBLi, SBL1, ..., and the main (main) bit lines are denoted by reference numerals MBL0, MBL1,... Are arranged as .., and the ground (ground) bit lines are arranged as indicated by reference numerals GBL0, GBL1, ...,. Each main bit line is formed between an odd (odd) sub bit line and an even (even) sub bit line, and a plurality of sub cells corresponding to a plurality of memory cells (memory cells) are formed. It is formed between the lines. Gate terminals of the memory cells arranged in each column are connected to corresponding word lines WLi, respectively. Here, the selection of the word lines WLi is performed by the first decoder 10. In addition, each of the main bit lines is connected to the sense amplifier circuit 40 through the main bit line selection circuit 35, and the ground bit lines are connected to the ground bit line selection circuit 20, respectively.

Bank select transistors GST1, GST2,... Are connected to one ends of the odd-numbered sub bit lines SBL1, SBL3,..., And two adjacent bank select transistors GST1, GST2. ... are connected to the ground bit lines GBL1, GBL2, ..., respectively. Gates of the bank select transistors GST1, GST2,... Alternately connected to the odd-numbered sub bit lines are alternately connected to the bank select signal lines GSL2 and GSL1. One ends of the even-numbered sub bit lines SBL2, SBL4,... Are connected to bank select transistors BST1, BST2,..., And two adjacent bank select transistors BST1, BST2,. ... are connected to the main bit lines MBL1, MBL2, ..., respectively. Gates of the bank select transistors BST1, BST2,... Alternately connected to the even-numbered sub-bit lines are alternately connected to the two bank select signal lines SSL2 and SSL1. In addition, the ground bit lines GBL1,..., GBLj are connected to a ground bit line selection circuit 20 controlled by the second decoder 25. The main bit lines MBL1,... MBLi are connected to the main bit line selection circuit 35 controlled by the third decoder 30.

A method of reading data stored in a memory cell is described below with reference to FIG. 1 configured as described above. It is assumed that the cell data of the memory cell M1 is read among the memory cells of FIG. 1. In this case, the bank select signal lines SSL1 and GSL1 of the odd and even sub bit lines are set to a logic level 'high', and the bank select signal lines of another odd and even sub bit line are set. The fields SSL2 and GSL2 are set to a logic level 'low'. The word lines are controlled by the first decoder 10 so that the word line WL1 is set high and the remaining word lines WLn are all set low (eg, GND level). The sense voltage applied through the sense amplifier circuit 40 is supplied to the main bit line MBL1 selected by the main bit line selection circuit 35, and the bias of the same level is applied to the unselected main bit line MBL0. Bias) voltage is supplied, and the remaining main bit lines MBL2 and MBLj are floated. On the other hand, the ground bit line GBL1 selected by the operation of the ground bit line selection circuit 20 connected to the second decoder 25 is set to the ground voltage, and other ground bit lines GBL0, GBL2, and GBLj are set. Are all in the floating state. The voltage application state includes the main bit line MBL1, the bank select transistor BST1 connected to the even-numbered sub bit line, the even-numbered sub bit line SBL2, and the memory cell M1. ), The odd-numbered sub bit line SBL1, the bank select transistor GST1 of the sub bit line SBL1, and the ground bit line GBL1 connected to the ground bit line select circuit 20, in turn. Form a current path. When the voltage level appearing on the main bit line MBL1 is sensed by the sense amplifier 40 in the above voltage application state, the cell data stored in the memory cell M1 is read.

When the above-described method is applied to the memory cell M2 to read the cell data stored in the memory cell M2, the bank select signal line GSL2 is set high and the bank select connected to the even-numbered sub bit line is selected. The bank select signal lines SSL1 are set high to select transistors, and the other bank select signal lines SSL2 and GSL1 are set low. The word line WL1 is set high and the remaining word lines WLn are set low. The sensing voltage is supplied to the main bit line MBL1, the bias voltage of the same level as the sensing voltage is supplied to the main bit line MBL0, and the ground bit line GBL1 is operated by the ground bit line selection circuit 20. Is supplied with ground voltage, and the other ground bit lines are floated. The voltage application state in this case is the main bit line MBL1, the bank select transistor BST1 connected to the even-numbered sub bit line, the even-numbered sub bit line SBL2, the memory cell M2, and the odd-numbered number. A current path is formed through the sub bit line SBL3, the bank select transistor GST2 connected to the odd sub bit line, and the ground bit line GBL1 connected to the ground bit line select circuit 20. Accordingly, the sense amplification circuit 40 senses and amplifies the cell data stored in the memory cell M2, and the data of the memory cell M2 is read.

This time, assuming that the cell data stored in the memory cell M3 is read, a sense voltage is supplied to the main bit line MBL1 and a bias voltage is supplied to the main bit line MBL0. The ground bit line GBL1 is grounded, and other ground bit lines are floated. The voltage application state includes the main bit line MBL1, the bank select transistor BST2 connected to the even sub bit line, the even sub bit line SBL4, the memory cell M3, and the odd sub bit. A current path through the line SBL3, the bank select transistor GST2 connected to the odd-numbered sub bit line, and the ground bit line GBL1 is formed to read the cell data stored in the memory cell M3.

When the memory cell M4 is read in the same manner as described above, the sensing voltage is supplied to the main bit line MBL1, and the bias voltage having the same level as the sensing voltage is supplied to the main bit line MBL0. The ground bit line GBL2 is grounded to ground voltage, and other ground bit lines are floated. According to the voltage application state, the main bit line MBL1, the bank select transistor BST2 connected to the even sub bit line, the even sub bit line SBL4, the memory cell M4, and the odd number A current path is formed through the sub bit line SBL5, the bank select transistor GST3 connected to the odd sub bit line, and the ground bit line GBL2 connected to the ground bit line select circuit 20. Cell data stored in the memory cell M4 is read through the sense amplifier circuit 40.

When each selected memory cell is read through the main bit line by the voltage application method as described above, a memory cell data read error may be generated as follows.

First, for a read operation, a sensing voltage and a bias voltage are respectively supplied to the selected main bit line MBL1 and the bias bit line MBL0, and the remaining main bit line MBLi is floated, and the selected ground bit line (GBL1) is grounded to the ground level, and the remaining ground bit lines GBL2 and GBL0 are in a floating state. In this state, assuming that the memory cell M2 is an " OFF " cell, the voltage level of the ground bit line GBL0 becomes a constant voltage level due to a coupling phenomenon in the read operation of the memory cell M2. That is, the voltage is coupled by the main bit line MBL0 receiving the bias voltage so that the voltage level of the ground bit line GBL0 is 1/2 of the voltage level of the main bit line MBL0. After all, the voltage level of the ground bit line (GBL0) is about half lower than the main bit line (MBL1), so the voltage of the main bit line (MBL1) along the path of "L5" which is the current path shown in FIG. The ground bit line GBL0 is applied to charge the ground bit line GBL0. Therefore, since the voltage level of the main bit line MBL1 is lowered, the cell data of the memory cell M2 which is an "OFF" cell can be read into an "ON" cell. In this way, a read malfunction occurs when the off cell is read with the data of the on cell.

Except for the memory cell M2, when the data of the memory cells M1, M3, and M4 are read, the floated ground bit line GBL2 receives the main bit line MBL1 receiving the sensed voltage and the bias voltage. Since the voltage is located between the main bit lines MBL2, the voltage level of the ground bit line GBL2 is equal to the voltage levels of the bit lines MBL1 and MBL2 due to the coupling phenomenon. Therefore, when reading the memory cells, a leakage current path is blocked, so that a read malfunction is unlikely to occur.

In order to solve a read malfunction problem when the memory cell M2 is an off cell when performing a read operation as shown in FIG. 1, a bias voltage is also applied to the ground bit line as shown in FIG. 2. Is taking. That is, in order to solve the problem caused by the off-cell characteristics of the memory cell M2, the sensing voltage and the bias voltage are supplied to the selected main bit line MBL1 and the bit line MBL2, respectively, and other main bit lines are provided. The ground bit line connected to the selected memory cell is grounded, but the bias voltage is supplied to the adjacent ground bit line GBL2. When the above voltage application condition is applied to Fig. 1, the current path " L5 "

However, the scheme as shown in Fig. 4 can solve the read malfunction by improving the " OFF " cell characteristics, but it causes another problem. In other words, when bias is applied to the ground bit line, the current flowing in the "ON" cell of the memory cells M1, M3, and M4 is weakened, thereby lowering the sensing margin. In other words, since the current path "L6" is formed due to the bias level applied to the ground bit line GBL2, the on-cell flowing through the current bit "L7" via the main bit line and the selected memory cell M1. The current is reduced. This causes a problem of lowering the current margin of the " ON " cell of the memory cell M1.

As described above, when the bias voltage is supplied to the ground bit line to improve the off-cell characteristics, the current path due to the applied bias level is undesirably generated, which causes a problem of deterioration of the on-cell characteristics during the read operation. . Therefore, if the current margin is out of the sensing margin of the sense amplifier circuit, there is still a problem that lead malfunction occurs.

Accordingly, an object of the present invention is to provide a semiconductor memory device and a driving method thereof, which can solve the above-mentioned problems.

Another object of the present invention is to provide an improved read method capable of minimizing read malfunction by optimally preventing deterioration of on-cell or off-cell characteristics.

According to an aspect of the present invention for achieving the above objects, a read method of a semiconductor memory device having a hierarchical bit line arrangement and having Noah-type flat memory cells includes one main bit through bank select transistors. A plurality of memory cells connected to a line may be separated by parts, and a bias voltage level applied to an adjacent ground bit line corresponding thereto may be differentially applied to each of the separated parts.                         

According to the present invention described above, it is possible to optimally prevent the deterioration of characteristics for the on-cell or off-cell to minimize the lead malfunction.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

In the present invention, a plurality of memory cells connected to the selected main bit line are distinguished by parts, and the bias level applied from the adjacent ground bit line is differentiated to minimize characteristic deterioration due to on-cell and off-cell during a read operation.

3 to 6 are characteristics deteriorated according to " ON " and " OFF " cell leads by distinguishing bias applied to the ground bit line during the data read operation of M1, M2, M3 and M4 of the memory cell according to the present invention. Figures showing solving the. It should be noted that the memory cell arrangement structure within the memory cell array in the drawings is the same as that of the conventional FIGS. 1 and 2 described above.

Hereinafter, a voltage application condition when reading data will be described with reference to FIG. 3. 3 illustrates a case where cell data of a memory cell M1 programmed on-cell is read. The bank select signal lines SSL1 and GSL1 of the odd and even sub bit lines are set high, and the bank select signal lines SSL2 and GSL2 of the remaining odd and even sub bit lines are set low. . The selected word line WL1 is set high and the remaining word lines are set low. The sense voltage is applied to the main bit line MBL1, the same bias voltage is applied to the neighboring main bit line MBL2, the ground bit line GBL1 is grounded to the ground level, and the neighboring ground bit line ( GBL2) is applied with a voltage level that is 1/2 of the bias level of the main bit line. Thus, the half voltage of the bias level is supplied along the current path " I3 ". In this state, the potential of the ground bit line GBL2 is equal to the main bit lines MBL1 and MBL2 due to the coupling effect between the main bit lines MBL1 and MBL2.

When the memory cell M1 is "ON", the voltage level of the ground bit line GBL2 is equal to the voltage level of the main bit lines MBL1 and MBL2, but the amount of current is equal to the main bit lines MBL1. Since it is relatively smaller than the amount of current flowing through the MBL2, it hardly affects the current path "I4" flowing from the main bit line MBL1 to the memory cell.

On the other hand, even in the case of FIG. 4 which leads the off-cell, if the voltage application condition of FIG. 3 is applied as it is, even if it is an "OFF" cell, a leakage current path is not generated by the main bit line MBL2, but in the main bit line MBL1. There is little effect on the current pass " I4 " flowing into the memory cell.

Since the memory cells M3 and M4 operate in the same manner as described above, the characteristics of both the "ON" and "OFF" cells can be improved.

Hereinafter, with reference to FIGS. 5 and 6, when the memory cell M2 is an on and off cell, a voltage application condition and a read operation will be described.

The bank select signal lines SSL1 and GSL1 of the odd and even sub bit lines are set high, and the bank select signal lines SS2 and GSL2 of the other odd and even sub bit lines are low. Is set. The word line WL1 is set high and the other word lines WLn are set low. The sensing voltage is applied to the main bit line MBL1, and the same bias voltage is applied to the neighboring main bit line MBL0. The ground bit line GBL1 is grounded to ground, and the neighboring ground bit line GBL0 has a different amount of bias voltage than that when the memory cells M1, M3, and M4 lead, for example, the main bit lines MBL0 and MBL1. Apply a voltage at the same level as the voltage applied to). In the above voltage applying state, the neighboring ground bit line GBL0 receives the same bias voltage as the main bit line MBL1 even though the coupling bit is influenced by the main bit line MBL0 supplying the bias. Since it receives through, no extra charge is required. As a result, the current path " L5 " shown in Fig. 1 of the prior art is not generated.

As such, since the ground bit line does not need to be separately charged, the characteristics of the "OFF" cell can be improved significantly without disturbing the characteristics of the "ON" cell.

As described above, in the present invention, the bias voltage level applied from the ground bit line is separately applied for each part of the memory cell in order to prevent deterioration of the characteristics of the "ON" and "OFF" cells of the memory cells connected to the main bit line. Therefore, it is possible to make all memory cells have the same characteristic as a whole.

As described above, the present invention has been described in detail only with respect to specific embodiments, but it is obvious to those skilled in the art that the present invention can be modified or changed within the scope of the technical idea of the present invention. It belongs to the scope of claims. For example, the level of the bias voltage applied to the ground bit line may be different from those of the embodiments, or the circuit configuration may be added or subtracted or replaced depending on the matter.

According to the present invention described above, it is possible to optimally prevent the deterioration of characteristics on or off cells, thereby minimizing lead malfunction.

Claims (8)

delete delete delete delete delete A certain number of word lines are arranged in a row direction, main bit lines and ground bit lines cross the word lines, and each of the main bit lines and ground bit lines is connected to a bank selection transistor for selecting a memory cell. In the semiconductor memory device having a plurality of the main bit line and the ground bit line forming a block, and having a memory cell array consisting of the plurality of blocks: In the one block, the main bit line and the ground bit line are constantly arranged in the same direction, the main bit line is connected to the main bit line selection control circuit, and the ground bit line is connected to the ground bit line selection control circuit. Become, The ground bit line selection control circuit and the main bit line selection control circuit are connected to a third decoder and a second decoder, Two or more bit lines are selected from the ground bit line selection control circuit and the main bit line selection control circuit. The main bit line selection control circuit is connected to a sense amplifier circuit and the ground bit line selection control circuit is connected to ground. The method of claim 6, wherein at least one ground bit line is connected to one or more ground grounds in the same block, and is different from a level of a bias voltage supplied to the main bit line when a bias is applied to at least one neighboring ground bit line. Apparatus characterized in that the supply. 8. The bias level of claim 7, wherein a bias level of supplying a portion of a plurality of memory cells selected by a bank selection transistor of the main bit line and the ground bit line to an adjacent ground bit line is supplied to the main bit line. Apparatus for selectively supplying at a voltage of 1/2.

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