KR100714637B1 - Method for manufacturing vertical structure light emitting diode - Google Patents

Abstract

Provided is a method of manufacturing a vertical light emitting diode that can prevent damage to a substrate. According to an aspect of the present invention, there is provided a method of manufacturing a vertical structure light emitting diode, including sequentially forming an n-type cladding layer, an active layer, a p-type cladding layer, and a p-side electrode on a growth substrate; Separating the resultant in which the p-side electrode is formed into a plurality of individual chip structures; Bonding the plurality of chip structures on a conductive substrate such that the p-side electrode faces a bonding surface; Removing the growth substrate from the plurality of chip structures bonded to the conductive substrate; Forming an n-side electrode on the n-type clad layer; Separating the conductive substrate into individual light emitting devices.

LED, light emitting diode, vertical structure

Description

Method for Manufacturing Vertical Structure Light Emitting Diode

1 is a cross-sectional view illustrating a conventional vertical structure light emitting diode manufacturing method.

2 to 9 are views for explaining a method for manufacturing a vertical structure light emitting diode according to an embodiment of the present invention, each of (a) is a plan view and (b) is a sectional view.

10 is a cross-sectional view of a light emitting diode manufactured according to a method of manufacturing a vertical structure light emitting diode according to another embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

101: sapphire substrate 102: light emitting structure

103: n-type cladding layer 105: active layer

107: p-type cladding layer 109: p-side electrode

121: conductive substrate 123, 124: metal layer

125: solder 126: groove

127: n-side electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor light emitting device, and more particularly, to a method of manufacturing a vertical structure light emitting diode capable of suppressing substrate damage caused by a difference in coefficient of thermal expansion during substrate bonding.

Light Emitting Diode (LED) using a GaN-based semiconductor represented by Al _x Ga _y In _(1-xy) N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) Has attracted attention as a light emitting device in the blue, green or ultraviolet region. Currently used GaN LEDs include a horizontal GaN LED and a vertical GaN LED. In the horizontal structure LED, since both the p-side electrode and the n-side electrode are disposed on the same side of the device, it is difficult to provide a sufficient light emitting area and is vulnerable to electrostatic discharge (ESD).

In order to overcome this disadvantage, a method of using thin vertical LEDs instead of horizontal LEDs has been proposed. In a vertical LED, the p-side electrode and the n-side electrode are disposed to face each other with semiconductor epitaxial layers therebetween. Vertical LEDs are typically manufactured through a bonding process of a conductive substrate (eg, a Si wafer or a GaAs wafer) in a wafer state and a separation process of a growth substrate (eg, a sapphire substrate) that is performed after the bonding process. Korean Laid-Open Patent Publication No. 2004-58479 discloses a method of manufacturing a vertical LED including a process of bonding a Si wafer and a process of separating a sapphire substrate. However, when the conductive substrate in the wafer state is bonded to the semiconductor layer, damage to the conductive substrate or the semiconductor layer is likely to occur due to the difference in thermal expansion coefficient between the conductive substrate and the semiconductor layer.

1 (a) to (e) are cross-sectional views illustrating a conventional method for manufacturing a vertical structure LED. First, as shown in FIG. 1A, an n-type cladding layer 13, an active layer 15, and a p-type cladding layer 17 are sequentially grown on a sapphire substrate 11 in a wafer state to emit light. Form the structure 12. Thereafter, the p-side electrode 19 is formed on the p-type cladding layer 17.

Next, as shown in FIG. 1B, the conductive substrate 21 in a wafer state such as a Si wafer is bonded to the p-side electrode 19 using a conductive adhesive layer 23 such as Au (wafer-to-wafer). Bonding process: wafer to wafer bonding). Thereafter, the sapphire substrate 1 is separated by irradiating a laser beam as shown in FIG. 1C (laser lift off process: laser lift off). Next, as shown in FIG. 1D, the n-side electrodes 25 are formed on the n-type cladding layer 13 and cut into individual elements as shown in FIG. 1E. in d) line A represents the cutting line). As a result, the vertical structure LED 10 is obtained.

However, when the conductive substrate is bonded to the p-side electrode by the wafer-to-wafer bonding method as described above, damage such as cracking of the conductive substrate is likely to occur due to the difference in thermal expansion coefficient. In addition, the wafer-to-wafer bonding method described above tends to be poor in alignment with a pre-patterned conductive substrate. The thickness of the conductive substrate or the sapphire substrate can be reduced to reduce the damage of the conductive substrate, but in this case, an additional process is additionally required and the damage thereof is not effectively suppressed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a vertical structure light emitting diode that can effectively and easily prevent damage to a conductive substrate generated during the bonding process of a conductive substrate. .

In order to achieve the above technical problem, the manufacturing method of the vertical structure light emitting diode according to the present invention comprises the steps of sequentially forming an n-type cladding layer, an active layer, a p-type cladding layer and a p-side electrode on the growth substrate; Separating the resultant in which the p-side electrode is formed into a plurality of individual chip structures; Bonding the plurality of chip structures on a conductive substrate such that the p-side electrode faces a bonding surface; Removing the growth substrate from the plurality of chip structures bonded to the conductive substrate; Forming an n-side electrode on the n-type clad layer; Separating the conductive substrate into individual light emitting devices.

According to an embodiment of the present invention, the n-type cladding layer, the active layer and the p-type cladding layer are Al _x Ga _y In _(1-xy) N (0≤x≤1, 0≤y≤1, 0≤x + y ≤1) formed of a semiconductor material. In this case, a sapphire substrate can be used as the growth substrate.

The conductive substrate may be a Si substrate, a GaAs substrate, or a SiC substrate. Alternatively, the conductive substrate may be a metal substrate such as Al, Cu, or W.

According to a preferred embodiment, prior to the bonding step of the chip structure, the conductive substrate may be patterned to form a groove on the upper surface. In this case, the groove may be formed around the junction of the chip structure.

Before the bonding step of the chip structure, a metal layer may be formed on the bonding surface of the conductive substrate. In addition, a metal layer may be formed on the opposite surface of the bonding surface of the conductive substrate.

According to the present invention, the manufacturing method may further include packaging each of the light emitting devices after separating the conductive substrate into individual light emitting devices.

According to one embodiment of the invention, the manufacturing method further comprises the step of forming a metal layer on the bonding surface of the conductive substrate before the bonding step of the chip structure, in the packaging step is connected to the n-side electrode of the light emitting device A first bonding wire and a second bonding wire connected to the metal layer may be formed.

According to another embodiment of the present invention, the manufacturing method includes forming a conductive via penetrating the conductive substrate before the bonding step of the chip structure; The method may further include forming upper and lower metal layers on the bonding surface and the opposite surface of the conductive substrate, respectively, to electrically connect the upper and lower metal layers by the conductive vias. In this case, a bonding wire connected to the n-side electrode of the light emitting device may be formed in the packaging step.

According to the present invention, by using a chip-to-wafer bonding process instead of the conventional wafer-to-wafer method, it is possible to effectively prevent substrate damage such as substrate breakage when bonding a conductive substrate. Therefore, the stress on the individual chips can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings are the same elements.

2 to 9 are views for explaining a method of manufacturing a vertical structure light emitting diode according to an embodiment of the present invention. 2-8, (a) shows a top view and (b) shows a side cross-sectional view. In this embodiment, a sapphire substrate is used as a growth substrate, and a GaN-based semiconductor (that is, Al _x Ga _y In _(1-xy) N (0≤x≤1, 0≤y≤1, 0 ≦ x + y ≦ 1)), but the present invention is not limited thereto.

First, referring to FIG. 2, an n-type GaN cladding layer 103, an active layer 105, and a p-type GaN cladding layer 107 are grown on a sapphire substrate 101 having a wafer shape. Accordingly, the light emitting structure 102 formed on the substrate 101 is obtained. After that, as shown in FIG. 3, the p-side electrode layer 109 is formed on the p-type GaN cladding layer 107. The p-side electrode layer 109 may be patterned to be separated for each device region.

Next, referring to FIG. 4, a substrate in a wafer state on which the p-side electrode layer 109 is formed is diced for each device region to obtain a plurality of separated chip structures 110 (line B of FIG. 3B). Indicates a cutting line). Each chip structure 110 includes a sapphire substrate 101, a light emitting structure 102, and a p-side electrode 109.

Meanwhile, as shown in FIG. 5, a conductive substrate 121 in a wafer form is prepared. The upper surface of the conductive substrate 121 may be patterned to have the groove 126. The part (convex part) enclosed by the groove part corresponds to a junction part in a later joining process. The metal layer 123 may be formed on the upper surface of the patterned conductive substrate 121. In addition, the solder 125 may be previously formed on the convex portion of the metal layer 123 to bond the chip structure 110 and the conductive substrate 121. The metal layer 124 may also be formed on the lower surface of the conductive substrate 121. The metal layer 124 formed on the lower surface of the conductive substrate 121 may form one terminal of the light emitting diode (see FIG. 10). The conductive substrate 121 / metal layers 123 and 124 / solder 125 may be prepared in advance before the chip structure 110 is formed.

As the conductive substrate 121, for example, a Si substrate, a GaAs substrate, or a SiC substrate can be used. Alternatively, a metal substrate such as Al, Cu, or W may be used as the conductive substrate 121. As the metal layers 123 and 124, a metal such as Au or Ag may be used, and as the solder 125, Au—Sn or Sn may be used.

Thereafter, as shown in FIG. 6, the separated plurality of chip structures 110 are bonded to the junction of the conductive substrate 101 in the form of a wafer. That is, the p-side electrode 109 of each chip structure 110 is bonded to the bonding portion (convex portion) of the conductive substrate 121 using the solder 123. At this time, heat (or heat and pressure) is applied for adhesion by soldering. As described above, in the bonding process according to the present invention, the structure 110 in the chip state is bonded to the conductive substrate 121 in the wafer state. By using such a chip-to-wafer bonding process, it is possible to effectively suppress cracking of the conductive substrate, which has been frequently generated in the past.

When performing the bonding process by the conventional wafer-to-wafer method, due to the difference in thermal expansion coefficient between the conductive substrate and the semiconductor layer, significant stress is applied to the "wafer state" semiconductor layer bonded to the conductive substrate. Due to such stress, cracking of the conductive substrate is likely to occur. In addition, when the conductive substrate is previously patterned, it is difficult to accurately align the wafer-to-wafer bonding process.

However, by bonding the structure 110 in the chip state to the conductive substrate 121 in the wafer state (chip-to-wafer method) as in the present invention, the stress applied to the conductive substrate 121 and the semiconductor layer 102 is remarkable. Can be reduced. As a result, damage to the conductive substrate is effectively suppressed. In addition, since each individual chip structure 110 is bonded to the bonding surface of the conductive substrate 121, the problem of mis-alignment hardly occurs. In addition, since the upper surface of the conductive substrate 121 is patterned as described above, it is possible to prevent short-circuit caused by solder sticking out of the light emitting structure 102 during bonding.

Next, as shown in FIG. 7, the sapphire substrate 101 is removed from the chip structure 110. The sapphire substrate 101 may be separated and removed using a laser lift off (LLO). That is, the sapphire substrate 101 can be separated from the n-type cladding layer 103 by irradiating a laser beam to the interface between the sapphire substrate 101 and the GaN-based light emitting structure 102. In this case, since the sapphire substrate 101 is removed from the chip-shaped structure 110 instead of the wafer, the nitride gas generated at the time of LLO may be more easily discharged than in the prior art (FIG. 1C). .

After removal of the sapphire substrate 101 using LLO or the like, an n-side electrode 127 is formed on the exposed surface of the light emitting structure 102 (that is, on the n-type cladding layer 103) (Fig. b)). As a result, a vertical light emitting device assembly is obtained (see FIG. 7). For convenience, the n-side electrode is not shown in FIG.

Next, as shown in FIG. 8, the conductive substrate 121 is cut or separated into individual elements to obtain a plurality of light emitting devices 100 (line C in FIG. 7 represents a cutting line). The light emitting device 100 corresponds to a vertical GaN-based light emitting diode (that is, the n-side electrode and the p-side electrode are disposed to face each other between the light emitting structures 102. Negative (n) from the n-side electrode 127 The terminal can be taken out and the positive terminal can be taken out from the conductive substrate 121 connected with the p-side electrode 109.

The light emitting device 100 of FIG. 8 may be appropriately packaged through chip bonding, wire bonding, and molding steps. For example, as shown in FIG. 9, the n-side electrode 127 and the p-side electrode 109 may be connected to an external wiring structure such as a lead frame by using two wires 130 and 131 in a packaging process. . Specifically, the n-side electrode 127 may be connected to an external terminal (− terminal) through the first bonding wire 130, and the p-side electrode 109 may be a second bonding wire 131 connected to the metal layer 123. It can be connected to the other external terminal (+ terminal) through).

10 is a cross-sectional view of a vertical structure light emitting diode manufactured according to another embodiment. In this embodiment, the conductive via 124 penetrating the conductive substrate 121 is formed. The step of forming the conductive via 124 may be performed before the step of bonding the chip structure (see FIG. 6). The conductive via 124 may be filled with a material of high conductivity (eg, Cu, Ag, etc.). The conductive via 124 connects the upper and lower metal layers 123 and 124 to each other, thereby connecting the p-side electrode 109 to the lower metal layer 124. Accordingly, it is not necessary to separately form a bonding wire for connecting the p-side electrode 109 in the packaging step, and only one bonding wire 130 connected to the n-side electrode 127 needs to be formed.

It is intended that the invention not be limited by the foregoing embodiments and the accompanying drawings, but rather by the claims appended hereto. In addition, the present invention may be substituted, modified and changed in various forms without departing from the technical spirit of the present invention described in the claims.

As described above, according to the present invention, by using a chip-to-way bonding process, it is possible to effectively prevent substrate damage such as cracking of the conductive substrate and to significantly reduce stress on individual chips. In addition, since the chip-to-wafer method, the alignment state is good at the time of bonding. In addition, patterning of the conductive substrate effectively prevents short circuits due to solder. Furthermore, the nitride-based gas generated when the growth substrate is removed using the LLO may be more easily discharged.

Claims (15)

delete delete delete Sequentially forming an n-type cladding layer, an active layer, a p-type cladding layer and a p-side electrode on the growth substrate; Separating the resultant in which the p-side electrode is formed into a plurality of individual chip structures; Bonding the plurality of chip structures on a conductive substrate such that the p-side electrode faces a bonding surface; Removing the growth substrate from the plurality of chip structures bonded to the conductive substrate; Forming an n-side electrode on the n-type cladding layer; And Separating the conductive substrate into individual light emitting devices, And the conductive substrate is formed of a material selected from the group consisting of Si, GaAs and SiC. delete Sequentially forming an n-type cladding layer, an active layer, a p-type cladding layer and a p-side electrode on the growth substrate; Separating the resultant in which the p-side electrode is formed into a plurality of individual chip structures; Bonding the plurality of chip structures on a conductive substrate such that the p-side electrode faces a bonding surface; Removing the growth substrate from the plurality of chip structures bonded to the conductive substrate; Forming an n-side electrode on the n-type cladding layer; And Separating the conductive substrate into individual light emitting devices, Before the bonding step of the chip structure, further comprising the step of patterning the conductive substrate to form a groove on the upper surface of the conductive substrate, And the groove is formed around a region to which the chip structure is to be bonded. Sequentially forming an n-type cladding layer, an active layer, a p-type cladding layer and a p-side electrode on the growth substrate; Separating the resultant in which the p-side electrode is formed into a plurality of individual chip structures; Bonding the plurality of chip structures on a conductive substrate such that the p-side electrode faces a bonding surface; Removing the growth substrate from the plurality of chip structures bonded to the conductive substrate; Forming an n-side electrode on the n-type cladding layer; And Separating the conductive substrate into individual light emitting devices, Before the bonding step of the chip structure, the vertical structure light emitting diode manufacturing method comprising the step of forming a metal layer on the bonding surface of the conductive substrate. The method of claim 7, wherein And forming a metal layer on an opposite side of the bonding surface of the conductive substrate before the bonding of the chip structure. Sequentially forming an n-type cladding layer, an active layer, a p-type cladding layer and a p-side electrode on the growth substrate; Separating the resultant in which the p-side electrode is formed into a plurality of individual chip structures; Bonding the plurality of chip structures on a conductive substrate such that the p-side electrode faces a bonding surface; Removing the growth substrate from the plurality of chip structures bonded to the conductive substrate; Forming an n-side electrode on the n-type cladding layer; And Separating the conductive substrate into individual light emitting devices, And after separating the conductive substrate into individual light emitting devices, packaging each of the light emitting devices. The method of claim 9, Before the bonding step of the chip structure, further comprising the step of forming a metal layer on the bonding surface of the conductive substrate, And in the packaging step, forming a first bonding wire connected to the n-side electrode of the light emitting device and a second bonding wire connected to the metal layer. The method of claim 9, Forming a conductive via penetrating the conductive substrate before bonding the chip structure; And And forming upper and lower metal layers on junction surfaces of the conductive substrate and opposite surfaces thereof, respectively, so that the upper and lower metal layers are electrically connected by the conductive vias. Way. The method of claim 11, And manufacturing a bonding wire connected to the n-side electrode of the light emitting device in the packaging step. The method of claim 9, The n-type cladding layer, the active layer and the p-type cladding layer are formed of an Al _x Ga _y In _(1-xy) N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) semiconductor material. Vertical structure light emitting diode manufacturing method characterized in that. The method of claim 9, The growth substrate is a vertical structure light emitting diode manufacturing method, characterized in that the sapphire substrate. The method of claim 9, The conductive substrate is a vertical structure light emitting diode manufacturing method, characterized in that the metal substrate.

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