KR100714275B1 - Embedded capacitor - Google Patents

Abstract

The present invention relates to an embedded capacitor, and provides an embedded capacitor for a printed wiring board on which nanopore arrays are formed by anodization. According to the invention, the process temperature is lowered below 200 ° C. and the capacitance density is 300 nF / cm ^2. A new concept of embedded capacitors can be manufactured. The aluminum / alumina nanopore capacitor formed on the silicon substrate embodied by the present invention observed a capacitance density of 86 nF / cm ^{2 by} a 150 μm diameter upper pad, 10 MHz measurement.

Embedded Capacitors, Anodic Oxidation, Aluminum, Titanium, Printed Wiring Boards (PWB)

Description

Embedded Capacitors {EMBEDDED CAPACITOR}

1 is a graph showing the correlation between dielectric constant and dielectric breakdown voltage of a dielectric material.

Figure 2 is a schematic diagram of alumina nano pores formed by the anodization method according to the present invention.

Figure 3 is a schematic diagram of a metal oxide thin film nano-pore embedded capacitor, the specific surface area and the thickness of the oxide thin film is controlled in accordance with the present invention.

4A and 4B are schematic diagrams and actual pictures showing a process of controlling oxide nano pore pitch by nano stamping.

Figures 5a to 5c is a schematic diagram showing the appearance of controlling the various types of alumina nano-pores and residual aluminum form.

6a to 6e is a process chart showing a two-step anodization process according to an embodiment of the present invention.

Figures 7a to 7c is a schematic diagram and photograph showing a microstructure controlled pore shape in accordance with an embodiment of the present invention.

8A and 8B are photographs showing the surface and interfacial microstructure of alumina nanopores with controlled aspect ratios.

*** Explanation of symbols for the main parts of the drawing ***

10: substrate 11: lower electrode

12a: metal seed layer 12b: metal pillar

13: metal oxide thin film 14: upper electrode

The present invention relates to a built-in capacitor, and to a thin film type built-in capacitor for a printed wiring board formed nanopore array by anodization.

As computers get faster, signal transmission speeds get faster and malfunctions get smaller. Increasing the signal transmission speed of a printed wiring board (PWB) equipped with a central computing device and an integrated circuit chip is required.

Until now, most printed wiring board surfaces have a general discrete chip resistor or individual chip capacitor. However, recently, printed wiring boards incorporating passive elements such as resistors or capacitors have been developed.

This passive element embedded printed wiring board technology replaces the role of the existing chip resistors and chip capacitors by inserting passive elements such as resistors or capacitors into the outer or inner layers of the substrate using new materials and new processes. The passive printed circuit board includes a passive element, for example, a capacitor, buried inside or outside of the substrate itself. If the passive capacitor is integrated as part of the printed wiring board regardless of the size of the substrate itself, the embedded capacitor ( embedded capacitor). The most important feature of the embedded printed wiring board is that since the capacitor is inherently provided as part of the printed wiring board, no additional capacitor mounting is necessary.

Embedded capacitors, which provide stable operating power to the device, use a stacked structure with double-sided copper clad laminates on both sides of the capacitor material. These capacitors are formed on FR-4 insulator material with glass cloth impregnated with epoxy resin.

Conventionally, embedded capacitors formed by forming a dielectric material between upper and lower copper foil layers form a dielectric material at a high temperature of 600 ° C. or higher on a copper foil, and then clad the capacitor / copper layer on the FR-4 substrate, and patterning. To produce a final printed wiring board. Until now, we have focused on the development of high-k dielectric materials such as PbZrTiO ₃ (dielectric constant 2000) and BaTiO ₃ , which can be developed in copper foils that withstand high temperatures above 600 ° C, or in low temperature processes below 600 ° C that can withstand conventional copper foils. .

As a process technology to date, a technique of forming by using a high dielectric constant powder and a polymer composite, screen printing, ink-jet technology, etc. has been used, but these technologies have a high process temperature or a capacity The disadvantage is that the capacitance density value is low.

Accordingly, it is an object of the present invention to provide a new concept of embedded capacitor materials and manufacturing processes that can lower the process temperature to 200 ° C. or less and further enhance capacitance density.

In order to achieve the above object, the present invention is formed on a substrate, a first electrode layer on the substrate, a metal layer formed on the first electrode and including a columnar nano-pore array, and formed on the surface of the metal layer and nano-pore array Provided is a built-in capacitor comprising a metal oxide layer, and a second electrode layer formed on the metal oxide layer.

The metal layer is composed of any one material selected from Al, Ti, Ta, Zr, and the metal oxide layer is obtained by anodizing the metal layer and in Al ₂ O ₃ , TiO ₂ , Ta ₂ O ₅ , ZrO ₂ It is composed of any one material selected.

The present invention also forms a first electrode layer on a substrate, a metal layer formed of any one selected from Al, Ti, Ta, and Zr on the first electrode, and anodized the metal layer to form pillar-shaped nanoparticles. Forming a pore array and at the same time to form a metal oxide layer on the surface of the metal layer and nano-pore array, and forming a second electrode layer on the metal oxide layer provides an embedded capacitor manufacturing method.

The method may further include forming an anodization starting point with a nano array probe on the surface of the metal layer.

The anodization step may be performed in a two-step process of first performing anodization to form nanopore arrays, removing the nanopore arrays, and performing anodization secondly.

Anodic oxidation is a technique of surface treatment by adding an anode to a treatment object and a cathode to a solution. Anodization is commonly used as a surface treatment technique for aluminum alloys, and it improves corrosion resistance, durability, and adhesion depending on the type of solution used after oxidation treatment. Most of the anodizing treatment results in an uneven surface of the porous surface. The porous surface by this anodizing treatment increases the surface area to improve adhesion to subsequent membranes or to impart color by injecting various dyes into the porous surface. You may. In addition, the characteristics of the known metal may vary depending on the type of various solutions used in the anodizing coating. In the case of representative chromic acid, the corrosion resistance is excellent and in the case of phosphoric acid, the adhesion is excellent.

In the present invention, such anodization is appropriately used to improve the structure of the embedded capacitor, thereby increasing the area of the dielectric layer and making the thickness uniform. The result is a high-capacity embedded capacitor with high capacitance density, high dielectric breakdown potential, and particularly low process temperatures for easy matching with copper electrodes. In addition, a room temperature process is also possible, and various substrate materials may be used without limitation to the substrate used.

The present invention uses the materials shown in Table 1 as a material capable of anodizing among the various materials shown in FIG. Fig. 1 shows the correlation between dielectric constant and breakdown field of dielectric materials usable for printed wiring boards, and the values of dielectric constant and dielectric breakdown potential satisfy ε _{r ·} E _BR ² = 400. The choice of the best can do material is important.

The capacitance value is proportional to the dielectric constant and the electrode width, and is inversely proportional to the dielectric thickness. The material shown in Table 1 has a large specific surface area of the formed oxide layer, thereby achieving a high capacitance value.

[Table 1] Characteristics of Metal Oxide Dielectrics Producible by Anodization

Al ₂ O ₃ TiO ₂ Ta ₂ O ₅ ZrO ₂ Dielectric Constant @ 1 kHz 9.3-11.5 110.0 11.6 12.5 Dielectric loss 5 x 10 ^-4 Melting point (of metal) 660 1,668 2,996 1,852 Unit price (arbitrary unit) 10 20 30 40

The structure of the high capacitance density embedded capacitor according to the present invention is shown in FIG. 2. A metal oxide (Al ₂ O ₃ ) is formed as a dielectric layer on the metal layer (Al in this embodiment) by anodization. This metal oxide layer is in the form of a porous thin film, but the specific surface area is large, but if the process is not properly controlled, the metal may be difficult to remain under the metal oxide layer.

In the present invention, the metal layer remains under the metal oxide layer formed by anodization so that the capacitance density can be improved while serving as a lower electrode. Referring to FIG. 3, a thin film of the lower electrode 11 is formed on the substrate 10, and a metal seed layer 12a is formed on the lower electrode 11. The metal seed layer 12a is partially oxidized by anodic oxidation to form a metal oxide thin film 13 thereon, while a metal seed layer remains below the metal oxide thin film to form a metal pillar 12b. . The metal pillar 12b and the metal oxide thin film 13 form a nano-sized columnar pore array, thereby increasing the area of the entire metal oxide thin film 13. In addition, the thickness of the metal oxide thin film 13 is very uniform, so that a high capacitance density can be obtained. An upper electrode 14 is formed on the metal oxide thin film 13.

Various materials may be used as the substrate 10. Since the process temperature of the present invention is low and the process may be performed at room temperature, various polymer materials may be used. Each of the layers can be formed by a variety of thin film manufacturing method, and there is no particular limitation in the present invention. The lower electrode 11 and the upper electrode 14 may be a metal having excellent conductivity, and copper was used in the embodiment of the present invention. In addition, the metal seed layer 12a may use any one selected from metals associated with the materials listed in Table 1, that is, Al, Ti, Ta, and Zr.

As shown in FIG. 3, the additional metal is proposed in the present invention so that the pillar-shaped metal remains under the metal oxide thin film 13 to facilitate nanopore array formation. Referring to FIGS. 4A and 4B, an anodization process is performed after forming an initial point of anodization (see FIG. 4B) on the surface of the metal seed layer 12a using an external tool having a nano-sized probe (see FIG. 4A). When performed, it was confirmed that it is very easy to obtain the same structure as the metal pillar 12b of FIG. 3. As described above, according to the present invention, in order to control the shape of the lower metal layer of the metal oxide thin film 13 and to implement a large area capacitor, the gap of the nano pores of the metal oxide thin film may be controlled.

On the other hand, by controlling the type, pH, amount of use, etc. of the electrolyte used for anodization, it is possible to control the nano-pore form and the metal residue of the metal oxide. 5a to 5c, a weak acid to neutral solution can form a very dense oxide layer without pores on the metal layer (FIG. 5a) and the thickness of the oxide depends on the applied voltage. On the other hand, the use of a stronger acidic solution results in the formation of an oxide layer having a pore structure of constant size (FIG. 5b). Furthermore, in the case of using a very strong acid solution, the pores become large in proportion to the treatment time, and the metal layer is etched rather than the oxide layer is formed (FIG. 5C).

Table 2 shows the types, concentrations, applied voltages, and representative pore diameters of the anodization solutions used in the examples of the present invention.

Table 2 Anodizing Solution Composition and Process Conditions

Anodizing solution Concentration (mol%) Voltage (V) Pore diameter (nm) Sulfuric acid 0.5 25 30 Oxalic acid 0.3 40 45 Phosphoric Acid 1.0 160 400

6A to 6E illustrate a process of controlling the pore shape by anodizing aluminum metal according to an embodiment of the present invention. In this embodiment, a uniform porous aluminum oxide (alumina) thin film is formed by two-stage anodization. Such two-stage anodization can implement an array of tens of nanometers diameter pores having a very excellent alignment. .

First, an aluminum thin film is formed on a substrate (using silicon in this embodiment) as shown in FIG. 6A. In order to apply an electric field for anodization, a large amount of doping may be performed on the substrate or a lower electrode may be formed separately. Further surface treatment may be performed to form high quality alumina nanopores (FIG. 6B). Next, as shown in FIG. 6C, aluminum is anodized to form an alumina nanoporous layer primarily, and the alumina pore layer formed primarily is removed (FIG. 6D). By removing the alumina pore layer formed in this way, a well-aligned anodization starting point can be obtained. Subsequently, secondary anodic oxidation as shown in FIG. 6E may form high-quality alumina nanopores having excellent alignment.

Such two-stage anodization is because the structure of the anodized nanopore layer formed primarily is irregular, so that the pore shape is uniformly aligned by anodic oxidation process after removing the first nanoporous layer. 7A through 7C, the shape of the alumina nanopores formed primarily is irregular as shown in FIG. 7A. However, the alumina nanoporous layer is removed as shown in FIG. After the formation, the secondary anodization is performed to obtain a well-aligned alumina nanoporous layer as shown in FIG. 7C.

The aspect ratio and pore shape of the nano pores of the metal oxide layer obtained by the anodization process on the metal layer can be effectively controlled through the base material and the multi-step process to be used.

The surface and cross section of the finally formed alumina nanopores are shown in FIGS. 8A and 8B. 0.4 mol% phosphoric acid was used as the anodizing solution, and when the applied voltage was different, the pore size was in the range of 52-75 nm when the voltage of 30 V was applied (8a), and the pore size was 120- 150 nm range.

As described above, after forming an Au upper electrode having a diameter of 150 μm on the porous alumina formed by the anodic oxidation method and measuring the capacitance density at 10 MHz, a capacitance density of 86 nF / cm ² was obtained. Further improved values can be obtained by controlling the size and shape of the nanopores.

As described above, the present invention can manufacture a built-in capacitor having a high capacitance density using a low temperature process of 200 ° C. or less and various kinds of substrate materials. By utilizing these built-in capacitors, it will be possible to develop high-performance printed wiring boards.

Claims (7)

A first electrode layer having regular irregularities formed on an upper surface thereof; A metal oxide layer having a uniform thickness formed on the first electrode layer; And And a second electrode layer formed on the metal oxide layer. Built-in capacitor. The built-in capacitor of claim 1, wherein the first electrode layer is made of any one material selected from Al, Ti, Ta, and Zr. The built-in capacitor of claim 1, wherein the metal oxide layer is made of any one material selected from Al ₂ O ₃ , TiO ₂ , Ta ₂ O ₅ , and ZrO ₂ . Forming a first electrode layer of any one material selected from Al, Ti, Ta, Zr on the substrate, By anodizing the first electrode layer to form regular irregularities on the top surface of the first electrode layer, a metal oxide layer having a uniform thickness is formed on the first electrode layer on which the irregularities are formed. Forming a second electrode layer on the metal oxide layer; Built-in capacitor manufacturing method. The method of claim 4, further comprising forming an anodization starting point with a nano array probe on the surface of the first electrode layer. The method of claim 4, wherein the anodizing step is performed by first anodizing to form a nanopore array, removing the nanopore array, and performing anodization secondly. The method of claim 4, wherein the substrate is a polymer material, and the metal oxide layer is formed at a maximum of 200 ° C. 6.

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