KR100707230B1 - CDR Circuit and PLL Circuit - Google Patents

Abstract

Commonly used CDRs have the advantage of being easy to understand and simple to implement. Its operation generates the desired frequency by an external clock and compares it with the data to adjust the phase so that the clock boundary is in the middle of the data, restoring the data. This structure has the disadvantage that when switching from coarse loop to fine loop, the frequency that should not be changed is changed due to the bandwidth problem. In other words, if the bandwidth is wide, not only the phase but also the frequency is changed. In order to prevent this, it is possible to set a separate loop filter or two VCOs. In this case, the size increases and a problem of mismatch occurs. In addition, a lock detector is placed to switch the fine loop from the coarse loop. The lock of the first cycle fails due to the acquisition time of the PLL. Therefore, the lock time of CDR becomes long, and if you reduce the number of lock detectors to prevent this, you cannot meet the spec of given frequency.

The proposed method to solve the problem of CDR is as follows.

First, the existing lock detector is modified to generate a signal that can predict the lock signal in advance, and by using this, the lock time of the CDR is reduced while maintaining the PPM spec of the clock that the lock detector can determine.

Second, by using the signal that predicts the lock signal in advance, the loop bandwidth is gradually adjusted so that the frequency does not change when switching from coarse loop to fine loop and the jitter characteristic is improved. There are two ways to adjust the bandwidth: controlling the amount of current in the current pump, adjusting the resistance and capacitor, and the lock detector that generates the signal predicting the lock signal in the CDR and the method using the predicted signal. , PLL, CDR can be applied to all.

In particular, the method of dynamically adjusting the capacitance of the capacitor in the loop filter to control the loop bandwidth and consequently improving stability has the advantage of being relatively easy to implement. The goal here is to implement a CDR that takes into account all three of these factors, which can be applied independently or in an organic way.

PLL, CDR, Charge Pump, Lock Detector

Description

CDR and PLL circuits {CDR Circuit and PLL Circuit}

1 is a block diagram showing a CDR of a general structure,

2 is a block diagram illustrating a general serial transmitter structure;

3 is a block diagram showing a general receiver structure;

4 is a block diagram showing a PLL circuit using a charge pump;

5 is a graph showing a characteristic curve of the VCO in the circuit of FIG.

6 is a block diagram and timing diagram illustrating an embodiment of the charge pump of FIG. 4;

7 is a block diagram illustrating the PLL circuit of FIG. 4;

8 is a circuit diagram illustrating an embodiment of a loop filter of FIG. 4;

9 is a block diagram showing a CDR of a double loop structure,

10 is a circuit diagram illustrating an embodiment of a loop filter of FIG. 9;

11 is a circuit diagram illustrating an embodiment of a loop filter according to the spirit of the present invention;

12 is a circuit diagram showing another embodiment of a loop filter according to the spirit of the present invention;

13 is a circuit diagram for explaining the principle of a loop filter according to the spirit of the present invention;

14 is a cross-sectional view showing a structure of a MOS capacitor used in FIG.

15 is a circuit diagram showing an embodiment of a charge pump according to the spirit of the present invention;

16 is a circuit diagram illustrating an embodiment of a lock-prediction unit according to the spirit of the present invention.

The present invention relates to a clock / data recovery circuit, and more particularly, to a clock / data recovery circuit for setting frequency and phase to input data. It also relates to a PLL circuit used in the clock / data recovery circuit.

With the development of semiconductor processing technology, the amount of information that can be processed in one chip is increasing exponentially. For example, the current Pentium processor has tens of millions of transistors integrated and runs at a 3.2GHz clock. However, due to the limited number of pins and poor channel conditions such as PCBs and cables, the amount of data exchanged by the chip with external systems cannot keep up with the data throughput within the chip. So, up to now, what determines the operating speed of the entire system is not the operating speed inside the chip, but the channel bandwidth between the chips.

For this reason, researches to develop high-speed data transceivers between chips have been actively conducted. There are two ways to send a large amount of data from a data transceiver. One method is to increase the number of transmission channels to increase the parallel transmission unit to increase the overall data bandwidth, the other method is to transfer data at high speed through one channel. Increasing the parallel transmission unit has a limitation of using a large number of pins limited to the chip. In addition, data is sent through multiple channels and clocked through other channels. Even if the transmitter sends data at the same time, the mismatch between each channel causes the time for each signal to arrive at the receiver, which reduces the timing margin for data recovery. There is this. In the case of serial transmission, in order to solve the disadvantage that the timing margin in parallel transmission is reduced, only one channel is used to transmit high-speed data with a clock. Therefore, since the clock is not transmitted separately using another channel, the receiver recovers the clock using the received data stream, and uses the clock to sample the data stream again to recover the data. PC and network fields are representative of these data communication applications. In the serial transmission, a block called a clock and data recovery circuit (CDR) is used at the receiving end. The principle of the clock and data recovery circuit is as follows.

Data sent from the transmitter of FIG. 1 is transmitted through a channel and received by the receiver of FIG. Since most channels have limited bandwidth, when the data is sent at high speed, the waveform received by the receiver is somewhat distorted. The receiver restores the clock based on the received waveforms and restores the data using the clock. The CDR circuit plays a very important role in restoring clock and data. A well designed part is a very important quality parameter for serial transmission. Currently, a structure using a PLL (Phase Locking Loop) circuit principle is used for this purpose.

As shown in FIG. 3, a typical PLL circuit includes a phase detector and a voltage controlled oscillator. The phase detector detects the phase relationship between the restored clock and the input reference clock, and accordingly, the charge pump sends an appropriate current to the loop filter to change the control voltage of the voltage controlled oscillator. The voltage controlled oscillator generates a clock whose oscillation frequency is proportional to the control voltage, and then checks this modified generated clock and the next input clock and phase. This feedback causes the recovered clock, which is the output of the voltage controlled oscillator, and the incoming data to be in phase.

Figure 4 shows the structure of a CDR circuit which is generally widely used in accordance with the prior art. This has the advantage of being easy to understand and simple to implement. The operation of the CDR circuit generates a desired frequency by an external clock, compares it with data, and adjusts a phase so that an edge of the clock is in the middle of the data, thereby restoring data. To this end, a coarse loop for matching frequencies in the macro range and a fine loop for matching phases in the micro range are provided.

The disadvantage of the double loop structure according to the prior art is that when switching from a curse loop to a fine loop, a frequency that should not be changed due to a bandwidth problem is changed. In particular, if the bandwidth of the curse loop is wide, there is a problem that the frequency as well as the phase is easily changed. To prevent this, a low pass filter (LPF) may be set apart or two voltage controlled oscillators (VCOs) may be provided. In this case, the chip size may be increased and mismatch elimination may be complicated.

On the other hand, a lock detector is provided to switch the fine loop from the curse loop, and the lock of the first period is failed due to the acquisition time of the PLL circuit. Therefore, there is also a problem that the lock time of the CDR circuit becomes long. To prevent this, reducing the number of lock detector counts will prevent the specs of a given frequency from meeting.

Since the input data is a variable data value rather than a clock, no transition occurs every clock period. When the phase / frequency detector (PFD) attempts to adjust the correct phase and frequency, the frequency decreases again in the continuous data portion. This is because ripples are excessively generated at the output frequency, so that the phase and frequency cannot be exactly matched with the phase / frequency detector (PFD) alone. This is because the phase detector PD cannot be used in the initial state where the frequency of the input data cannot be determined because the signals to be compared can operate only when the frequencies are similar to some extent.

The present invention has been made to solve the above problems, and an object thereof is to provide a CDR circuit in which the extraction frequency does not vary with bandwidth.

Another object of the present invention is to provide a CDR circuit capable of reducing chip size and preventing mismatch.

It is another object of the present invention to provide a CDR circuit that can reduce lock time.

The present invention for achieving the above object is a voltage controlled oscillator for generating an oscillation clock having a frequency proportional to the magnitude of the input oscillation voltage, a charge pump for generating a regulating current for adjusting the oscillation voltage, A loop filter for low pass band filtering the first regulated current to the voltage controlled oscillator, and determining whether the oscillation clock has reached a predetermined target frequency, thereby controlling the output of the first regulated current. And a lock / free lock detector for adjusting a bandwidth of the loop filter according to a degree of the oscillation clock reaching the target frequency, wherein the loop filter has one side connected to an output terminal of the charge pump. A filter resistor for determining a real part of a transfer function, and is connected between the other side of the filter resistor and a ground terminal; A default pole capacitor for determining the base pole of the moon function, a default zero capacitor connected between the output terminal of the charge pump and the ground terminal to determine the base zero point of the transfer function, between the filter resistor and the ground end. Connected in parallel with the default pole capacitor, the at least one additional pole capacitor for adjusting the bandwidth of the loop filter, and connected between the output terminal of the charge pump and the ground terminal in parallel with the default zero capacitor. At least one additional zero capacitor adjusting a bandwidth of the loop filter, and at least one of controlling the parallel connection of the default pole capacitor and the additional pole capacitor in response to a free lock signal of the lock / free lock detector. One or more pole control switches and the lock / free lock detector At least one zero control switch for controlling parallel connection of said default zero capacitor and said additional zero capacitor in response to a free lock signal of < RTI ID = 0.0 > and < / RTI > It provides a PLL circuit including a potential holding portion for applying a potential of a level, and the potential of the same level as the default zero capacitor to one of the additional zero capacitor that is not connected to the default zero capacitor.
In addition, the present invention for achieving the above object, a voltage controlled oscillator for generating an oscillation clock having a frequency proportional to the magnitude of the input oscillation voltage, and a first generating current for adjusting the oscillation voltage; A first charge pump, a loop filter for low pass band filtering the first regulated current to the voltage controlled oscillator, and determining whether the oscillation clock has reached a predetermined target frequency, and accordingly the first regulated current A first frequency detector for controlling the output of the shared loop, the voltage controlled oscillator and the loop filter sharing the curse loop, and generating a second regulated current for adjusting the oscillation voltage of the voltage controlled oscillator. A second charge pump output to the loop filter, and a proximity between a frequency of a received data signal and a frequency of the oscillation clock; Selects a fine loop including a second frequency detector for controlling the output of the second regulated current, and a loop that is activated according to the extent to which the oscillation clock reaches the target frequency in the curse loop, and the loop filter And a lock / freelock detector for adjusting a bandwidth of the loop filter, wherein the loop filter includes a filter resistor having one side connected to an output terminal of the first charge pump to determine a real part of a transfer function, and the other side of the filter resistor and ground. A default pole capacitor connected between stages to determine a basic pole of the transfer function, a default zero capacitor coupled between an output terminal of the first charge pump and the ground terminal to determine a base zero point of the transfer function, Connected between a filter resistor and the ground terminal to form a parallel connection with the default pole capacitor, At least one additional pole capacitor for adjusting bandwidth, and connected between the output terminal of the first charge pump and the ground terminal in parallel with the default zero capacitor, and at least one adjusting the bandwidth of the loop filter. An additional zero capacitor, at least one pole control switch controlling parallel connection of said default pole capacitor and said additional pole capacitor in response to a free lock signal of said lock / free lock detector, and a free lock of said lock / free lock detector At least one zero control switch for controlling parallel connection of said default zero capacitor and said additional zero capacitor in response to a signal, and a potential at the same level as said default pole capacitor, not connected to said default pole capacitor of said additional pole capacitor; Is applied and the addition zero Provided is a CDR circuit including a potential holding unit for applying a potential at the same level as the default zero capacitor to a capacitor not connected to the default zero capacitor.

To help understand, the structure and winry of the serial transceiver will be described in detail before describing the present invention.

In general, a serial data transceiver transmits a signal to a channel through a driver after serializing a data stream at a transmitter, and a receiver has a relationship of recovering clock and data together using a signal transmitted through a channel. The bandwidth of the channel is limited and there is jitter and noise, so the waveform of the signal seen by the receiver is distorted. The receiver will function to recover the original signal from this distorted waveform. One embodiment of the transmitter structure is shown in FIG. 1 and one embodiment of the receiver structure is shown in FIG.

The transmitter having the structure shown in FIG. 1 generates a 1.25 GHz clock through a PLL, and serializes 10 125 MHz data into 1.25 GHz data using a time division method at 10: 1 MUX using the clock. In the driver, this signal is loaded onto the channel. The pattern generator in front of the transmitter generates a random signal and is used to check the bit error rate (BER) at the receiver.

The receiver of the structure shown in FIG. 2 receives data transmitted from the transmitter through a channel. Since most channels have limited bandwidth, when the data is sent at high speed, the waveform received by the receiver is somewhat distorted. The receiver restores the clock based on the received waveforms and restores the data using the clock. For this purpose, PLL (Phase Locked Loop) circuit principle is used for CDR circuit. The CDR circuit does not operate immediately after receiving data, but performs a normal reception operation after a certain tracking time passes to synchronize the reception data signal with the internal reception operation clock.

The PLL (Phase Locked Loop) circuit outputs a clock having the same frequency and phase difference as the reference clock. A PLL typically consists of a Phase Frequency Detector (PFD), a Charge Pump (CP), a Loop Filter (LF), a Voltage Controlled Oscillator (VCO), and a reference clock. Dividers are included if higher frequencies are needed. The structure of a general PLL circuit is shown in FIG.

The illustrated phase-frequency detector (PFD) compares the frequency and phase of the divided clock output to the output of the reference clock and divider, thereby up or down signals. signal). The up signal makes the oscillation clock of the voltage controlled oscillator faster when the divided clock is slower than the reference clock, and the down signal is divided into the divided clock. When the clock is faster than the reference clock, it causes the voltage-controlled oscillator (VCO) to oscillate more slowly. That is, since the voltage controlled oscillator VCO outputs a high frequency or a low frequency according to the control voltage, the up signal is passed through the charge pump CP and the loop filter LF. By increasing the control voltage of the voltage-controlled oscillator (VCO), the voltage-controlled oscillator (VCO) outputs a higher frequency. On the other hand, the down signal serves to lower the control voltage of the voltage controlled oscillator VCO while passing through the charge pump CP and the loop filter LF so that the voltage controlled oscillator VCO has a lower frequency. Make it oscillate. The frequency divider performs a frequency dividing operation of an oscillation clock of a voltage controlled oscillator (VCO). Based on this principle of operation, the PLL circuit is stabilized when the frequency and phase of the reference clock and the divided clock are finally the same. If the divider operates for 10 divisions and the reference clock is 125 MHz, after stabilization, the PLL circuit generates a 125 MHz division clock and 1.25 GHz oscillation clock having the same phase as the reference clock.

Examining the dynamics of a PLL circuit is an essential part of determining whether the PLL is operating reliably. The design of the loop filter, which determines the frequency characteristics and stability of the PLL, must be precisely verified using dynamics. On the other hand, the CDR circuit pursued by the present invention also includes the PLL circuit structure (file loop), so that the loop has similar dynamics.

First, the voltage controlled oscillator (VCO) will be described. The characteristic curve of the voltage controlled oscillator VCO may be briefly shown in FIG. 5, and the transfer function of the voltage controlled oscillator VCO may be expressed as in Equation 1 below.

Referring next to the charge pump, the transfer function of the charge pump is derived from Eq.

Based on the results above, let's look at the characteristics of the entire PLL loop. The entire loop is simplified as shown in FIG. 7.

When designing a loop filter (LF), which is a type of low pass filter, the trade-off between the reference sideband and the switching speed must be considered. Therefore, the loop filter LF should be designed to balance the lock time with the jitter reference spurs required by the system. In general, the narrower the bandwidth of the loop filter, the smaller the jitter reference spur, but the longer the lock time. 8 shows a structure of a loop filter implemented as a third-order band filter made of passive elements, and a transfer function of the illustrated loop filter is shown in Equation 3 below.

Here, the open loop transfer function L (s) and the closed loop transfer function C (s) are defined as in Equations 4a and 4b.

Among these, if the pole and zero analysis of the open loop transfer function is performed, the following equation 5 is obtained.

In addition, when the phase margin of the open loop transfer function is analyzed, Equation 6 is obtained.

Meanwhile, the fast acquisition techniques of frequencies that can be used in a CDR circuit using the PLL circuit principle are as follows.

1) How to Sweep Frequency

This method finds the frequency of the input signal by sweeping the frequency of the voltage controlled oscillator (VCO). When the frequency of the input signal and the voltage-controlled oscillator (VCO) output signal coincide, the loop locks and maintains the locked state.

2) How to design to support wide bandwidth

This method improves the frequency acquisition speed by widening the loop bandwidth in acquisition mode and reducing the bandwidth in tracking mode so that jitter is not degraded.

In the present invention, a method for accelerating frequency acquisition by widening the loop bandwidth during a large phase error by using a large phase error in the frequency synchronization mode and a small phase error in the tracking mode. Is extended to the clock-data restorer (CDR) to generate a signal that predicts the lock signal in advance in the clock-data restorer (CDR), and the loop bandwidth is gradually increased using the predicted signal. The method of adjustment was used. Details will be covered in the next chapter.

The idea of the present invention is to apply a variable loop bandwidth to a curse loop filter of a CDR circuit, for example, for the purpose of supporting fast acquisition of frequency without deteriorating jitter characteristics in the CDR circuit of FIG. 4.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The CDR circuit applying the PLL circuit principle to which the idea of the present invention is applied will be described as the first embodiment, and the general-purpose PLL circuit having the PLL circuit principle will be described as the second embodiment. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

(Example 1)

The CDR circuit of this embodiment as shown in FIG. 9 includes a curse loop for matching the oscillation clock to a predetermined target frequency in a wide range within a predetermined error range; And a fine loop for matching an oscillation clock having a frequency obtained in the curse loop with a frequency and phase with a received data signal. And a lock / free lock detector 900 for selecting a loop that is activated according to the extent to which the oscillation clock reaches the target frequency in the curse loop, and adjusting a bandwidth of a loop filter constituting the curse loop and the fine loop. Is made of.

The illustrated loop has a voltage controlled oscillator 200 for generating an oscillation clock having a frequency proportional to the magnitude of the input oscillation voltage; A first charge pump 600 generating a first regulated current to regulate the oscillation voltage; A loop filter (300) for low pass band filtering the first regulated current and delivering it to the voltage controlled oscillator (200); And a first frequency detector for determining whether the oscillation clock has reached a predetermined target frequency and controlling the output of the first regulated current accordingly.

The illustrated fine loop shares the voltage controlled oscillator 200 and the loop filter 300 with the curse loop, and generates a second regulated current for adjusting the oscillation voltage of the voltage controlled oscillator 200. A second charge pump 400 output to the filter 300; And a second frequency detector for controlling the output of the second regulated current according to the proximity of the frequency of the received data signal and the frequency of the oscillation clock.

The illustrated lock / free lock detector 900 includes: a lock detector for detecting a time point when the oscillation clock is close to the target frequency, which is a time point for switching an activation loop from the curse loop to the fine loop; And a free-lock detector for detecting a time before the activation loop is switched from the curse loop to the fine loop after a predetermined time.

Hereinafter, a detailed embodiment of the CDR circuit of the illustrated structure and its operation principle will be described.

First, the loop bandwidth and frequency acquisition characteristics of the PLL circuit portion of the CDR circuit are as follows. The wider the loop bandwidth, the shorter the acquisition time, and the narrower the bandwidth, the longer the acquisition time. . On the other hand, the jitter characteristic is affected by noise as the loop bandwidth is wider, and the jitter characteristic is worsened. In other words, the faster the loop, the faster the bandwidth. The smaller the loop, the smaller the bandwidth. As described above, the loop bandwidth is shown in Equation 5 above. As can be seen from Equation 5, the factors that can control the loop bandwidth are the gain of the voltage controlled oscillator (VCO), the R and C values of the loop filter, and the magnitude of the pump current.

9 illustrates a structure of a clock-data reconstructor that fits frequency and phase into two stages. Using a single voltage controlled oscillator (VCO), the frequency is first tuned through a loop I. In this case, the lock detector converts the loop I to the loop II when the reference clock frequency and the generated frequency coincide with each other at a predetermined integer ratio. The Fine Loop (Loop II) is intended to match the phase of the frequency that has already been matched to the data. In practice, the coincidence operation of the frequency is also performed in the micro range.

Accordingly, the first frequency detector of the present embodiment is a frequency-phase detector that receives a predetermined reference clock and compares it with the divided signal to determine whether a target frequency is reached, and the second frequency detector includes the oscillation signal and the reception signal. A phase detector for determining whether or not the data signal is in phase and outputting a second charge pump control signal according to its front and back relationship. The first frequency detector may further include: a divider for generating a divided signal by dividing the oscillation signal by a predetermined multiple; And a frequency-phase detector configured to receive a predetermined reference clock and determine whether the frequency of the divided signal matches, and output a first charge pump control signal according to the result, so that a lower reference clock can be used. Can be.

However, when a switch is made from a loop I to a loop II through a lock detector, a problem of false lock may be locked due to the loop bandwidth due to the loop bandwidth. do. In order to prevent this, the loop bandwidth of the loop filter LPF is reduced. In this case, the lock time in the loop I is slowed. Therefore, the lock detector has a signal that predicts the lock signal in advance and a circuit for the lock signal separately from the actual lock signal, and gradually increases the loop bandwidth based on the predicted signal. Trying to solve the above problem. That is, the present invention gradually changes one or more of a resistance, a current, and a capacitance by using a signal that predicts a lock signal in advance in conventional clock-data recoverer (CDR) structures. ) And to prevent the frequency from changing during loop switching.

First, a method of changing a current or a resistance of a charge pump, which is one of methods of controlling a loop bandwidth according to the present invention, will be described. The connection structure of the charge pump and the loop filter for this is shown in Figure 10, the bandwidth in Figure 10 can be expressed by the following equation 7.

As shown in the above equation, the smaller the charge pump current Ip, the smaller the bandwidth. On the other hand, it can be seen that the loop bandwidth changes according to the change in the resistance value R2 of the loop filter. One thing to note here is the consideration of phase margin. Instead of simply widening or reducing the bandwidth, the phase margin should be taken into account to ensure that there is no significant problem with stability. When adjusting the frequency in the loop I in the clock-data reconstructor (CDR), start the current with a large resistance and keep the frequency up to the desired level without compromising the stability. Prediction logic generated by the lock detector changes current or resistance individually or simultaneously to make the bandwidth small enough, and generates a lock signal to the loop II. Switch. Then, a fast lock time can be obtained in the first loop I, a jitter can be reduced in the second loop II, and a false lock can be prevented. .

Next, a method of changing capacitance, which is another method of adjusting the loop bandwidth, will be described.

As can be seen from Equation 7, the larger the capacitance (C1), the smaller the bandwidth (bandwidth). Therefore, when the frequency is adjusted in the loop I in the clock-data reconstructor (CDR), starting with the capacitance (C1) small in a range that does not impair stability, the frequency is gradually increased to the desired level. After increasing, the capacitance (C1) is changed through the lock-prediction signal generated by the lock detector to make the loop bandwidth small enough, and the lock signal is generated to generate the fine loop (Loop II). Switch to Accordingly, fast lock time can be obtained in the loop I, low phase noise can be prevented in the loop II, and false lock can be prevented. The bandwidth can be adjusted by changing the capacitance C1 as well as other capacitances C2 together or singly. In Equation 7, it can be seen that the other capacitance C2 becomes narrower as the value becomes larger. This method can be applied to PLL circuits for other purposes, and the general-purpose PLL circuits to which the method is applied will be described in the second embodiment.

10 and 11 illustrate an embodiment of a circuit configuration in which a dynamic characteristic of a loop filter proposed by the present invention can be dynamically changed by a digital control method. 12 is a simplified illustration of the loop filter of FIG. 10 or 11. The change in filter characteristics is obtained by changing the capacitance by additionally connecting or disconnecting the capacitors provided in parallel. First, only capacitors (Cz, Cz ') that constitute the basic loop filter are connected to the V _control stage. The remaining capacitors are discontinuous by charge-registration button when connected. In order to prevent this from appearing, the buffer of FIG. 10 or the comparator of FIG. 11 is continuously charged to the same voltage as the V _control stage. One example of a buffer is a unity gain operational amplifier. After that, the prelock detector determines that the oscillation frequency of the PLL structure is close to the target frequency, and additionally connects additional capacitors to the V _control stage to naturally change the filter characteristics. In this circuit, the capacitors can all be arranged in uniform capacitance or in multiples of capacitance so that the degree of change in filter characteristics can be adjusted as desired.

Among the various ways of implementing a capacitor, there is a method using a MOSFET. In this circuit, a fixed capacitor is placed and the capacitors are connected in parallel, and the capacitors are implemented using a MOSFET. 13A-13C show an implementation of a MOS capacitor using depletion, accumulation, and inversion regions. Using the characteristics of the MOSFET capacitor, when the freelock detector operates, the Vmos voltage is changed to change the overall capacitance value to adjust the bandwidth.

The loop filter shown in FIG. 10 or 11 applying the above scheme comprises: a default pole capacitor for determining a basic pole of a transfer function; A default zero capacitor that determines the default zero point of the transfer function; A filter resistor for determining the real part of the transfer function; One or more additional pole capacitors for adjusting bandwidth in parallel with the default pole capacitors; At least one pole control switch for controlling parallel connection of said default pole capacitor and said additional pole capacitor; One or more additional zero capacitors for adjusting bandwidth in a parallel connection to the default zero capacitor; One or more zero control switches for controlling parallel connection of said default zero capacitor and said additional zero capacitor; And a potential holding unit for applying a potential having the same level as that of the default pole capacitor to one of the additional zero capacitors not connected to the default zero capacitor.

In order to further reduce manufacturing cost and / or implementation area, only one type of the additional pole capacitor or the additional zero capacitor may be implemented, and for the range and / or convenience of bandwidth adjustment, the additional pole capacitor or the It has all the additional zero capacitors. Naturally, the pole / zero switch for the additional pole / zero capacitor not implemented is also deleted.

The potential holding unit receives a potential of the default pole / zero capacitor as shown in FIG. 10 and implements it as a voltage buffer outputting the additional pole / zero capacitor, or as shown in FIG. 11, the potential of the default pole / zero capacitor as shown in FIG. And a voltage comparator that receives the potential of the additional pole / zero capacitor and regulates the charging current for the additional pole / zero capacitor according to its superiority.

FIG. 14 shows a circuit configuration in which the magnitude of the current supplied to the loop filter by the charge pump can be changed. As illustrated, the current charge function is provided to the first charge pump. The first charge pump includes: a plurality of charge pumps I0 to In intermittently connected to the loop filter; And a plurality of switches S1 to Sn for switching the respective charge pumps I0 to In according to the control of the lock / freelock detector.

In the above configuration, the passive element portion of the loop filter may use only one of the same type, but by adjusting the charge pump, the amount of current supplied to the loop filter may be adjusted. If you need to flow a lot of current to increase the loop gain, you can connect several preliminary charge pumps to the Vcontrol stage. Then, the oscillation frequency of the PLL is close to the target frequency. In order to reduce loop gain and increase stability, spare charge pumps can be separated from the Vcontrol stage. Even in this type of configuration, the amount of current in the charge pump can be uniformly configured or multiplied by the configuration of the control logic that generates the control signal to be transmitted to the switch connecting and disconnecting each charge pump. It can also be configured as.

The prelock detector included in the lock / prelock detector 900 of FIG. 9 has an externally input frequency of 125 MHz (F _REF ) and an internal voltage controlled oscillator of 1.25 GHz (F _VCO ). Is properly compared to determine whether the frequency becomes equal to the reference clock F _REF . There are various implementations of this. For example, the free lock detector 920 shown in FIG. 16 includes: an M divider 921 for generating a divided reference clock obtained by dividing the reference clock by M; An oscillation clock counter unit for counting the number of oscillation clocks generated during one or half cycles of the divided reference clock; And a prelock determiner 925 for determining whether to freelock according to the number of counts of the oscillation clock counter.

The oscillation clock counter includes a synchronization flip-flop 922 for synchronizing the divided reference clock and the oscillation clock; An edge detector 923 for detecting an edge of the output signal of the synchronization flip-flop 922; And an oscillation clock counter 924 that is initialized according to the edge detection of the edge detector 923 and counts the oscillation clock. The free lock determiner 925 receives the edge detection signal of the edge detector 923 and the count signal of the oscillation clock counter 924, and when the edge detection signal is activated, the count signal has a predetermined number of counts. If abnormal, the free lock state is determined.

The free lock detector determines whether to lock at a counter time point up to 1/2 of a lock counter (not shown), and if the lock condition is equal to the actual lock condition, that is, the remaining 1/2 If the count is determined to be locked, a prelock signal is generated, thereby helping to change the bandwidth. The number of prelocks, the number of prelocks, etc. can be set more depending on the implementation, or only one, as in the previous example.

The used blocks are first reference clock (F _REF) In the following the path of the side, input the reference clock (F _REF) the 320 division div_320 blocks and to synchronize it to a rising edge of the oscillation clock (F _VCO) Synchronous flip-flop (sadff_rst) and the edge detector (edge_detector) that detects the transition portion of the divided and synchronized signal is converted to a pulse. On the other hand, the oscillation clock (F _VCO) In the following the path of the side, and the clock number of the oscillation clock (F _VCO) input (clock tick) count 14bit oscillator clock counter (counter_14b), the detection pulses of the edge detectors is a rising It is judged whether the output of the oscillation clock counter (counter_14b) indicates the specified number at the moment of rising, and the oscillation clock (F _VCO ) frequency is pre-locked to the reference clock (F _REF ) by the voltage controlled oscillator (VCO). A freelock determiner to determine whether In addition, a gate logic for resetting the oscillation clock counter counter_14b each time a detection pulse periodically output from the edge detector may be additionally included.

Detailed operation of the illustrated circuit is as follows. First, splitting the reference clock (F _REF ) into 320 results in a frequency of 390.625 KHz. The edge detector detects both rising / falling edges of this frequency, so that the pulse output from the output of the edge detector The period is 1 / (390.625 × 2) = 1.28 μs. During this one cycle, if the counter is counted up by the oscillation clock (F _VCO ), which normally oscillates to 1.25GHz, the output of the counter should indicate 1600 times at the end of one cycle. In the prelock logic (Pre_logic), the output of the oscillation clock counter is compared with the binary value of 1600, which is hard-wired, and the prelock signal is sent high when the oscillation clock (F) is equal. _VCO ) indicates that it is correctly prelocked at a frequency 10 times faster than the reference clock (F _REF ). On the contrary, if the output of the oscillation clock counter comparing at the rising edge of the detection pulse from the edge detector (edge_detector) is not 3200, the oscillation clock (F _VCO ) indicates that it is not prelocked at the desired frequency. Will keep the signal low. In a real hardware environment, there may be some variation in frequency even in the case of freelock, so the freelocked value allows an error of 3 bits (± 8) from the LSB side at 1600. It is desirable to design a value that detects the frequency shifting out of the free lock state to an error of 4 bits (± 16).

(Example 2)

As shown in FIG. 16, the PLL circuit of the present embodiment includes: a voltage controlled oscillator 1200 for generating an oscillation clock having a frequency proportional to the magnitude of an input oscillation voltage; A charge pump 1600 generating a regulating current for regulating the oscillation voltage; A loop filter (1300) for low pass band filtering the regulated current and delivering it to the voltage controlled oscillator; A frequency detector for determining whether the oscillation clock has reached a predetermined target frequency and controlling the output of the regulated current accordingly; And a prelock detector 1900 for adjusting the bandwidth of the loop filter according to the degree to which the oscillation clock reaches the target frequency.

The illustrated frequency detector includes: an N divider 1800 for generating a divided signal obtained by dividing the oscillation signal by N; And a frequency-phase detector 1700 that receives a predetermined reference clock and determines whether the frequency of the divided signal matches, and outputs a first charge pump control signal according to the result, which is 1 / N times lower than a target frequency. The reference clock is used to determine whether the target frequency is reached, that is, whether the PLL loop is locked.

The illustrated freelock detector 1900 is for predicting a lock time, which is a time point when the oscillation clock approaches the target frequency, before a predetermined time. In some implementations, the apparatus may further include a lock detector (not shown) for detecting the lock time and controlling the operation of the charge pump 1600.

When the oscillation clock of the voltage controlled oscillator 1200 is locked while increasing from the initial low frequency to the target frequency, the prelock detector 1900 determines whether the oscillation clock is close to a predetermined prelock target frequency lower than the target frequency. It will have a configuration for judging. An exemplary embodiment of the free-lock detector includes an M divider 921 for generating a divided reference clock obtained by dividing the reference clock by M as shown in FIG. 15; An oscillation clock counter unit for counting the number of oscillation clocks generated during one or half cycles of the divided reference clock; And a prelock determiner 925 for determining whether to freelock according to the number of counts of the oscillation clock counter.

The oscillation clock counter unit may include: a synchronization flip-flop 922 for synchronizing the divided reference clock and the oscillation clock; An edge detector 923 for detecting an edge of the output signal of the synchronization flip-flop 922; And an oscillation clock counter 924 that is initialized according to the edge detection of the edge detector 923, and counts the oscillation clock, and the free lock determiner 925 is an edge detection signal of the edge detector 923. And when the count signal is more than a predetermined number of counts when the edge detection signal is activated by receiving the count signal of the oscillation clock counter 924, it is determined as a free lock state.

On the other hand, in order to obtain a variable loop bandwidth, similarly to the case of the first embodiment, the loop filter of this embodiment has a structure shown in FIG. 10 or 11, or the charge pump of this embodiment has a structure shown in FIG. It can have

Detailed embodiments of the components of the present embodiment and an operation description thereof will be omitted since they overlap with the first embodiment.

Although the present invention has been described by way of limited embodiments and drawings, the present invention is not limited thereto, and the technical spirit of the present invention and the claims to be described below by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of equivalents.

By implementing the PLL circuit and the CDR circuit according to the present invention, there is an effect that the variation of the extraction frequency does not occur depending on the bandwidth.

In addition, the present invention can reduce the chip size, has the effect of preventing mismatch and / or the effect of reducing the lock time.

Claims (26)

A voltage controlled oscillator for generating an oscillation clock having a frequency proportional to a magnitude of an input oscillation voltage; A charge pump generating a regulating current for regulating the oscillation voltage; A loop filter for low pass band filtering the first regulated current and delivering it to the voltage controlled oscillator; A frequency detector for determining whether the oscillation clock has reached a predetermined target frequency and controlling the output of the first regulated current accordingly; And And a lock / free lock detector for adjusting the bandwidth of the loop filter according to the extent to which the oscillation clock reaches the target frequency. The loop filter, A filter resistor having one side connected to an output terminal of the charge pump to determine a real part of a transfer function; A default pole capacitor connected between the other side of the filter resistor and a ground terminal to determine a basic pole of the transfer function; A default zero capacitor connected between an output terminal of the charge pump and the ground terminal to determine a basic zero point of the transfer function; At least one additional pole capacitor connected between the filter resistor and the ground terminal to form a parallel connection with the default pole capacitor, and controlling a bandwidth of the loop filter; At least one additional zero capacitor connected between an output terminal of the charge pump and the ground terminal to form a parallel connection with the default zero capacitor, and controlling a bandwidth of the loop filter; At least one pole control switch controlling parallel connection of said default pole capacitor and said additional pole capacitor in response to a free lock signal of said lock / free lock detector; At least one zero control switch controlling parallel connection of said default zero capacitor and said additional zero capacitor in response to a free lock signal of said lock / free lock detector; And A potential at the same level as the default pole capacitor is applied to one of the additional pole capacitors not connected to the default pole capacitor, and a potential at the same level as the default zero capacitor to one not connected to the default zero capacitor among the additional zero capacitors. Potential holding part for applying PLL circuit comprising a. The method of claim 1, wherein the frequency detector, A divider for generating a divided signal by dividing the oscillation signal by a predetermined multiple; And A frequency-phase detector that receives a predetermined reference clock, determines whether the frequency of the divided signal matches, and outputs a first charge pump control signal according to the result. PLL circuit comprising a. The method of claim 1, wherein the lock / free lock detector, A lock detector for detecting a lock point in which the oscillation clock is close to the target frequency; And Free lock detector for predicting the lock time in advance a predetermined time PLL circuit comprising a. The method of claim 3, wherein the free lock detector, And a configuration for determining whether the oscillation clock is close to a predetermined freelock target frequency lower than the target frequency. The method of claim 4, wherein the free lock detector, An M divider for generating a divided reference clock by dividing the reference clock by M; An oscillation clock counter unit for counting the number of oscillation clocks generated during one or half cycles of the divided reference clock; Free lock determiner for determining whether or not free lock according to the number of count of the oscillation clock counter unit PLL circuit comprising a. The method of claim 5, wherein the oscillation clock counter, A synchronization flip-flop for synchronizing the divided reference clock and the oscillation clock; An edge detector for detecting an edge of the output signal of the synchronous flip-flop; And An oscillation clock counter initialized according to edge detection of the edge detector and counting the oscillation clock; PLL circuit comprising a. The method of claim 6, wherein the free lock determiner, A PLL circuit receiving an edge detection signal of the edge detector and a count signal of the oscillation clock counter. delete delete According to claim 1, wherein the potential holding unit A PLL circuit that is a voltage buffer that receives the potential of one of two nodes to maintain the same potential and outputs it to the other node. According to claim 1, wherein the potential holding unit And a voltage comparator that receives a potential of two nodes to maintain the same potential and regulates charging current for the additional pole or zero capacitor according to its superiority. The method of claim 1, wherein the charge pump, A plurality of charge pumps connected with the loop filter; And And a plurality of switches for switching each charge pump under control of the lock / freelock detector. A voltage controlled oscillator for generating an oscillation clock having a frequency proportional to the magnitude of the input oscillation voltage; A first charge pump generating a first regulated current for regulating the oscillation voltage; A loop filter for low pass band filtering the first regulated current and delivering it to the voltage controlled oscillator; A first frequency detector for determining whether the oscillation clock has reached a predetermined target frequency and controlling the output of the first regulated current accordingly Curse loop comprising a; Share the voltage controlled oscillator and loop filter with the curse loop, A second charge pump generating a second regulating current for adjusting the oscillation voltage of the voltage controlled oscillator and outputting the second regulated current to the loop filter; A second frequency detector for controlling the output of the second regulated current according to the proximity of the frequency of the received data signal and the frequency of the oscillation clock A fine loop comprising a; And And a lock / free lock detector for selecting a loop that is activated according to the extent to which the oscillation clock reaches the target frequency in the curse loop, and adjusting the bandwidth of the loop filter. The loop filter, A filter resistor having one side connected to an output terminal of the first charge pump to determine a real part of a transfer function; A default pole capacitor connected between the other side of the filter resistor and a ground terminal to determine a basic pole of the transfer function; A default zero capacitor connected between an output terminal of the first charge pump and the ground terminal to determine a basic zero point of the transfer function; At least one additional pole capacitor connected between the filter resistor and the ground terminal to form a parallel connection with the default pole capacitor, and controlling a bandwidth of the loop filter; At least one additional zero capacitor connected between an output terminal of the first charge pump and the ground terminal to form a parallel connection with the default zero capacitor, and controlling a bandwidth of the loop filter; At least one pole control switch controlling parallel connection of said default pole capacitor and said additional pole capacitor in response to a free lock signal of said lock / free lock detector; At least one zero control switch controlling parallel connection of said default zero capacitor and said additional zero capacitor in response to a free lock signal of said lock / free lock detector; And A potential at the same level as the default pole capacitor is applied to one of the additional pole capacitors not connected to the default pole capacitor, and a potential at the same level as the default zero capacitor to one not connected to the default zero capacitor among the additional zero capacitors. Potential holding part for applying CDR circuit comprising a. The method of claim 13, wherein the second frequency detector, And a phase detector for determining whether or not the oscillation signal and the received data signal are in phase and outputting a second charge pump control signal according to its front and back relationship. The method of claim 13, wherein the first frequency detector, A divider for generating a divided signal by dividing the oscillation signal by a predetermined multiple; And A frequency-phase detector that receives a predetermined reference clock, determines whether the frequency of the divided signal matches, and outputs a first charge pump control signal according to the result. CDR circuit comprising a. The method of claim 15, wherein the lock / free lock detector, A lock detector for detecting a time point at which the oscillation clock is close to the target frequency, which is a time point for switching an activation loop from the curse loop to the fine loop; And Free lock detector for detecting the time before the activation loop switching from the curse loop to the fine loop after a predetermined time CDR circuit comprising a. The method of claim 16, wherein the free lock detector, And a configuration for determining whether the oscillation clock is close to a predetermined freelock target frequency lower than the target frequency. The method of claim 17, wherein the free lock detector, An M divider for generating a divided reference clock by dividing the reference clock by M; An oscillation clock counter unit for counting the number of oscillation clocks generated during one or half cycles of the divided reference clock; Free lock determiner for determining whether or not free lock according to the number of count of the oscillation clock counter unit CDR circuit comprising a. The method of claim 18, wherein the oscillation clock counter, A synchronization flip-flop for synchronizing the divided reference clock and the oscillation clock; An edge detector for detecting an edge of the output signal of the synchronous flip-flop; And An oscillation clock counter initialized according to the edge detection of the edge detector and counting the oscillation clock CDR circuit comprising a. The method of claim 19, wherein the free lock determiner, CDR circuit receiving the edge detection signal of the edge detector and the count signal of the oscillation clock counter. The method of claim 16, wherein the lock detector, A CDR circuit for detecting whether or not a lock as an average of the output signal of the frequency phase detector for a predetermined period. delete delete The method of claim 13, wherein the potential holding unit A CDR circuit that receives a potential of one of two nodes to maintain the same potential and outputs the potential to another node. The method of claim 13, wherein the potential holding unit A CDR circuit comprising a voltage comparator that receives a potential of two nodes to maintain the same potential, and regulates a charging current for the additional pole / zero capacitor according to its superiority. The method of claim 13, wherein the first charge pump, A plurality of charge pumps connected with the loop filter; And And a plurality of switches for switching each charge pump under control of the lock / freelock detector.

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