KR100699807B1 - Stack chip and stack chip package comprising the same - Google Patents

Stack chip and stack chip package comprising the same Download PDF

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Publication number
KR100699807B1
KR100699807B1 KR1020060008304A KR20060008304A KR100699807B1 KR 100699807 B1 KR100699807 B1 KR 100699807B1 KR 1020060008304 A KR1020060008304 A KR 1020060008304A KR 20060008304 A KR20060008304 A KR 20060008304A KR 100699807 B1 KR100699807 B1 KR 100699807B1
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South Korea
Prior art keywords
chip
pad
stacked
connection
input
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KR1020060008304A
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Korean (ko)
Inventor
이종주
이동호
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삼성전자주식회사
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Priority to KR1020060008304A priority Critical patent/KR100699807B1/en
Priority to US11/627,791 priority patent/US7462930B2/en
Application granted granted Critical
Publication of KR100699807B1 publication Critical patent/KR100699807B1/en
Priority to US12/267,343 priority patent/US7768115B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60Q—ARRANGEMENT OF SIGNALLING OR LIGHTING DEVICES, THE MOUNTING OR SUPPORTING THEREOF OR CIRCUITS THEREFOR, FOR VEHICLES IN GENERAL
    • B60Q3/00—Arrangement of lighting devices for vehicle interiors; Lighting devices specially adapted for vehicle interiors
    • B60Q3/80—Circuits; Control arrangements
    • B60Q3/88—Means for plugging to the electrical power supply of the vehicle, e.g. by using cigarette lighter sockets
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21—LIGHTING
    • F21V—FUNCTIONAL FEATURES OR DETAILS OF LIGHTING DEVICES OR SYSTEMS THEREOF; STRUCTURAL COMBINATIONS OF LIGHTING DEVICES WITH OTHER ARTICLES, NOT OTHERWISE PROVIDED FOR
    • F21V23/00—Arrangement of electric circuit elements in or on lighting devices
    • F21V23/003—Arrangement of electric circuit elements in or on lighting devices the elements being electronics drivers or controllers for operating the light source, e.g. for a LED array
    • F21V23/004—Arrangement of electric circuit elements in or on lighting devices the elements being electronics drivers or controllers for operating the light source, e.g. for a LED array arranged on a substrate, e.g. a printed circuit board
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    • H01L23/64—Impedance arrangements
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60Y—INDEXING SCHEME RELATING TO ASPECTS CROSS-CUTTING VEHICLE TECHNOLOGY
    • B60Y2200/00—Type of vehicle
    • B60Y2200/10—Road Vehicles
    • B60Y2200/11—Passenger cars; Automobiles
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    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73257—Bump and wire connectors
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A stack chip and a stack chip package comprising the same are provided to connect internal circuits of two semiconductor chips to each other by using one input/output buffer connected to an external connection terminal. A stack chip includes two semiconductor chips(112,122) which are opposite to each other. Each of the semiconductor chips includes a silicon substrate having an active surface and a rear surface opposite to the active surface, an internal circuit formed on the active surface, chip pads(114,124) having input/output pads connected through input/output buffers to the internal circuits, and connective pads(118,128) having one or more input/output pads formed on the active surface. The connective pads of the two semiconductor chips are connected electrically with each other. At least, one semiconductor chip includes a first through-electrode having an exposed connective terminal.

Description

적층 칩 및 그를 갖는 적층 칩 패키지{Stack chip and stack chip package comprising the same}Stacked chip and stacked chip package having the same {Stack chip and stack chip package comprising the same}

도 1은 종래기술에 따른 적층 칩을 개략적으로 보여주는 회로도이다.1 is a circuit diagram schematically showing a stacked chip according to the prior art.

도 2는 도 1의 적층 칩을 갖는 적층 칩 패키지를 보여주는 단면도이다.FIG. 2 is a cross-sectional view illustrating a stacked chip package having the stacked chips of FIG. 1.

도 3은 본 발명에 따른 적층 칩을 개략적으로 보여주는 회로도이다.3 is a circuit diagram schematically showing a stacked chip according to the present invention.

도 4는 도 3의 회로를 갖는 제 1 실시예에 따른 적층 칩을 보여주는 단면도이다.4 is a cross-sectional view illustrating a stacked chip according to a first embodiment having the circuit of FIG. 3.

도 5는 도 4의 제 1 칩을 보여주는 평면도이다.5 is a plan view illustrating the first chip of FIG. 4.

도 6은 도 5의 단면도이다.6 is a cross-sectional view of FIG. 5.

도 7 내지 도 12는 도 4의 적층 칩의 웨이퍼 레벨 제조 방법에 따른 각 단계를 보여주는 도면들이다.7 to 12 are diagrams illustrating each step according to the wafer level manufacturing method of the stacked chip of FIG. 4.

도 13은 도 4의 적층 칩을 갖는 적층 칩 패키지의 일 예를 보여주는 단면도이다.13 is a cross-sectional view illustrating an example of a stacked chip package having the stacked chips of FIG. 4.

도 14는 도 4의 적층 칩을 갖는 적층 칩 패키지의 다른 예를 보여주는 단면도이다.14 is a cross-sectional view illustrating another example of a stacked chip package having the stacked chips of FIG. 4.

도 15는 도 3의 회로를 갖는 제 2 실시예에 따른 적층 칩을 보여주는 단면도이다.FIG. 15 is a cross-sectional view illustrating a stacked chip according to a second embodiment having the circuit of FIG. 3.

도 16은 도 3의 회로를 갖는 제 3 실시예에 따른 적층 칩의 반도체 칩을 보여주는 평면도이다.FIG. 16 is a plan view illustrating a semiconductor chip of the stacked chip according to the third embodiment having the circuit of FIG. 3.

도 17은 도 16의 고속 패드와 연결된 접속 패드가 재배선된 상태를 보여주는 단면도이다.17 is a cross-sectional view illustrating a state in which connection pads connected to the high speed pad of FIG. 16 are rearranged.

도 18은 도 16의 저속 패드와 연결되어 재배선된 상태를 보여주는 단면도이다.FIG. 18 is a cross-sectional view illustrating a state in which the low speed pad of FIG. 16 is connected and rewired.

도 19는 도 16의 전원/접지 회로 배선과 연결되어 재배선된 상태를 보여주는 단면도이다.FIG. 19 is a cross-sectional view illustrating a state in which a wire is connected to the power / ground circuit wire of FIG. 16 and rearranged.

* 도면의 주요 부분에 대한 설명 *Description of the main parts of the drawing

110 : 제 1 웨이퍼 112 : 제 1 칩110: first wafer 112: first chip

114 : 제 1 칩 패드 118 : 제 1 접속 패드114: first chip pad 118: first connection pad

119 : 제 1 관통 전극 120 : 제 2 웨이퍼119: first through electrode 120: second wafer

122 : 제 2 칩 124 : 제 2 칩 패드122: second chip 124: second chip pad

128 : 제 2 접속 패드 130 : 적층 칩128: second connection pad 130: stacked chip

131 : 전기적 연결 수단 132 : 금속 범프131: electrical connection means 132: metal bump

133, 136 : 충진층 135 : 접속 범프133, 136: filling layer 135: connection bump

140 : 배선기판 150 : 수지 봉합부140: wiring board 150: resin sealing portion

160 : 외부접속단자 170 : 절단기160: external connection terminal 170: cutting machine

200a, 200b : 적층 칩 패키지200a, 200b: stacked chip package

본 발명은 반도체 패키지 기술에 관한 것으로, 더욱 상세하게는 두 개의 반도체 칩이 적층된 적층 칩 및 그를 갖는 적층 칩 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor package technology, and more particularly, to a stacked chip having two semiconductor chips stacked thereon and a stacked chip package having the same.

DRAM과 같은 메모리 제품의 발전 방향은 고속화와 고용량화의 두 방향으로 대변될 수 있다. 이러한 고용량화를 달성하는 한가지 방법으로 반도체 칩을 3차원으로 적층하는 칩 적층 방법이 활용되고 있다. 이러한 칩 적층에 의한 용량의 확장은 동일한 패키지 면적에 대해 제품의 용량을 간단히 적층되는 반도체 칩 수에 대응되는 배수로 증가시킬 수 있는 장점을 갖고 있다.The development direction of memory products such as DRAM can be represented in two directions: high speed and high capacity. As one method of achieving such high capacity, a chip stacking method of stacking semiconductor chips in three dimensions has been utilized. The expansion of capacity by chip stacking has an advantage of increasing the capacity of a product by a multiple corresponding to the number of semiconductor chips that are simply stacked for the same package area.

이와 같은 칩 적층 구조를 갖는 적층 칩 패키지의 경우, 반도체 칩의 칩 패드와 외부접속단자의 연결은 미국등록특허 제5,323,060호에 개시된 바와 같이 와이어 본딩(wire bonding)에 의해 이루어지거나, 미국등록특허 제5,973,403호에 개시된 바와 같이 플립 칩 본딩(flip chip bonding)과 와이어 본딩이 혼합된 형태로 이루어질 수 있다. 최근에는 미국등록특허 제6,429,096호에 개시된 바와 같이, 관통전극(through electrode)을 이용하기도 한다.In the case of the multilayer chip package having such a chip stack structure, the connection between the chip pad and the external connection terminal of the semiconductor chip is made by wire bonding as disclosed in US Patent No. 5,323,060, or US Patent No. As disclosed in 5,973,403, flip chip bonding and wire bonding may be mixed. Recently, as disclosed in US Pat. No. 6,429,096, a through electrode is also used.

종래기술에 따른 적층 칩 패키지(100)는, 도 1 및 도 2에 도시된 바와 같이, 동일한 두 개의 반도체 칩(12, 22)이 스페이서(37; spacer)를 매개로 배선기판(40)의 상부면(41)에 적층된 구조를 갖는다. 반도체 칩(12, 22)의 칩 패드(14, 24)와 배선기판(40)은 본딩 와이어(35)에 의해 전기적으로 연결된다. 배선기판(40)의 상부면(41)에 실장된 반도체 칩(12, 22)과 본딩 와이어(35)는 수지 봉합부(50)에 의 해 봉합되어 보호된다. 그리고 배선기판(40)의 하부면(42)에 반도체 칩(12, 22)의 칩 패드(14, 24)와 전기적으로 연결된 솔더 볼과 같은 외부접속단자(60)가 형성된다.In the stacked chip package 100 according to the related art, as shown in FIGS. 1 and 2, two identical semiconductor chips 12 and 22 are formed on the upper portion of the wiring board 40 via a spacer 37. It has a structure laminated on the surface 41. The chip pads 14 and 24 of the semiconductor chips 12 and 22 and the wiring board 40 are electrically connected by the bonding wires 35. The semiconductor chips 12 and 22 and the bonding wire 35 mounted on the upper surface 41 of the wiring board 40 are sealed and protected by the resin sealing unit 50. In addition, an external connection terminal 60 such as solder balls electrically connected to the chip pads 14 and 24 of the semiconductor chips 12 and 22 is formed on the lower surface 42 of the wiring board 40.

이때 외부접속단자(60)를 통하여 입력되는 신호는 각각 반도체 칩(12, 22)의 칩 패드(14, 24) 및 입출력 버퍼(16, 26; I/O buffer)를 거쳐 내부 회로(17, 27)로 전송된다.At this time, signals input through the external connection terminal 60 are passed through the chip pads 14 and 24 and the input / output buffers 16 and 26 of the semiconductor chips 12 and 22, respectively. Is sent).

이와 같이 두 개의 반도체 칩(12, 22)이 적층된 적층 칩 패키지(100)는 외부접속단자(60)에 대한 입력 용량 로딩(input capacitive loading)이 2배로 증가하여 단품 패키지(하나의 반도체 칩이 내장된 반도체 패키지) 대비 속도가 떨어지는 문제점을 안고 있다. 즉 입력 용량 로딩은 칩 패드(14, 24)와 내부 회로(17, 27)를 연결하는 입출력 버퍼(16, 26)의 수와 관계되는 데, 외부접속단자(60)에 두 개의 반도체 칩(12, 22)의 칩 패드(14, 24)가 병렬로 연결되기 때문에, 각각의 외부접속단자(60)에 대해 두 개의 입출력 버퍼(16, 26)가 연결되어 입력 용량 로딩이 2배로 증가하게 된다. 그리고 입력 용량 로딩의 증가는 적층되는 반도체 칩 수에 비례해서 증가하게 된다.As described above, in the multilayer chip package 100 in which two semiconductor chips 12 and 22 are stacked, the input capacitive loading of the external connection terminal 60 is doubled so that a single package (one semiconductor chip is It has a problem of slowing down compared to an embedded semiconductor package). That is, the input capacitance loading is related to the number of input / output buffers 16 and 26 connecting the chip pads 14 and 24 to the internal circuits 17 and 27, and the two semiconductor chips 12 are connected to the external connection terminal 60. Since the chip pads 14 and 24 of FIG. 22 are connected in parallel, two input / output buffers 16 and 26 are connected to each external connection terminal 60 to double the input capacity loading. In addition, the increase in the input capacitance loading increases in proportion to the number of stacked semiconductor chips.

한편 적층 칩 패키지(100) 동작시 열적 문제로 인해 이러한 칩 적층 구조에서는 하나의 반도체 칩만이 실제 동작하고 다른 하나는 대기(standby) 상태에 있기 때문에, 동작하지 않는 입출력 버퍼들이 여러개 연결되어 있는 것은 손실이라 할 수 있다.On the other hand, due to thermal problems during the operation of the stacked chip package 100, since only one semiconductor chip is actually operated and the other is in a standby state in the chip stack structure, it is lost that multiple input / output buffers are connected. This can be called.

그리고 이러한 입력 용량 로딩의 증가는 적층 칩 패키지/시스템의 고속화에 따라 채널/시스템 레벨에서 데이터의 베리드 윈도우 사이즈(valid window size)를 감소시켜 시스템 레벨의 신호 무결성(signal integrity)을 떨어뜨림으로써, 실제 적층 칩 패키지/시스템의 고속화를 방해한다.And this increase in input capacity loading reduces the valid window size of the data at the channel / system level as the stack chip package / system speeds up, thereby lowering the system integrity signal integrity. It hinders the speed of the actual stacked chip package / system.

따라서, 본 발명의 제 1 목적은 입력 용량 로딩을 감소시켜 단품 패키지와 비교하여 동일하거나 유사한 속도를 유지하면서 용량을 두 배로 증가시킬 수 있도록 하는 데 있다.Accordingly, the first object of the present invention is to reduce the input capacity loading so that the capacity can be doubled while maintaining the same or similar speed as compared to the single package.

본 발명의 제 2 목적은 동작하지 않는 입출력 버퍼들의 수를 최소화할 수 있도록 하는 데 있다.It is a second object of the present invention to minimize the number of input / output buffers that are not operating.

본 발명의 제 3 목적은 입력 용량 로딩을 감소시켜 시스템 레벨 신호 무결성을 향상시킬 수 있도록 하는 데 있다.It is a third object of the present invention to reduce input capacity loading so that system level signal integrity can be improved.

상기 목적을 달성하기 위하여, 본 발명은 두 개의 반도체 칩을 적층하는 칩 적층 구조에 있어서, 외부접속단자와 연결되는 하나의 입출력 버퍼를 통하여 두 개의 반도체 칩의 내부 회로를 연결하는 적층 칩 및 그를 갖는 적층 칩 패키지를 제공한다.In order to achieve the above object, the present invention provides a chip stack structure for stacking two semiconductor chips, comprising a stacked chip for connecting internal circuits of two semiconductor chips through one input / output buffer connected to an external connection terminal and Provides a stacked chip package.

본 발명은 활성면이 서로 마주보게 두 개의 반도체 칩이 적층된 적층 칩을 제공한다. 이때 반도체 칩은 활성면과, 활성면에 반대되는 배면을 갖는 실리콘 기판을 포함한다. 내부 회로는 실리콘 기판의 활성면 내에 형성된다. 내부 회로와 연결된 칩 패드들은 내부 회로와 입출력 버퍼를 매개로 연결된 입출력 패드를 포함한 다. 칩 패드들과 연결되어 활성면에 형성되는 접속 패드들은 입출력 버퍼와 내부 회로 사이에 연결되어 활성면에 형성된 적어도 하나 이상의 입출력용 접속 패드를 포함한다. 그리고 두 개의 반도체 칩은 접속 패드들끼리 전기적으로 연결되며, 적어도 하나의 반도체 칩은 칩 패드와 연결되어 배면으로 접속단이 노출된 제 1 관통 전극이 형성되어 있다.The present invention provides a stacked chip in which two semiconductor chips are stacked with their active surfaces facing each other. In this case, the semiconductor chip includes a silicon substrate having an active surface and a back surface opposite to the active surface. Internal circuitry is formed within the active surface of the silicon substrate. Chip pads connected to internal circuits include input / output pads connected through internal circuits and input / output buffers. The connection pads connected to the chip pads and formed on the active surface include at least one connection pad for input / output connected between the input / output buffer and the internal circuit and formed on the active surface. In addition, the two semiconductor chips are electrically connected to the connection pads, and the at least one semiconductor chip is connected to the chip pads to form a first through electrode having the connection end exposed at the rear thereof.

본 발명에 따른 적층 칩에 있어서, 반도체 칩은 제 1 칩과, 제 1 칩의 활성면에 적층된 제 2 칩을 포함한다. 제 1 관통 전극은 제 1 칩의 칩 패드를 관통하여 형성된다.In the stacked chip according to the present invention, the semiconductor chip includes a first chip and a second chip stacked on the active surface of the first chip. The first through electrode is formed through the chip pad of the first chip.

본 발명에 따른 적층 칩에 있어서, 접속 패드는 활성면 위에 재배선되어 형성된다.In the stacked chip according to the present invention, the connection pads are rewired on the active surface.

본 발명에 따른 적층 칩에 있어서, 입출력 패드는 고속 패드와 저속 패드를 포함하며, 고속 패드는 입출력용 접속 패드에 연결된다.In the stacked chip according to the present invention, the input / output pad includes a high speed pad and a low speed pad, and the high speed pad is connected to the connection pad for the input / output.

저속 패드에 일단이 연결되어 활성면 위에 재배선되어 형성되며, 타단에 저속용 접속 패드를 갖는 저속용 재배선층을 포함할 수 있다.One end is connected to the low speed pad and is redistributed on the active surface, and the other end may include a low speed redistribution layer having a low speed connection pad.

본 발명에 따른 적층 칩에 있어서, 칩 패드는 전원/접지 패드를 더 포함한다. 이때 일단이 내부 회로의 전원/접지 배선에 연결되어 활성면 위에 재배선되어 형성되며, 전원/접지용 접속 패드를 갖는 전원/접지용 재배선층을 더 포함할 수 있다. 전원/접지용 재배선층은 다른 재배선층에 비해서 넓게 형성하는 것이 바람직하다. 특히 전원/접지 패드는 전원/접지용 재배선층의 타단에 연결된다.In the stacked chip according to the present invention, the chip pad further includes a power supply / grounding pad. In this case, one end may be connected to a power / ground wire of an internal circuit and redistributed on the active surface, and may further include a power / grounding redistribution layer having a power / grounding connection pad. The power supply / grounding redistribution layer is preferably formed wider than other redistribution layers. In particular, the power / grounding pad is connected to the other end of the power / grounding redistribution layer.

본 발명에 따른 적층 칩에 있어서, 제 2 칩은 칩 패드와 연결된 제 2 관통 전극을 더 포함할 수 있다.In the stacked chip according to the present invention, the second chip may further include a second through electrode connected to the chip pad.

본 발명에 따른 적층 칩에 있어서, 반도체 칩은 센터 패드형 반도체 칩이다.In the stacked chip according to the present invention, the semiconductor chip is a center pad type semiconductor chip.

본 발명에 따른 적층 칩에 있어서, 제 1 및 제 2 칩의 상기 접속 패드들은 금속 범프를 매개로 전기적으로 연결된다. 제 1 칩의 활성면과 제 2 칩의 활성면 사이에 개재된 충진층에 의해 금속 범프는 보호된다.In the stacked chip according to the present invention, the connection pads of the first and second chips are electrically connected via metal bumps. The metal bumps are protected by a filling layer interposed between the active surface of the first chip and the active surface of the second chip.

본 발명은 또한 전술된 적층 칩을 갖는 적층 칩 패키지를 제공한다. 즉 적층 칩의 제 1 칩의 면이 배선기판의 상부면에 실장된다. 이때 제 1 칩의 배면으로 노출된 제 1 관통 전극의 접속단이 배선기판의 상부면에 전기적으로 연결된다. 적층 칩이 실장된 배선기판의 영역은 수지 봉합부에 의해 봉합된다. 그리고 외부접속단자는 배선기판의 하부면에 형성되며, 제 1 관통 전극의 접속단과 전기적으로 연결된다.The present invention also provides a stacked chip package having the stacked chips described above. That is, the surface of the first chip of the stacked chip is mounted on the upper surface of the wiring board. At this time, the connection end of the first through electrode exposed to the rear surface of the first chip is electrically connected to the upper surface of the wiring board. The area of the wiring board on which the stacked chip is mounted is sealed by the resin sealing portion. The external connection terminal is formed on the lower surface of the wiring board and is electrically connected to the connection end of the first through electrode.

제 1 관통 전극의 접속단과 배선기판의 전기적 연결 수단으로 접속 범프나 본딩 와이어가 사용될 수 있다. 접속 범프를 매개로 본딩된 경우, 배선기판과 적층 칩 사이에 충진층을 개재하여 접속 범프를 보호한다. 그리고 배선기판에 적층 칩이 안정적으로 실장될 수 있도록, 제 1 칩의 배면의 가장자리 둘레와 배선기판의 상부면 사이에 스페이서를 개재할 수 있다.A connection bump or a bonding wire may be used as an electrical connection means of the connection end of the first through electrode and the wiring board. When bonded via the connection bumps, the connection bumps are protected through a filling layer between the wiring board and the stacked chip. In addition, a spacer may be interposed between the edge of the rear surface of the first chip and the upper surface of the wiring board so that the stacked chip may be stably mounted on the wiring board.

본딩 와이어를 매개로 본딩된 경우, 배선기판은 제 1 관통 전극의 접속단이 노출되게 창이 형성된다. 창을 통하여 배선기판과 제 1 관통 전극의 접속단은 본딩 와이어에 의해 전기적으로 연결된다. 이때 수지 봉합부는 배선기판의 상부면에 실장된 적층 칩을 봉합하는 제 1 수지 봉합부와, 배선기판의 하부면의 창을 봉합하여 형성된 제 2 수지 봉합부를 포함한다.When bonded through the bonding wire, the wiring board is formed with a window so that the connection end of the first through electrode is exposed. The connecting end of the wiring board and the first through electrode is electrically connected by a bonding wire through the window. In this case, the resin encapsulation part includes a first resin encapsulation part for encapsulating a laminated chip mounted on an upper surface of a wiring board, and a second resin encapsulation part formed by sealing a window of a lower surface of the wiring board.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

도 3은 본 발명에 따른 적층 칩(130)을 개략적으로 보여주는 회로도이다. 도 3을 참조하면, 본 발명에 따른 적층 칩(130)은 외부접속단자(160)와 연결되는 하나의 입출력 버퍼(116)를 통하여 두 개의 반도체 칩(112, 122)의 내부 회로(117, 127)가 연결되도록 구성된다. 반도체 칩(112, 122)은 회로 배선을 통하여 칩 패드(114, 124), 입출력 버퍼(116, 126) 및 내부 회로(117, 127) 순으로 연결된다. 그리고 접속 패드(118, 128)가 입출력 버퍼(116, 126)와 내부 회로(117, 127)를 연결하는 회로 배선(117a, 127a) 사이에 연결된다. 제 1 및 제 2 칩(112, 122)의 접속 패드(118, 128)는 전기적 연결 수단(131)을 매개로 전기적으로 연결된다. 그리고 제 1 칩(112)의 제 1 칩 패드(114)가 외부접속단자(160)와 전기적으로 연결된다. 여기서 칩 패드(114, 124)는 입출력 패드이다.3 is a circuit diagram schematically illustrating a stacked chip 130 according to the present invention. Referring to FIG. 3, the stacked chip 130 according to the present invention may include internal circuits 117 and 127 of two semiconductor chips 112 and 122 through one input / output buffer 116 connected to an external connection terminal 160. ) Is configured to be connected. The semiconductor chips 112 and 122 are connected to the chip pads 114 and 124, the input / output buffers 116 and 126, and the internal circuits 117 and 127 through circuit wiring. The connection pads 118 and 128 are connected between the input / output buffers 116 and 126 and the circuit wirings 117a and 127a connecting the internal circuits 117 and 127. The connection pads 118 and 128 of the first and second chips 112 and 122 are electrically connected to each other via the electrical connection means 131. The first chip pad 114 of the first chip 112 is electrically connected to the external connection terminal 160. Here, the chip pads 114 and 124 are input / output pads.

본 발명에 따른 적층 칩(130)의 입출력 신호의 흐름을 살펴보면, 먼저 입력 신호는 외부접속단자(160)를 통하여 제 1 칩(112)의 제 1 칩 패드(114)로 입력된 후, 제 1 칩(112)의 제 1 입출력 버퍼(116)를 거쳐 연결된 접속 패드(118, 128)를 통하여 제 1 칩(112) 또는 제 2 칩(122)의 내부 회로(117, 127)로 입력된다. 즉 입력 신호는 제 1 칩(112)의 제 1 내부 회로(117)로 입력되거나, 제 1 칩(112)의 제 1 접속 패드(118), 전기적 연결 수단(131) 및 제 2 칩(122)의 제 2 접속 패드(128) 를 거쳐 제 2 칩(122)의 제 2 내부 회로(127)로 입력된다.Looking at the flow of the input and output signals of the stacked chip 130 according to the present invention, first input signal is input to the first chip pad 114 of the first chip 112 through the external connection terminal 160, and then the first It is input to the internal circuits 117 and 127 of the first chip 112 or the second chip 122 through the connection pads 118 and 128 connected through the first input / output buffer 116 of the chip 112. That is, the input signal is input to the first internal circuit 117 of the first chip 112, or the first connection pad 118, the electrical connection means 131, and the second chip 122 of the first chip 112. It is input to the second internal circuit 127 of the second chip 122 via the second connection pad 128 of.

그리고 출력 신호는 제 1 또는 제 2 내부 회로(117, 127)를 통하여 제 1 입출력 버퍼(116)로 출력된 후, 제 1 칩 패드(114)를 거쳐 외부접속단자(160)로 출력된다. 즉 제 1 내부 회로(117)의 출력 신호는 기존과 동일하게 제 1 입출력 버퍼(116) 및 제 1 칩 패드(114)를 거쳐 외부접속단자(160)로 출력된다. 제 2 내부 회로(127)의 출력 신호는 제 2 접속 패드(128), 전기적 연결 수단(131) 및 제 1 접속 패드(118)를 거쳐 제 1 입출력 버퍼(116) 및 제 1 칩 패드(114)를 통하여 외부접속단자(160)로 출력된다.The output signal is output to the first input / output buffer 116 through the first or second internal circuits 117 and 127, and then to the external connection terminal 160 via the first chip pad 114. In other words, the output signal of the first internal circuit 117 is output to the external connection terminal 160 via the first input / output buffer 116 and the first chip pad 114 in the same manner as before. The output signal of the second internal circuit 127 is passed through the second connection pad 128, the electrical connection means 131, and the first connection pad 118 to the first input / output buffer 116 and the first chip pad 114. It is output to the external connection terminal 160 through.

이때 제 2 칩(122)의 제 2 칩 패드(124)와 제 2 입출력 버퍼(126)는 패키징이 완료된 이후에는 입출력 단자로 사용되지 않는다.In this case, the second chip pad 124 and the second input / output buffer 126 of the second chip 122 are not used as input / output terminals after packaging is completed.

따라서 외부접속단자(160)에서 바라보는 적층 칩(130)의 입력 용량 로딩을 단품 패키지 수준으로 낮출 수 있기 때문에, 단품 패키지와 동일하거나 유사한 속도를 유지하면서 고속화를 지원하면서 용량을 두 배로 증가시킬 수 있다.Therefore, since the input capacity loading of the stacked chip 130 viewed from the external connection terminal 160 can be lowered to a single package level, the capacity can be doubled while supporting high speed while maintaining the same or similar speed as the single package. have.

제 1 실시예First embodiment

이와 같은 회로를 갖는 본 발명의 제 1 실시예에 따른 적층 칩(130)이 도 4 내지 도 6에 도시되어 있다. 도 4는 도 3의 회로를 갖는 제 1 실시예에 따른 적층 칩(130)을 보여주는 단면도이다. 도 5는 도 4의 제 1 칩(112)을 보여주는 평면도이다. 그리고 도 6은 도 5의 단면도이다.4 to 6 illustrate a stacked chip 130 according to a first embodiment of the present invention having such a circuit. 4 is a cross-sectional view illustrating the stacked chip 130 according to the first embodiment having the circuit of FIG. 3. 5 is a plan view illustrating the first chip 112 of FIG. 4. 6 is a cross-sectional view of FIG. 5.

제 1 실시예에 따른 적층 칩(130)은 반도체 칩(112, 122)의 활성면(111a, 121a)이 서로 마주보게 적층된 듀얼 칩(dual chip)이다. 반도체 칩(112, 122)의 활성면(111a, 121a)에는 접속 패드(118, 128)가 형성되어 있으며, 접속 패드(118, 128)는 금속 범프(132)와 같은 전기적 연결 수단을 매개로 전기적으로 연결된다. 적층된 반도체 칩(112, 122) 사이로 충진된 충진층(133)에 의해 금속 범프(132)는 보호된다. 그리고 적층 칩(130)을 외부접속단자와 연결할 수 있도록, 적어도 하나의 반도체 칩(112)에는 칩 패드(114)와 연결된 관통 전극(119)이 형성되어 있다.The stacked chip 130 according to the first embodiment is a dual chip in which the active surfaces 111a and 121a of the semiconductor chips 112 and 122 are stacked to face each other. Connection pads 118 and 128 are formed on the active surfaces 111a and 121a of the semiconductor chips 112 and 122, and the connection pads 118 and 128 are electrically connected to each other through an electrical connection means such as metal bumps 132. Is connected. The metal bumps 132 are protected by the filling layer 133 filled between the stacked semiconductor chips 112 and 122. In addition, the at least one semiconductor chip 112 has a through electrode 119 connected to the chip pad 114 to connect the stacked chip 130 with an external connection terminal.

제 1 실시예에 따른 적층 칩(130)에 대해서 구체적으로 설명하면 다음과 같다.Hereinafter, the stacked chip 130 according to the first embodiment will be described in detail.

반도체 칩(112, 122)은 활성면(111a, 121a)이 서로 마주보게 적층된 제 1 칩(112)과 제 2 칩(122)으로 이루어진다. 이때 제 1 칩(112)과 제 2 칩(122)은 유사한 구조를 갖기 때문에, 제 1 칩(112)을 중심으로 설명하면 다음과 같다.The semiconductor chips 112 and 122 include a first chip 112 and a second chip 122 in which the active surfaces 111a and 121a are stacked to face each other. In this case, since the first chip 112 and the second chip 122 have a similar structure, the first chip 112 will be described below.

제 1 칩(112)은 실리콘 기판(111)의 활성면(111a)에 제 1 칩 패드(114)들과 제 1 접속 패드(118)들이 형성되고, 제 1 칩 패드(114)와 제 1 접속 패드(118)를 제외한 활성면(111a)은 보호층(115)으로 덮인 구조를 갖는다. 실리콘 기판(111)은 활성면(111a)과, 활성면(111a)에 반대되는 배면(111b)을 갖는다. 제 1 칩 패드(114)는 실리콘 기판(111)의 내부에 형성된 집적회로들과 전기적으로 연결되며, 전기 전도성이 양호한 알루미늄(Al), 구리(Cu) 등으로 형성된다. 보호층(115)은 실리콘 기판(111) 내부의 집적회로들을 외부환경으로부터 보호하며, 산화막, 질화막 또는 그 조합으로 형성된다.In the first chip 112, the first chip pads 114 and the first connection pads 118 are formed on the active surface 111a of the silicon substrate 111, and the first chip pad 114 and the first connection pad are formed. The active surface 111a except for the pad 118 has a structure covered with the protective layer 115. The silicon substrate 111 has an active surface 111a and a back surface 111b opposite to the active surface 111a. The first chip pad 114 is electrically connected to integrated circuits formed in the silicon substrate 111 and is formed of aluminum (Al), copper (Cu), or the like having good electrical conductivity. The protection layer 115 protects the integrated circuits inside the silicon substrate 111 from an external environment and is formed of an oxide film, a nitride film, or a combination thereof.

제 1 칩 패드(114)는 입출력 패드(114a, 114b)와 전원/접지 패드(114c)로 이 루어진다. 입출력 패드(114a, 114b)는 속도가 빨라 저 입력 용량(low input capacitance)이 중요한 고속 패드(114a)와, 입력 용량 로딩의 증가가 크게 문제되지 않는 저속 패드(114b)로 이루어진다. 입출력 패드(114a, 114b)는 각각 제 1 입출력 버퍼(116)를 매개로 제 1 내부 회로와 연결된다.The first chip pad 114 is composed of input / output pads 114a and 114b and a power / ground pad 114c. The input / output pads 114a and 114b are composed of a high speed pad 114a where speed is low and low input capacitance is important, and a low speed pad 114b in which an increase in input capacity loading is not a problem. The input / output pads 114a and 114b are connected to the first internal circuit through the first input / output buffer 116, respectively.

제 1 접속 패드(118)는 입출력 패드(114a, 114b)와 연결되는 입출력용 접속 패드(118a, 118b)와, 전원/접지 패드(114c)에 연결되는 전원/접지용 접속 패드(118c)를 포함하며, 팹(FAB) 공정을 통한 재배선 방법으로 활성면(111a)에 형성된다. 이때 입출력용 접속 패드(118a, 118b)는 제 1 입출력 버퍼(116)와 제 1 내부 회로 사이의 회로 배선(117a)에 연결되어 활성면(111a)에 형성된다. 입출력용 접속 패드(118a, 118b)는 고속 패드(114a)에 연결되는 고속용 접속 패드(118a)와, 저속 패드(114b)에 연결되는 저속용 접속 패드(118b)로 이루어진다.The first connection pad 118 includes input / output connection pads 118a and 118b connected to the input / output pads 114a and 114b, and a power / ground connection pad 118c connected to the power / grounding pad 114c. And, it is formed on the active surface 111a by the rewiring method through the Fab (FAB) process. In this case, the input / output connection pads 118a and 118b are connected to the circuit wiring 117a between the first input / output buffer 116 and the first internal circuit and are formed on the active surface 111a. The input / output connection pads 118a and 118b include a high speed connection pad 118a connected to the high speed pad 114a and a low speed connection pad 118b connected to the low speed pad 114b.

한편 제 1 실시예에서는 고속 및 저속용 접속 패드(118a, 118b)가 제 1 입출력 버퍼(116)와 제 1 내부 회로 사이의 회로 배선(117a)에 연결되어 활성면(111a)에 형성된 예를 개시하였지만, 고속용 접속 패드만이 제 1 입출력 버퍼와 제 1 내부 회로 사이의 회로 배선에 연결할 수도 있다.Meanwhile, the first embodiment discloses an example in which the high speed and low speed connection pads 118a and 118b are connected to the circuit wiring 117a between the first input / output buffer 116 and the first internal circuit and formed on the active surface 111a. However, only the high speed connection pad may be connected to the circuit wiring between the first input / output buffer and the first internal circuit.

전원/접지용 접속 패드(118c)는 입출력용 접속 패드(118a, 118b)들과 동일하게 배열될 수 있도록 활성면(111a)에 형성된다.The power supply / grounding connection pad 118c is formed on the active surface 111a so as to be arranged in the same manner as the input / output connection pads 118a and 118b.

제 1 칩 패드(114)는 활성면(111a)의 중심 부분에 일렬 또는 이렬로 배열되기 때문에, 제 1 접속 패드(118)는 제 1 칩 패드(114)에서 이격되어 형성된다. 따라서 제 1 칩(112) 위에 적층되는 제 2 칩(122)은 중심에서 약간 비겨진 오프셋 (offset) 형태로 적층될 수 있다. 이때 오프셋되는 정도가 클 경우 적층 칩 패키지의 실장 면적이 커지기 때문에, 오프셋 정도는 작을수록 좋으며 100㎛ 내외로 형성될 수 있다. 이런 이유로 제 1 접속 패드(118)는 제 1 칩 패드(114)에 근접하게 형성하는 것이 바람직하다.Since the first chip pads 114 are arranged in a row or in a row at the center portion of the active surface 111a, the first connection pads 118 are formed to be spaced apart from the first chip pads 114. Therefore, the second chip 122 stacked on the first chip 112 may be stacked in an offset form slightly struck from the center. In this case, when the offset is large, the mounting area of the multilayer chip package is large. Therefore, the smaller the offset, the better and may be formed to about 100 μm. For this reason, it is preferable to form the first connection pad 118 in close proximity to the first chip pad 114.

제 1 및 제 2 칩(112, 122)의 서로 대응되는 제 1 및 제 2 접속 패드(118, 128)는 금속 범프(132)를 매개로 연결된다. 금속 범프(132)로는 솔더 범프, 금 범프 또는 니켈 범프가 사용될 수 있다. 이때 활성면(111a, 121a)이 서로 마주보게 반도체 칩(112, 122)이 적층되기 때문에, 제 1 접속 패드(118)와 제 2 접속 패드(128) 사이의 거리를 최대한 짧게 형성할 수 있다.The first and second connection pads 118 and 128 corresponding to each other of the first and second chips 112 and 122 are connected through the metal bumps 132. Solder bumps, gold bumps or nickel bumps may be used as the metal bumps 132. In this case, since the semiconductor chips 112 and 122 are stacked such that the active surfaces 111a and 121a face each other, the distance between the first connection pad 118 and the second connection pad 128 can be formed as short as possible.

그리고 제 1 칩(112)과 제 2 칩(122)의 사이에 개재되어 금속 범프(132)를 보호하는 충진층(133)이 형성되어 있다. 충진층(133)으로 에폭시 또는 실리콘 계열의 수지가 사용될 수 있다.A filling layer 133 is formed between the first chip 112 and the second chip 122 to protect the metal bumps 132. Epoxy or silicone-based resin may be used as the filling layer 133.

한편 제 1 실시예에서는 전기적 연결 수단으로 금속 범프(132)를 개시하였지만, 이방 전도성 필름(Anisotropic Conductive Film; ACF)이 사용될 수 있다. 이방 전도성 필름을 사용하는 경우 별도의 충진층을 형성하는 공정을 생략할 수 있다.Meanwhile, although the metal bump 132 is disclosed as an electrical connection means in the first embodiment, an anisotropic conductive film (ACF) may be used. In the case of using an anisotropic conductive film, a process of forming a separate filling layer may be omitted.

이때 적층 칩(130)을 외부접속단자와 연결할 수 있도록, 제 1 칩(112)에는 제 1 칩 패드(114)와 연결되어 배면(111b)으로 접속단(119d)이 노출된 제 1 관통 전극(119)이 형성되어 있다. 제 1 관통 전극(119)은 제 1 칩 패드(114)를 관통하여 형성된 관통 구멍(119a)에 도전성 물질(119c)이 충전된 구조를 갖는다. 도전성 물질(119c)과 실리콘 기판(111) 사이의 절연을 위해서 관통 구멍(119a)과 도전성 물 질(119c) 사이에는 절연층(119b)이 형성되어 있다.In this case, the first chip electrode 112 may be connected to the first chip pad 114 so that the stacked chip 130 may be connected to the external connection terminal. 119 is formed. The first through electrode 119 has a structure in which the conductive material 119c is filled in the through hole 119a formed through the first chip pad 114. An insulating layer 119b is formed between the through hole 119a and the conductive material 119c to insulate the conductive material 119c from the silicon substrate 111.

한편 제 1 실시예에서는 제 1 접속 패드(118)를 팹 공정을 통한 재배선으로 형성한 예를 개시하였지만, 도 16에 도시된 바와 같이, 웨이퍼 레벨 재배선 공정으로 형성할 수도 있다.Meanwhile, although the first embodiment discloses an example in which the first connection pads 118 are formed by redistribution through a fab process, as illustrated in FIG. 16, the first connection pad 118 may be formed by a wafer level redistribution process.

적층 칩의 웨이퍼 레벨 제조 방법Wafer level manufacturing method of laminated chip

도 7 내지 도 12는 도 4의 적층 칩(130)의 웨이퍼 레벨 제조 방법에 따른 각 단계를 보여주는 도면들이다. 한편 도면을 통틀어 동일한 도면부호는 동일한 구성요소를 나타낸다.7 to 12 are diagrams illustrating respective steps according to the wafer level manufacturing method of the stacked chip 130 of FIG. 4. On the other hand, the same reference numerals throughout the drawings represent the same components.

제 1 실시예에 따른 적층 칩의 웨이퍼 레벨 제조 방법은, 도 7에 도시된 바와 같이, 제 1 웨이퍼(110)와 제 2 웨이퍼를 준비하는 단계로부터 출발한다. 이때 제 1 웨이퍼(110)와 제 2 웨이퍼는 동일한 구조를 갖기 때문에, 제 1 웨이퍼(110)만 도시하였다.The wafer level manufacturing method of the stacked chip according to the first embodiment starts from preparing a first wafer 110 and a second wafer, as shown in FIG. In this case, since the first wafer 110 and the second wafer have the same structure, only the first wafer 110 is illustrated.

제 1 웨이퍼(110)는 복수의 제 1 칩(112)을 포함하며, 제 1 칩(112)들은 칩 절단 영역(113)에 의해 구분된다. 이때 팹 공정을 통하여 제 1 칩(112)의 활성면(111a)의 중심 부분에 제 1 칩 패드(114)가 형성되고, 제 1 칩 패드(114)에 근접하게 제 1 접속 패드(118)가 형성된다. 이때 제 1 웨이퍼(110)는 배면 연마 공정 전의 상태로 대략 700㎛ 두께를 가지며, 8인치 또는 12인치의 직경을 갖는다.The first wafer 110 includes a plurality of first chips 112, and the first chips 112 are separated by the chip cutting region 113. At this time, the first chip pad 114 is formed at the center of the active surface 111a of the first chip 112 through the fab process, and the first connection pad 118 is close to the first chip pad 114. Is formed. In this case, the first wafer 110 has a thickness of approximately 700 μm in a state before the back polishing process, and has a diameter of 8 inches or 12 inches.

다음으로 도 8에 도시된 바와 같이, 활성면(111a, 121a)이 마주보게 제 1 웨이퍼(110) 위에 제 2 웨이퍼(120)를 적층하는 단계가 진행된다. 이때 제 1 접속 패 드(118)와 제 2 접속 패드(128)는 금속 범프(131)를 매개로 접합되며, 제 1 웨이퍼(110)와 제 2 웨이퍼(120) 사이는 충진층(133)이 개재된다. 이때 제 2 웨이퍼(120)는 제 1 웨이퍼(110)에서 오프셋되어 적층된다.Next, as shown in FIG. 8, the second wafer 120 is stacked on the first wafer 110 so that the active surfaces 111a and 121a face each other. In this case, the first connection pad 118 and the second connection pad 128 are bonded to each other through the metal bump 131, and the filling layer 133 is formed between the first wafer 110 and the second wafer 120. It is interposed. In this case, the second wafer 120 is stacked on the first wafer 110 while being offset.

다음으로 도 9에 도시된 바와 같이, 제 1 웨이퍼(110)의 배면(111b)을 연마하는 단계가 진행된다. 연마 방법으로 그라인딩(grinding) 방법이 주로 사용되며, 그 외 식각 방법이나 화학적 기계적 연마 방법이 사용될 수 있다.Next, as shown in FIG. 9, the polishing of the back surface 111b of the first wafer 110 is performed. Grinding (grinding) is mainly used as the polishing method, and other etching methods or chemical mechanical polishing method may be used.

이때 연마 공정은 제조될 적층 칩의 박형화를 구현하면서, 제 1 칩 패드(114)에 관통 전극을 쉽게 형성하기 위해서 진행한다. 예컨대, 연마전 제 1 웨이퍼(110)가 700㎛ 두께를 갖는데, 연마 공정을 통하여 100㎛ 이하의 두께로 형성되며, 제 1 칩(112)의 구동에 무리가 없고 기술력이 허락한다면 더욱 얇게 가공할 수 있다.At this time, the polishing process proceeds to easily form the through electrode on the first chip pad 114 while realizing the thinning of the laminated chip to be manufactured. For example, before polishing, the first wafer 110 has a thickness of 700 μm, and is formed to a thickness of 100 μm or less through a polishing process, and may be processed thinner if the driving force of the first chip 112 is sufficient and technology permits. Can be.

다음으로 도 10에 도시된 바와 같이, 제 1 관통 전극(119)을 형성하는 단계가 진행된다. 즉 제 1 웨이퍼(110)의 배면(111b)을 통하여 제 1 칩 패드(114)로 관통 구멍(119a)을 형성한다. 관통 구멍(119a)은 원통 또는 다각기둥 형태의 수직형 구멍 뿐만 아니라, 실리콘 결정의 방향성 식각 방법 등에 의해 칩 패드(114)에 연결되는 부위 대비 배면(111b)의 입구부가 더 넓은 구멍일 수 있다. 그리고 관통 구멍(119a)에 도전성 물질(119c)을 충전함으로써 제 1 관통 전극(119)이 형성된다.Next, as shown in FIG. 10, the forming of the first through electrode 119 is performed. That is, the through hole 119a is formed in the first chip pad 114 through the rear surface 111b of the first wafer 110. The through hole 119a may be a hole in which the inlet portion of the back surface 111b is wider than a portion connected to the chip pad 114 by a directional etching method of silicon crystals, as well as a vertical hole having a cylindrical or polygonal pillar shape. The first through electrode 119 is formed by filling the through hole 119a with the conductive material 119c.

다음으로 도 11에 도시된 바와 같이, 제 2 웨이퍼(120)의 배면(121b)을 연마하는 단계가 진행된다. 이때 제 2 웨이퍼(120)의 배면(121b)을 연마하는 단계는 제 1 웨이퍼(110)를 연마하는 단계와 동일한 방법으로 진행될 수 있다.Next, as shown in FIG. 11, the polishing of the back surface 121b of the second wafer 120 is performed. In this case, the polishing of the rear surface 121b of the second wafer 120 may be performed in the same manner as the polishing of the first wafer 110.

마지막으로 도 12에 도시된 바와 같이 적층된 제 1 및 제 2 웨이퍼(110, 120)를 개별 적층 칩(130)으로 분리하는 단계가 진행된다. 즉 절단기(170)를 이용하여 제 1 및 제 2 웨이퍼(110, 120)의 칩 절단 영역(113, 123)을 따라서 제 1 칩(112)과 제 2 칩(122)을 분리함으로써, 개별 적층 칩(130)으로 분리할 수 있다.Finally, as shown in FIG. 12, the stacked first and second wafers 110 and 120 are separated into individual stacked chips 130. That is, by using the cutter 170, the first chip 112 and the second chip 122 are separated along the chip cutting regions 113 and 123 of the first and second wafers 110 and 120, thereby stacking the individual stacked chips. 130 can be separated.

이때 오프셋 정도에 따라 한 번의 절단 공정으로 개별 적층 칩으로 분리할 수도 있고, 두 번의 절단 공정으로 개별 적층 칩(130)으로 분리할 수 있다. 즉 오프셋되어 도 12에 도시된 바와 같이, 제 1 및 제 2 웨이퍼(110, 120)의 칩 절단 영역(113, 123)의 겹친 부분이 없거나, 겹친 부분이 있더라도 절단기(170)에 의해 절단되는 영역의 폭 보다는 크지 않은 경우, 제 1 웨이퍼(110)에 대한 절단 공정과 제 2 웨이퍼(120)에 대한 절단 공정을 개별적으로 진행한다. 한편 오프셋 정도가 100㎛ 작기 때문에, 적층 칩(130)의 양쪽 가장자리에 일부 충진층(133a)이 남게 되지만 적층 칩(130)을 분리하는 데는 문제가 없다.At this time, depending on the offset degree may be separated into individual stacked chips in one cutting process, may be separated into individual stacked chips 130 in two cutting processes. That is, as shown in FIG. 12 and offset, there is no overlapping portion of the chip cutting regions 113 and 123 of the first and second wafers 110 and 120, or an area to be cut by the cutter 170 even if there is an overlapping portion. If not greater than the width, the cutting process for the first wafer 110 and the cutting process for the second wafer 120 are performed separately. On the other hand, since the offset degree is 100 μm, some of the filling layer 133a remains on both edges of the stacked chip 130, but there is no problem in separating the stacked chip 130.

그리고 오프셋되더라도 제 1 및 제 2 웨이퍼의 칩 절단 영역이 겹치는 부분이 존재하고, 겹치는 부분이 절단기에 의해 절단되는 영역의 폭 보다는 큰 경우에는, 겹친 칩 절단 영역을 따라서 한 번의 절단 공정으로 진행할 수 있다. 물론 이 경우도 두 번의 절단 공정을 진행할 수 있음은 물론이다.If the portions where the chip cutting regions of the first and second wafers overlap each other are offset and the overlapping portions are larger than the width of the region cut by the cutter, the cutting process may be performed in one cutting process along the overlapping chip cutting regions. . Of course, in this case, two cutting processes can be performed.

이와 같은 제 1 실시예에 따른 적층 칩(130)은 전술된 바와 같이 웨이퍼 레벨에서 제조가 가능할 뿐만 아니라 칩 레벨에서도 가능함은 물론이다. 칩 레벨 제조 방법을 간단히 설명하면 다음과 같다. 제 1 관통 전극이 형성된 제 1 웨이퍼와 배면 연마가 완료된 제 2 웨이퍼를 준비한다. 제 1 웨이퍼와 제 2 웨이퍼를 각각 개별 제 1 및 제 2 칩으로 분리한다. 다음으로 활성면이 마주보게 제 1 칩과 제 2 칩을 적층하는 단계가 진행된다. 이때 제 1 접속 패드와 제 2 접속 패드는 금속 범프를 매개로 접합되며, 제 1 칩과 제 2 칩 사이는 충진층이 개재된다.As described above, the stacked chip 130 according to the first embodiment may not only be manufactured at the wafer level but also at the chip level. The chip level manufacturing method is briefly described as follows. A first wafer on which a first through electrode is formed and a second wafer on which back polishing is completed are prepared. The first wafer and the second wafer are separated into separate first and second chips, respectively. Next, the step of stacking the first chip and the second chip facing the active surface is performed. In this case, the first connection pad and the second connection pad are bonded to each other via a metal bump, and a filling layer is interposed between the first chip and the second chip.

이때 제 1 칩 위에 제 2 칩을 적층하는 단계는, 제 1 웨이퍼 상에서 진행하거나 배선기판 상에 제 1 칩을 부착한 이후에 진행할 수 있다.In this case, the stacking of the second chip on the first chip may be performed on the first wafer or after attaching the first chip on the wiring board.

적층 칩 패키지의 일 예Example of stacked chip package

도 13은 도 4의 적층 칩(130)을 갖는 적층 칩 패키지(200a)의 일 예를 보여주는 단면도이다. 도 13을 참조하면, 적층 칩 패키지(200a)는 배선기판(140)의 상부면(141)에 적층 칩(130)이 접속 범프(135)를 매개로 본딩되고, 배선기판(140)의 하부면(142)에 볼 형태의 외부접속단자(160)가 형성된 볼 그리드 어레이(Ball Grid Array; BGA) 타입의 반도체 패키지이다.13 is a cross-sectional view illustrating an example of a stacked chip package 200a having the stacked chips 130 of FIG. 4. Referring to FIG. 13, in the stacked chip package 200a, the stacked chip 130 is bonded to the upper surface 141 of the wiring board 140 via the connection bump 135 and the lower surface of the wiring board 140. A ball grid array (BGA) type semiconductor package in which a ball-type external connection terminal 160 is formed at 142.

적층 칩(130)의 제 1 관통 전극(119)의 접속단(119d)이 접속 범프(135)를 매개로 배선기판(140)의 상부면(141)에 실장된다. 즉 적층 칩(130)은 일종의 플립 칩 본딩 방법으로 배선기판(140)의 상부면(141)에 실장된다. 배선기판(140)과 적층 칩(130) 사이에 충진되어 접속 범프(135)를 보호하는 충진층(136)이 형성된다. 이때 접속 범프(135)로는 솔더 범프를 비롯하여 금 범프 또는 니켈 범프가 사용될 수 있으며, 충진층(136)은 언더필 방법으로 형성될 수 있다. 적층 칩(130)이 안정적으로 배선기판(140)의 상부면(141)에 실장될 수 있도록, 적층 칩(130)의 가장자리 둘레와 배선기판(130)의 상부면(141) 사이에 스페이서(137)를 개재할 수 있다. 물론 스 페이서(137)는 접속 범프(135)의 높이에 대응되는 직경을 갖는 것을 사용하는 것이 바람직하다.The connection end 119d of the first through electrode 119 of the stacked chip 130 is mounted on the upper surface 141 of the wiring board 140 via the connection bump 135. That is, the stacked chip 130 is mounted on the upper surface 141 of the wiring board 140 by a kind of flip chip bonding method. A filling layer 136 is formed between the wiring substrate 140 and the stacked chip 130 to protect the connection bump 135. In this case, as the connection bump 135, gold bumps or nickel bumps including solder bumps may be used, and the filling layer 136 may be formed by an underfill method. The spacer 137 is disposed between the edge of the stacked chip 130 and the upper surface 141 of the wiring board 130 so that the stacked chip 130 may be stably mounted on the upper surface 141 of the wiring board 140. ) Can be intervened. Of course, it is preferable to use the spacer 137 having a diameter corresponding to the height of the connection bump 135.

한편 배선기판(140)으로는 인쇄회로기판, 테이프 배선기판, 세라믹 배선기판, 실리콘 배선기판, 리드 프레임 등이 사용될 수 있다.The printed circuit board 140 may be a printed circuit board, a tape wiring board, a ceramic wiring board, a silicon wiring board, a lead frame, or the like.

배선기판(140)의 상부면(141)에 실장된 적층 칩(130)은 배선기판(140)의 상부면(141)을 봉합하는 수지 봉합부(150)에 의해 외부 환경으로부터 보호된다.The stacked chip 130 mounted on the upper surface 141 of the wiring board 140 is protected from the external environment by the resin encapsulation part 150 sealing the upper surface 141 of the wiring board 140.

그리고 외부접속단자(160)는 배선기판(140)의 하부면(142)에 형성된다. 외부접속단자(160)는 배선기판(140)의 내부 배선(143)을 통하여 접속 범프(135)와 전기적으로 연결된다. 이때 외부접속단자(160)로는 주로 솔더 볼이 사용될 수 있다.The external connection terminal 160 is formed on the bottom surface 142 of the wiring board 140. The external connection terminal 160 is electrically connected to the connection bump 135 through the internal wiring 143 of the wiring board 140. In this case, a solder ball may be mainly used as the external connection terminal 160.

따라서 제 1 칩(112)의 제 1 접속 패드(118)와 제 2 칩(122)의 제 2 접속 패드(128)가 금속 범프(132)에 의해 전기적으로 연결되고, 제 1 칩(112)의 제 1 칩 패드(114)에 형성된 제 1 관통 전극(119)이 외부접속단자(160)와 전기적으로 연결되기 때문에, 입력 신호는 외부접속단자(160)를 통하여 제 1 칩(112)의 제 1 칩 패드(114)로 입력된 후, 제 1 칩(112)의 입출력 버퍼를 거쳐 연결된 제 1 및 제 2 접속 패드(118, 128)를 통하여 제 1 또는 제 2 칩(112, 122)의 내부 회로와 연결되어 입력된다. 이로 인해 외부접속단자(160)에서 바라보는 적층 칩 패키지(200a)의 입력 용량 로딩을 단품 패키지 수준으로 낮출 수 있기 때문에, 단품 패키지와 동일하거나 유사한 속도를 유지하면서 고속화를 지원하면서 용량을 두 배로 증가시킬 수 있다.Therefore, the first connection pad 118 of the first chip 112 and the second connection pad 128 of the second chip 122 are electrically connected by the metal bumps 132, and Since the first through electrode 119 formed on the first chip pad 114 is electrically connected to the external connection terminal 160, the input signal is connected to the first of the first chip 112 through the external connection terminal 160. After the input to the chip pad 114, the internal circuit of the first or second chip 112, 122 through the first and second connection pads (118, 128) connected via the input and output buffer of the first chip 112 It is connected to and input. As a result, the input capacity loading of the stacked chip package 200a viewed from the external connection terminal 160 can be reduced to a single package level, thereby doubling the capacity while supporting high speed while maintaining the same or similar speed as the single package. You can.

적층 칩 패키지의 다른 예Other examples of stacked chip packages

일 예에 따른 적층 칩 패키지는 적층 칩이 접속 범프를 매개로 배선기판을 통하여 외부접속단자와 연결된 예를 개시하였지만, 도 14에 도시된 바와 같이, 본딩 와이어(235)를 매개로 배선기판(240)을 통하여 외부접속단자(260)와 연결될 수 있다.In the stacked chip package according to an example, the stacked chip is connected to an external connection terminal through a wiring board through a connection bump, but as illustrated in FIG. 14, the wiring board 240 is connected to a bonding wire 235. It may be connected to the external connection terminal 260 through.

도 14를 참조하면, 적층 칩 패키지(200b)는 배선기판(240)의 중심 부분에 형성된 창(245)에 적층 칩(130)의 제 1 관통 전극(119)의 접속단(119d)이 노출되게 실장된 보드 온 칩(Board On Chip; BOC) 타입의 반도체 패키지이다.Referring to FIG. 14, the stacked chip package 200b may expose the connection end 119d of the first through electrode 119 of the stacked chip 130 to the window 245 formed at the center portion of the wiring board 240. It is a board-on-chip (BOC) type semiconductor package mounted.

배선기판(240)의 중심 부분에 형성된 창(245)에 적층 칩(130)의 제 1 관통 전극(119)의 접속단(119d)이 노출되게 배선기판(240)의 상부면(241)에 부착된다.Attached to the upper surface 241 of the wiring board 240 so that the connection end 119d of the first through electrode 119 of the stacked chip 130 is exposed in the window 245 formed at the center portion of the wiring board 240. do.

본딩 와이어(235)는 창(245)을 통하여 제 1 관통 전극(119)의 접속단(119d)과 배선기판(240)을 전기적으로 연결한다.The bonding wire 235 electrically connects the connection terminal 119d of the first through electrode 119 and the wiring board 240 through the window 245.

배선기판(240)의 상부면(241)에 실장된 적층 칩(130)과 배선기판(240)의 창(245)에 노출된 본딩 와이어(235)를 봉합하는 수지 봉합부(251, 253)에 의해 외부 환경으로부터 보호된다. 이때 수지 봉합부(251, 253)는 배선기판(240)의 상부면(241)의 적층 칩(130)을 봉합하는 제 1 수지 봉합부(251)와, 배선기판(240)의 창(245)에 노출된 본딩 와이어(235)를 봉합하는 제 2 수지 봉합부(253)를 포함한다. 이때 제 1 및 제 2 수지 봉합부(251, 253)는 함께 형성될 수도 있고, 별도로 형성될 수 있다.Resin encapsulation portions 251 and 253 sealing the laminated chip 130 mounted on the upper surface 241 of the wiring board 240 and the bonding wire 235 exposed to the window 245 of the wiring board 240. By protecting it from the external environment. In this case, the resin sealing parts 251 and 253 may include the first resin sealing part 251 for sealing the stacked chip 130 of the upper surface 241 of the wiring board 240, and the window 245 of the wiring board 240. And a second resin encapsulation portion 253 for encapsulating the bonding wire 235 exposed to the substrate. In this case, the first and second resin sealing parts 251 and 253 may be formed together or separately formed.

그리고 볼 형태의 외부접속단자(260)는 제 2 수지 봉합부(253) 외측의 배선 기판(240)의 하부면(242)에 형성된다. 외부접속단자(260)는 배선기판(240) 및 본딩 와이어(235)를 매개로 적층 칩(130)의 제 1 관통 전극(119)과 전기적으로 연결된다. 외부접속단자(260)는 모기판에 실장할 수 있도록 적어도 제 2 수지 봉합부(253) 보다는 높게 형성된다. 이때 외부접속단자(260)로는 주로 솔더 볼이 사용된다.The external connection terminal 260 having a ball shape is formed on the lower surface 242 of the wiring board 240 outside the second resin sealing unit 253. The external connection terminal 260 is electrically connected to the first through electrode 119 of the stacked chip 130 through the wiring board 240 and the bonding wire 235. The external connection terminal 260 is formed at least higher than the second resin sealing portion 253 to be mounted on the mother substrate. At this time, a solder ball is mainly used as the external connection terminal 260.

한편 적층 칩 패키지(200b)로 BOC 타입의 반도체 패키지를 예시하였지만, 배선기판으로 리드 프레임을 사용하여 리드 온 칩(Lead On Chip; LOC) 타입의 반도체 패키지로 구현할 수도 있다.Meanwhile, although the BOC type semiconductor package is illustrated as the stacked chip package 200b, a lead on chip (LOC) type semiconductor package may be implemented using a lead frame as a wiring board.

제 2 실시예Second embodiment

제 1 실시예에 따른 적층 칩은 제 1 칩 패드에 제 1 관통 전극이 형성된 예를 개시하였지만, 도 15에 도시된 바와 같이, 제 2 칩 패드(224)에 제 2 관통 전극(229)을 형성할 수 있다.Although the stacked chip according to the first embodiment has disclosed an example in which the first through electrode is formed on the first chip pad, as shown in FIG. 15, the second through electrode 229 is formed on the second chip pad 224. can do.

도 15를 참조하면, 제 2 실시예에 따른 적층 칩(230)은 제 2 칩(222)의 제 2 칩 패드(224)를 관통하는 제 2 관통 전극(229)이 형성된 것을 제외하면 제 1 실시예에 따른 적층 칩과 동일한 구조를 갖는다.Referring to FIG. 15, the multilayer chip 230 according to the second embodiment of the present invention has a first implementation except that a second through electrode 229 penetrating the second chip pad 224 of the second chip 222 is formed. It has the same structure as the stacked chip according to the example.

제 2 실시예에 따른 적층 칩(230) 또한 웨이퍼 레벨 또는 칩 레벨에서 제조될 수 있다. 웨이퍼 레벨의 제조 방법의 경우, 관통 전극이 형성된 두 장의 웨이퍼를 준비한 다음, 활성면이 마주보게 적층하고 개별 적층 칩으로 분리하는 공정을 진행함으로써, 적층 칩을 얻을 수도 있다.The stacked chip 230 according to the second embodiment may also be manufactured at the wafer level or the chip level. In the case of the wafer-level manufacturing method, a stacked chip may be obtained by preparing two wafers having a through electrode formed thereon, and then stacking the active surfaces facing each other and separating them into individual stacked chips.

그리고 칩 레벨 제조 공정은, 제 1 및 제 2 관통 전극을 갖는 웨이퍼를 준비하는 것을 제외하면 제 1 실시예에 따른 칩 레벨 제조 공정과 동일한 방법으로 진행될 수 있다.The chip level fabrication process may be performed in the same manner as the chip level fabrication process according to the first embodiment except that the wafer having the first and second through electrodes is prepared.

제 3 실시예Third embodiment

제 1 실시예에 따른 적층 칩은 고속 및 저속 패드에 모두 연결되게 접속 패드가 형성된 예를 개시하였지만, 도 16 내지 도 19에 도시된 바와 같이, 고속 패드(314a)에만 연결되게 접속 패드(318a)를 형성할 수 있다.Although the stacked chip according to the first embodiment has disclosed an example in which the connection pad is formed to be connected to both the high speed and the low speed pad, as shown in FIGS. 16 to 19, the connection pad 318a is connected to only the high speed pad 314a. Can be formed.

도 16 내지 도 19를 참조하면, 제 3 실시예에 따른 적층 칩(312)의 접속 패드(318)는 웨이퍼 레벨 재배선 공정으로 형성된다. 이때 반도체 칩(312)은, 제 1 실시예의 경우 제 1 칩에 해당되며, 제 2 실시예에의 경우 제 1 및 제 2 칩에 해당될 수 있다.16 to 19, the connection pad 318 of the stacked chip 312 according to the third embodiment is formed by a wafer level redistribution process. In this case, the semiconductor chip 312 may correspond to the first chip in the first embodiment, and may correspond to the first and second chips in the second embodiment.

먼저 칩 패드(314) 중 고속 패드(314a)는, 도 16 및 도 17에 도시된 바와 같이, 웨이퍼 레벨 재배선 공정으로 형성된 고속용 접속 패드(318a)와 연결된다. 활성면(311a)에 입출력 버퍼(316)와 내부 회로를 연결하는 회로 배선(317a)에 연결된 매개 패드(381)가 활성면(311a)에 형성된다. 매개 패드(381)는 입출력 버퍼(316)를 경유하여 활성면(311a)에 형성된 고속 패드(314a)와 연결된다. 매개 패드(381) 및 고속 패드(314a)를 제외한 활성면(311a)은 보호층(315)으로 덮여 보호된다. 매개 패드(381)를 제외한 보호층(351)을 덮도록 제 1 절연층(383)이 형성된다. 매개 패드(381)를 포함한 제 1 절연층(383)의 상부에는 재배선층(384a)이 형성되며, 재배 선층(384a)의 일단에는 접속 패드(318a)가 마련되어 있다. 재배선층(384a)을 보호하는 제 2 절연층(385)이 제 1 절연층(363) 상부에 형성된다. 그리고 재배선층(384a)의 고속용 접속 패드(318a)가 노출되게 제 2 절연층(385)에 개방부(386)가 형성된다.First, the high speed pad 314a of the chip pad 314 is connected to the high speed connection pad 318a formed by the wafer level redistribution process, as shown in FIGS. 16 and 17. An intermediate pad 381 connected to the circuit wiring 317a connecting the input / output buffer 316 and the internal circuit to the active surface 311a is formed on the active surface 311a. The intermediate pad 381 is connected to the high speed pad 314a formed on the active surface 311a via the input / output buffer 316. The active surface 311a except for the intermediate pad 381 and the high speed pad 314a is covered and protected by the protective layer 315. The first insulating layer 383 is formed to cover the protective layer 351 except for the intermediate pad 381. The redistribution layer 384a is formed on the upper part of the 1st insulating layer 383 including the intermediate pad 381, and the connection pad 318a is provided in the one end of the redistribution layer 384a. A second insulating layer 385 that protects the redistribution layer 384a is formed on the first insulating layer 363. An opening 386 is formed in the second insulating layer 385 so that the high speed connection pad 318a of the redistribution layer 384a is exposed.

그리고 관통 전극(319)이 고속 패드(314a)를 관통하여 형성되며, 관통 전극(319)의 접속단(319d)이 반도체 칩(312)의 배면(311b)으로 노출된다.The through electrode 319 is formed through the high speed pad 314a, and the connection end 319d of the through electrode 319 is exposed to the back surface 311b of the semiconductor chip 312.

한편 매개 패드(381)가 활성면(311a)에 형성된 예를 개시하였지만, 재배선층(384a)이 직접 회로 배선(317a)에 연결될 수도 있다.Meanwhile, although the example in which the intermediate pad 381 is formed on the active surface 311a has been disclosed, the redistribution layer 384a may be connected to the direct circuit wiring 317a.

다음으로 칩 패드(314) 중 저속 패드(314b)는, 도 16 및 도 18에 도시된 바와 같이, 입출력 버퍼와 내부 회로를 연결하는 회로 배선에 연결되도록 접속 패드를 형성하지 않고 재배선으로 형성된 저속용 접속 패드(318b)에 직접 연결된다. 이때 저속용 접속 패드(318b)는 제 2 절연층(385)에 형성된 개방부(386)를 통하여 외부로 노출되며, 고속용 접속 패드(318a)의 배열에 대응되게 형성된다. 즉 저속 패드(314b)는 입력 용량 로딩의 증가가 크게 문제되지 않기 때문에, 저속 패드(314b)에 직접 연결되게 저속용 접속 패드(318b)를 형성한다.Next, as shown in FIGS. 16 and 18, the low speed pad 314b of the chip pad 314 is a low speed formed by rewiring without forming a connection pad so as to be connected to a circuit wiring connecting an input / output buffer and an internal circuit. Direct connection to the connection pad 318b. In this case, the low speed connection pad 318b is exposed to the outside through the opening 386 formed in the second insulating layer 385 and is formed to correspond to the arrangement of the high speed connection pad 318a. That is, since the low speed pad 314b does not significantly increase the input capacitance loading, the low speed connection pad 318b is formed to be directly connected to the low speed pad 314b.

물론 저속 패드(314b)를 관통하여 제 1 관통 전극(319)이 형성된다.Of course, the first through electrode 319 is formed through the low speed pad 314b.

다음으로 칩 패드(314) 중 전원/접지용 패드(314c)는, 도 16 및 도 19에 도시된 바와 같이, 재배선으로 형성된 전원/접지용 접속 패드(318c)에 직접 연결된다. 전원/접지용 재배선층(384c)의 일단은 내부 회로의 전원/접지 배선에 연결되고, 타단은 전원/접지용 패드(314c)에 연결된다. 이때 전원/접지용 재배선층(384c) 의 일단은 내부 회로의 전원/접지 배선에 연결되어 활성면(311a)에 위에 형성된 제 1 연결 패드(382)에 연결될 수 있다. 전원/접지용 접속 패드(318c)는 제 2 절연층(385)에 형성된 개방부(386)를 통하여 외부에 노출되며, 고속용 접속 패드(318a) 및 저속용 접속 패드(318b)의 배열에 대응되게 형성된다.Next, the power / grounding pad 314c of the chip pad 314 is directly connected to the power / grounding connection pad 318c formed by redistribution, as shown in FIGS. 16 and 19. One end of the power supply / grounding redistribution layer 384c is connected to the power supply / grounding wiring of the internal circuit, and the other end is connected to the power supply / grounding pad 314c. In this case, one end of the power supply / grounding redistribution layer 384c may be connected to the power supply / grounding wire of the internal circuit and connected to the first connection pad 382 formed on the active surface 311a. The power / grounding connection pad 318c is exposed to the outside through an opening 386 formed in the second insulating layer 385 and corresponds to the arrangement of the high speed connection pad 318a and the low speed connection pad 318b. Is formed.

전원/접지용 재배선층(384c)은 안정적인 전원 공급 및 접지를 이룰 수 있도록, 다른 재배선층에 비해서 넓게 형성된다. 예컨대 전원/접지용 재배선층(384c)은 구불구불한 길(meander)이나 나선(spiral) 형태로 형성될 수 있다.The power supply / grounding redistribution layer 384c is formed wider than other redistribution layers to achieve stable power supply and grounding. For example, the power / grounding redistribution layer 384c may be formed in a meander or spiral form.

물론 전원/접지용 패드(314c)를 관통하여 제 1 관통 전극(319)이 형성된다.Of course, the first through electrode 319 is formed through the power / grounding pad 314c.

한편, 본 명세서와 도면에 개시된 본 발명의 실시예들은 이해를 돕기 위해 특정 예를 제시한 것에 지나지 않으며, 본 발명의 범위를 한정하고자 하는 것은 아니다. 여기에 개시된 실시예들 이외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명한 것이다.On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to aid understanding, and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is apparent to those skilled in the art that other modifications based on the technical idea of the present invention may be implemented.

따라서, 본 발명의 구조를 따르면 외부접속단자와 연결되는 하나의 입출력 버퍼를 통하여 두 개의 반도체 칩의 내부 회로가 연결된다. 즉 외부접속단자를 통하여 입력되는 신호는 제 1 칩의 칩 패드 및 입출력 버퍼를 거쳐 연결된 제 1 및 제 2 접속 패드를 통하여 제 1 칩 또는 제 2 칩의 내부 회로로 전송된다. 이로 인해 입력 용량 로딩을 단품 패키지 수준으로 낮출 수 있기 때문에, 단품 패키지와 동일하거나 유사한 속도를 유지하면서 용량을 두 배로 증가시킬 수 있다.Therefore, according to the structure of the present invention, the internal circuits of two semiconductor chips are connected through one input / output buffer connected to an external connection terminal. That is, the signal input through the external connection terminal is transmitted to the internal circuit of the first chip or the second chip through the first and second connection pads connected through the chip pad and the input / output buffer of the first chip. This allows the input capacity loading to be lowered to a single package level, thereby doubling the capacity while maintaining the same or similar speed as the single package.

또한 입력 용량 로딩이 감소되기 때문에, 시스템 레벨 신호 무결성을 향상시킬 수 있는 장점도 있다.It also has the advantage of improving system-level signal integrity because input capacitance loading is reduced.

Claims (20)

활성면이 서로 마주보게 두 개의 반도체 칩이 적층된 적층 칩으로,A stacked chip in which two semiconductor chips are stacked with their active surfaces facing each other. 상기 반도체 칩은,The semiconductor chip, 활성면과, 상기 활성면에 반대되는 배면을 갖는 실리콘 기판과;A silicon substrate having an active surface and a back surface opposite the active surface; 상기 실리콘 기판의 활성면 내에 형성된 내부 회로와;An internal circuit formed in an active surface of the silicon substrate; 상기 내부 회로와 연결된 칩 패드들로, 상기 내부 회로와 입출력 버퍼를 매개로 연결된 입출력 패드를 갖는 칩 패드들과;Chip pads connected to the internal circuit, the chip pads having input / output pads connected through the internal circuit and an input / output buffer; 상기 칩 패드들과 연결되어 활성면에 형성되는 접속 패드들로, 상기 입출력 버퍼와 상기 내부 회로 사이에 연결되어 활성면에 형성된 적어도 하나 이상의 입출력용 접속 패드를 갖는 접속 패드들;을 포함하며,And connection pads connected to the chip pads and formed on an active surface, the connection pads connected between the input / output buffer and the internal circuit and having at least one connection pad for input / output formed on the active surface. 상기 두 개의 반도체 칩은 상기 접속 패드들끼리 전기적으로 연결되며, 적어도 하나의 반도체 칩은 상기 칩 패드와 연결되어 배면으로 접속단이 노출된 제 1 관통 전극이 형성되어 있는 것을 특징으로 하는 적층 칩.Wherein the two semiconductor chips are electrically connected to the connection pads, and the at least one semiconductor chip is connected to the chip pad and has a first through electrode having a connection end exposed at a rear thereof. 제 1항에 있어서, 상기 반도체 칩은 제 1 칩과, 상기 제 1 칩의 활성면에 적층된 제 2 칩을 포함하며,The semiconductor chip of claim 1, wherein the semiconductor chip comprises a first chip and a second chip stacked on an active surface of the first chip. 상기 제 1 관통 전극은 상기 제 1 칩의 칩 패드를 관통하여 형성된 것을 특징으로 하는 적층 칩.And the first through electrode is formed through the chip pad of the first chip. 제 2항에 있어서, 상기 접속 패드는 상기 활성면 위에 재배선되어 형성된 것을 특징으로 하는 적층 칩.The multilayer chip of claim 2, wherein the connection pads are redistributed on the active surface. 제 3항에 있어서, 상기 입출력 패드는 고속 패드와 저속 패드를 포함하며,The method of claim 3, wherein the input / output pad includes a high speed pad and a low speed pad, 상기 고속 패드는 상기 입출력용 접속 패드에 연결되는 것을 특징으로 하는 적층 칩.And the high speed pad is connected to the connection pad for input / output. 제 4항에 있어서, 일단이 상기 저속 패드에 연결되어 상기 활성면 위에 재배선되어 형성되며, 타단에 저속용 접속 패드를 갖는 저속용 재배선층;을 포함하는 것을 특징으로 하는 적층 칩.5. The stacked chip of claim 4, wherein one end of the low speed redistribution layer is connected to the low speed pad and is redistributed on the active surface and has a low speed connection pad at the other end thereof. 제 5항에 있어서, 일단이 상기 내부 회로의 전원/접지 배선에 연결되어 상기 활성면 위에 재배선되어 형성되며, 전원/접지용 접속 패드를 갖는 전원/접지용 재배선층;을 더 포함하며,The power supply / grounding redistribution layer of claim 5, further comprising: a power supply / grounding redistribution layer having one end connected to the power supply / grounding wire of the internal circuit and redistributed on the active surface and having a power supply / grounding connection pad. 상기 전원/접지용 재배선층은 다른 재배선층에 비해서 넓게 형성된 것을 특징으로 하는 적층 칩.The power supply / grounding redistribution layer is a laminated chip, characterized in that formed wider than other redistribution layer. 제 6항에 있어서, 상기 칩 패드는 전원/접지 패드를 더 포함하며,The method of claim 6, wherein the chip pad further comprises a power / ground pad, 상기 전원/접지 패드는 상기 전원/접지용 재배선층의 타단에 연결되는 것을 특징으로 하는 적층 칩.And the power / grounding pad is connected to the other end of the power / grounding redistribution layer. 제 2항에 있어서, 상기 제 2 칩은 상기 칩 패드와 연결된 제 2 관통 전극을 더 포함하는 것을 특징으로 하는 적층 칩.3. The stacked chip of claim 2, wherein the second chip further comprises a second through electrode connected to the chip pad. 제 2항에 있어서, 상기 반도체 칩은 센터 패드형 반도체 칩인 것을 특징으로 하는 적층 칩.3. The stacked chip of claim 2, wherein the semiconductor chip is a center pad type semiconductor chip. 제 2항 내지 제 9항의 어느 한 항에 있어서, 상기 제 1 및 제 2 칩의 상기 접속 패드들은 금속 범프를 매개로 전기적으로 연결된 것을 특징으로 하는 적층 칩.10. The stacked chip of any one of claims 2 to 9, wherein the connection pads of the first and second chips are electrically connected via metal bumps. 제 10항에 있어서, 상기 제 1 칩의 활성면과 상기 제 2 칩의 활성면 사이에 개재되어 상기 금속 범프를 보호하는 충진층;을 더 포함하는 것을 특징으로 하는 적층 칩.The stacked chip of claim 10, further comprising a filling layer interposed between the active surface of the first chip and the active surface of the second chip to protect the metal bumps. 제 2항 내지 제 9항의 어느 한 항에 있어서, 상기 제 1 및 제 2 칩의 상기 접속 패드들은 이방 전도성 필름(Anisotropic Conductive Film; ACF)을 매개로 전기적으로 연결된 것을 특징으로 하는 적층 칩.10. The stacked chip of any one of claims 2 to 9, wherein the connection pads of the first and second chips are electrically connected through an anisotropic conductive film (ACF). 제 10항에 따른 칩 적층 구조를 갖는 적층 칩과;A stacked chip having a chip stack structure according to claim 10; 상부면과 하부면을 가지며, 상기 적층 칩의 제 1 칩의 배면이 상기 상부면을 향하도록 실장되며, 상기 제 1 칩의 배면으로 노출된 상기 제 1 관통 전극의 접속단이 전기적으로 연결되는 배선기판과;A wiring having an upper surface and a lower surface, the back surface of the first chip of the stacked chip facing the upper surface, and a connection end of the first through electrode exposed to the back surface of the first chip electrically connected thereto; A substrate; 상기 적층 칩이 실장된 상기 배선기판의 영역을 봉합하는 수지 봉합부; 및A resin encapsulation portion sealing an area of the wiring board on which the stacked chip is mounted; And 상기 배선기판의 하부면에 형성되며, 상기 제 1 관통 전극의 접속단과 전기적으로 연결되는 외부접속단자;를 포함하는 것을 특징으로 적층 칩 패키지.And an external connection terminal formed on a lower surface of the wiring board and electrically connected to a connection end of the first through electrode. 제 13항에 있어서, 상기 제 1 관통 전극의 접속단과 상기 배선기판 사이에 개재된 접속 범프;를 더 포함하는 것을 특징으로 하는 적층 칩 패키지.The multilayer chip package of claim 13, further comprising a connection bump interposed between a connection end of the first through electrode and the wiring board. 제 14항에 있어서, 상기 배선기판과 상기 제 1 칩 사이에 충전되어 상기 접속 범프를 보호하는 충진층;을 더 포함하는 것을 특징으로 하는 적층 칩 패키지.The multilayer chip package of claim 14, further comprising a filling layer filling between the wiring board and the first chip to protect the connection bumps. 제 15항에 있어서, 상기 제 1 칩의 배면의 가장자리 둘레와 상기 배선기판의 상부면 사이에 개재된 스페이서;를 더 포함하는 것을 특징으로 하는 적층 칩 패키지.The multilayer chip package of claim 15, further comprising a spacer interposed between an edge of a rear surface of the first chip and an upper surface of the wiring board. 제 13항에 있어서, 상기 배선기판은 상기 제 1 관통 전극의 접속단이 노출되게 창이 형성되어 있으며,The method of claim 13, wherein the wiring board is formed with a window to expose the connection end of the first through electrode, 상기 창을 통하여 상기 배선기판과 상기 제 1 관통 전극의 접속단을 연결하 는 본딩 와이어;를 포함하는 것을 특징으로 하는 적층 칩 패키지.And a bonding wire connecting the connection end of the wiring board and the first through electrode to each other through the window. 제 17항에 있어서, 상기 수지 봉합부는,The method of claim 17, wherein the resin sealing portion, 상기 배선기판의 상부면에 실장된 상기 적층 칩을 봉합하는 제 1 수지 봉합부와;A first resin encapsulation unit encapsulating the stacked chip mounted on an upper surface of the wiring board; 상기 배선기판의 하부면의 상기 창을 봉합하여 형성된 제 2 수지 봉합부;를 포함하는 것을 특징으로 하는 적층 칩 패키지.And a second resin sealing portion formed by sealing the window of the lower surface of the wiring board. 활성면이 서로 마주보게 두 개의 반도체 칩이 적층된 적층 칩으로,A stacked chip in which two semiconductor chips are stacked with their active surfaces facing each other. 상기 반도체 칩은,The semiconductor chip, 활성면과, 상기 활성면에 반대되는 배면을 갖는 실리콘 기판과;A silicon substrate having an active surface and a back surface opposite the active surface; 상기 실리콘 기판의 활성면 내에 형성된 내부 회로와;An internal circuit formed in an active surface of the silicon substrate; 상기 내부 회로와 입출력 버퍼를 매개로 연결된 입출력 패드들과;Input / output pads connected through the internal circuit and an input / output buffer; 상기 입출력 버퍼와 상기 내부 회로 사이에 연결되어 활성면에 형성된 적어도 하나 이상의 접속 패드;를 포함하며And at least one connection pad connected between the input / output buffer and the internal circuit and formed on an active surface. 상기 두 개의 반도체 칩은 상기 접속 패드들끼리 전기적으로 연결되며, 적어도 하나의 반도체 칩은 상기 입출력 패드와 연결되어 배면으로 접속단이 노출된 관통 전극이 형성되어 있는 것을 특징으로 하는 적층 칩.Wherein the two semiconductor chips are electrically connected to the connection pads, and at least one semiconductor chip is connected to the input / output pad and has a through electrode having a connection end exposed at a rear thereof. 제 19항에 있어서, 상기 두 개의 반도체 칩의 상기 접속 패드들은 금속 범프 를 매개로 전기적으로 연결된 것을 특징으로 하는 적층 칩.20. The stacked chip of claim 19, wherein the connection pads of the two semiconductor chips are electrically connected through metal bumps.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8097940B2 (en) 2008-10-14 2012-01-17 Samsung Electronics Co., Ltd. Stack package
US8125068B2 (en) 2008-08-22 2012-02-28 Samsung Electronics Co., Ltd. Semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack, a semiconductor device package and an electronic apparatus including the semiconductor chip
WO2014112758A1 (en) * 2013-01-18 2014-07-24 (주)실리콘화일 Dual-substrate stack memory
KR20140110619A (en) * 2013-03-08 2014-09-17 삼성전자주식회사 Semiconductor package

Families Citing this family (221)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100699807B1 (en) * 2006-01-26 2007-03-28 삼성전자주식회사 Stack chip and stack chip package comprising the same
US20080001271A1 (en) * 2006-06-30 2008-01-03 Sony Ericsson Mobile Communications Ab Flipped, stacked-chip IC packaging for high bandwidth data transfer buses
KR100800473B1 (en) * 2006-06-30 2008-02-04 삼성전자주식회사 Stack chip having redistributed chip pad and stack chip package using the same
US7867878B2 (en) * 2007-09-21 2011-01-11 Infineon Technologies Ag Stacked semiconductor chips
KR100910229B1 (en) * 2007-11-13 2009-07-31 주식회사 하이닉스반도체 Stacked semiconductor package
KR101176187B1 (en) 2007-11-21 2012-08-22 삼성전자주식회사 Stacked semiconductor device and method for thereof serial path build up
US8076786B2 (en) * 2008-07-11 2011-12-13 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for packaging a semiconductor package
KR101009103B1 (en) * 2008-10-27 2011-01-18 삼성전기주식회사 A dual face package and a fabricating method for the same
KR20100056247A (en) * 2008-11-19 2010-05-27 삼성전자주식회사 Semiconductor package having adhesive layer
US20100193930A1 (en) * 2009-02-02 2010-08-05 Samsung Electronics Co., Ltd. Multi-chip semiconductor devices having conductive vias and methods of forming the same
US7986042B2 (en) 2009-04-14 2011-07-26 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8258810B2 (en) 2010-09-30 2012-09-04 Monolithic 3D Inc. 3D semiconductor device
US8669778B1 (en) 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device
US8384426B2 (en) 2009-04-14 2013-02-26 Monolithic 3D Inc. Semiconductor device and structure
US8373439B2 (en) * 2009-04-14 2013-02-12 Monolithic 3D Inc. 3D semiconductor device
US9711407B2 (en) 2009-04-14 2017-07-18 Monolithic 3D Inc. Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
US9509313B2 (en) * 2009-04-14 2016-11-29 Monolithic 3D Inc. 3D semiconductor device
US8058137B1 (en) 2009-04-14 2011-11-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8362482B2 (en) 2009-04-14 2013-01-29 Monolithic 3D Inc. Semiconductor device and structure
US8395191B2 (en) 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US8362800B2 (en) 2010-10-13 2013-01-29 Monolithic 3D Inc. 3D semiconductor device including field repairable logics
US8427200B2 (en) * 2009-04-14 2013-04-23 Monolithic 3D Inc. 3D semiconductor device
US8754533B2 (en) 2009-04-14 2014-06-17 Monolithic 3D Inc. Monolithic three-dimensional semiconductor device and structure
US9577642B2 (en) * 2009-04-14 2017-02-21 Monolithic 3D Inc. Method to form a 3D semiconductor device
US8405420B2 (en) 2009-04-14 2013-03-26 Monolithic 3D Inc. System comprising a semiconductor device and structure
US8378715B2 (en) 2009-04-14 2013-02-19 Monolithic 3D Inc. Method to construct systems
KR101078734B1 (en) * 2009-07-07 2011-11-02 주식회사 하이닉스반도체 Semiconductor Package and method for fabricating thereof and Stack Package using the same
US10157909B2 (en) 2009-10-12 2018-12-18 Monolithic 3D Inc. 3D semiconductor device and structure
US8742476B1 (en) 2012-11-27 2014-06-03 Monolithic 3D Inc. Semiconductor device and structure
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US10366970B2 (en) 2009-10-12 2019-07-30 Monolithic 3D Inc. 3D semiconductor device and structure
US8294159B2 (en) 2009-10-12 2012-10-23 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9099424B1 (en) 2012-08-10 2015-08-04 Monolithic 3D Inc. Semiconductor system, device and structure with heat removal
US8536023B2 (en) 2010-11-22 2013-09-17 Monolithic 3D Inc. Method of manufacturing a semiconductor device and structure
US8450804B2 (en) 2011-03-06 2013-05-28 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US10388863B2 (en) 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
US8581349B1 (en) 2011-05-02 2013-11-12 Monolithic 3D Inc. 3D memory semiconductor device and structure
US10354995B2 (en) 2009-10-12 2019-07-16 Monolithic 3D Inc. Semiconductor memory device and structure
US11984445B2 (en) 2009-10-12 2024-05-14 Monolithic 3D Inc. 3D semiconductor devices and structures with metal layers
US8476145B2 (en) 2010-10-13 2013-07-02 Monolithic 3D Inc. Method of fabricating a semiconductor device and structure
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US7927919B1 (en) * 2009-12-03 2011-04-19 Powertech Technology Inc. Semiconductor packaging method to save interposer
US8541819B1 (en) 2010-12-09 2013-09-24 Monolithic 3D Inc. Semiconductor device and structure
US8298875B1 (en) 2011-03-06 2012-10-30 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8461035B1 (en) 2010-09-30 2013-06-11 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8026521B1 (en) 2010-10-11 2011-09-27 Monolithic 3D Inc. Semiconductor device and structure
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US8492886B2 (en) 2010-02-16 2013-07-23 Monolithic 3D Inc 3D integrated circuit with logic
US8373230B1 (en) 2010-10-13 2013-02-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
JP2011249582A (en) * 2010-05-27 2011-12-08 Elpida Memory Inc Semiconductor device
US8642416B2 (en) 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
US8901613B2 (en) 2011-03-06 2014-12-02 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US9953925B2 (en) 2011-06-28 2018-04-24 Monolithic 3D Inc. Semiconductor system and device
US9219005B2 (en) 2011-06-28 2015-12-22 Monolithic 3D Inc. Semiconductor system and device
US10217667B2 (en) 2011-06-28 2019-02-26 Monolithic 3D Inc. 3D semiconductor device, fabrication method and system
US8273610B2 (en) 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US10497713B2 (en) 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US8163581B1 (en) 2010-10-13 2012-04-24 Monolith IC 3D Semiconductor and optoelectronic devices
US10290682B2 (en) 2010-10-11 2019-05-14 Monolithic 3D Inc. 3D IC semiconductor device and structure with stacked memory
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US8114757B1 (en) 2010-10-11 2012-02-14 Monolithic 3D Inc. Semiconductor device and structure
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US9197804B1 (en) 2011-10-14 2015-11-24 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US8379458B1 (en) 2010-10-13 2013-02-19 Monolithic 3D Inc. Semiconductor device and structure
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US10679977B2 (en) 2010-10-13 2020-06-09 Monolithic 3D Inc. 3D microdisplay device and structure
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11984438B2 (en) 2010-10-13 2024-05-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US8283215B2 (en) 2010-10-13 2012-10-09 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11121021B2 (en) 2010-11-18 2021-09-14 Monolithic 3D Inc. 3D semiconductor device and structure
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US11615977B2 (en) 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US20120193788A1 (en) 2011-01-31 2012-08-02 Advanced Micro Devices, Inc. Stacked semiconductor chips packaging
US8975670B2 (en) 2011-03-06 2015-03-10 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US10388568B2 (en) 2011-06-28 2019-08-20 Monolithic 3D Inc. 3D semiconductor device and system
US8569884B2 (en) 2011-08-15 2013-10-29 Tessera, Inc. Multiple die in a face down package
US8687399B2 (en) 2011-10-02 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US9029173B2 (en) 2011-10-18 2015-05-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9000557B2 (en) 2012-03-17 2015-04-07 Zvi Or-Bach Semiconductor device and structure
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US10600888B2 (en) 2012-04-09 2020-03-24 Monolithic 3D Inc. 3D semiconductor device
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US8686428B1 (en) 2012-11-16 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US8574929B1 (en) 2012-11-16 2013-11-05 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US8674470B1 (en) 2012-12-22 2014-03-18 Monolithic 3D Inc. Semiconductor device and structure
US11961827B1 (en) 2012-12-22 2024-04-16 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11967583B2 (en) 2012-12-22 2024-04-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US9385058B1 (en) 2012-12-29 2016-07-05 Monolithic 3D Inc. Semiconductor device and structure
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US9871034B1 (en) 2012-12-29 2018-01-16 Monolithic 3D Inc. Semiconductor device and structure
US10115663B2 (en) 2012-12-29 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US10651054B2 (en) 2012-12-29 2020-05-12 Monolithic 3D Inc. 3D semiconductor device and structure
US10892169B2 (en) 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US10600657B2 (en) 2012-12-29 2020-03-24 Monolithic 3D Inc 3D semiconductor device and structure
US10325651B2 (en) 2013-03-11 2019-06-18 Monolithic 3D Inc. 3D semiconductor device with stacked memory
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US8994404B1 (en) 2013-03-12 2015-03-31 Monolithic 3D Inc. Semiconductor device and structure
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US10224279B2 (en) 2013-03-15 2019-03-05 Monolithic 3D Inc. Semiconductor device and structure
US9117749B1 (en) 2013-03-15 2015-08-25 Monolithic 3D Inc. Semiconductor device and structure
US11030371B2 (en) 2013-04-15 2021-06-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
US9021414B1 (en) 2013-04-15 2015-04-28 Monolithic 3D Inc. Automation for monolithic 3D devices
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US9524948B2 (en) * 2013-09-30 2016-12-20 Mediatek Inc. Package structure
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
US10297586B2 (en) 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
KR20150092881A (en) * 2014-02-06 2015-08-17 엘지이노텍 주식회사 Pcb, package substrate and a manufacturing method thereof
KR102152865B1 (en) * 2014-02-06 2020-09-07 엘지이노텍 주식회사 Printed circuits board, package substrate and a manufacturing method thereof
US20160071822A1 (en) * 2014-09-08 2016-03-10 International Business Machines Corporation OPTIMIZING POWER DISTRIBUTION FROM A POWER SOURCE THROUGH A C4 SOLDER BALL GRID INTERCONNECTED THROUGH SILICON VIAS IN INTERMEDIATE INTEGRATED CIRCUIT CHIP CONNECTED TO CIRCUITRY IN AN UPPER INTEGRATED CIRCUIT CHIP THROUGH A GRID OF MICRO uC4 SOLDER BALLS
KR102320046B1 (en) * 2014-09-19 2021-11-01 삼성전자주식회사 Semiconductor Packages Having a Cascaded Chip Stack
KR20160056379A (en) * 2014-11-10 2016-05-20 삼성전자주식회사 Chip using triple pad configuration and packaging method thereof
US10381328B2 (en) 2015-04-19 2019-08-13 Monolithic 3D Inc. Semiconductor device and structure
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
JP6515724B2 (en) * 2015-07-31 2019-05-22 富士通株式会社 Semiconductor device
US11956952B2 (en) 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
WO2017053329A1 (en) 2015-09-21 2017-03-30 Monolithic 3D Inc 3d semiconductor device and structure
US11978731B2 (en) 2015-09-21 2024-05-07 Monolithic 3D Inc. Method to produce a multi-level semiconductor memory device and structure
US10522225B1 (en) 2015-10-02 2019-12-31 Monolithic 3D Inc. Semiconductor device with non-volatile memory
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US10418369B2 (en) 2015-10-24 2019-09-17 Monolithic 3D Inc. Multi-level semiconductor memory device and structure
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11991884B1 (en) 2015-10-24 2024-05-21 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
KR102570325B1 (en) * 2016-11-16 2023-08-25 에스케이하이닉스 주식회사 Stacked type semiconductor package having redistribution line structure
KR102455427B1 (en) * 2017-12-20 2022-10-17 삼성전자주식회사 Semiconductor package and manufacturing method thereof
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11158594B2 (en) * 2019-11-12 2021-10-26 Samsung Electronics Co., Ltd. Semiconductor packages having improved reliability in bonds between connection conductors and pads
US11171121B2 (en) * 2020-03-31 2021-11-09 Micron Technology, Inc. Semiconductor devices with redistribution structures configured for switchable routing
CN112864121A (en) * 2021-01-14 2021-05-28 长鑫存储技术有限公司 Chip structure, packaging structure and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990084846A (en) * 1998-05-12 1999-12-06 김영환 Multichip Module
KR20010004562A (en) * 1999-06-29 2001-01-15 김영환 chip size stack package and method of fabricating the same
KR20050104164A (en) * 2004-04-28 2005-11-02 주식회사 하이닉스반도체 Semiconductor chip package of stack type
KR20060007530A (en) * 2004-07-20 2006-01-26 주식회사 하이닉스반도체 Chip stack package

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323060A (en) 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
US5696031A (en) 1996-11-20 1997-12-09 Micron Technology, Inc. Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US6072236A (en) * 1996-03-07 2000-06-06 Micron Technology, Inc. Micromachined chip scale package
JP4547728B2 (en) 1999-03-29 2010-09-22 ソニー株式会社 Semiconductor device and manufacturing method thereof
KR100415279B1 (en) 2001-06-26 2004-01-16 삼성전자주식회사 Chip stack package and manufacturing method thereof
KR20030018642A (en) 2001-08-30 2003-03-06 주식회사 하이닉스반도체 Stack chip module
US6611052B2 (en) 2001-11-16 2003-08-26 Micron Technology, Inc. Wafer level stackable semiconductor package
US6800930B2 (en) * 2002-07-31 2004-10-05 Micron Technology, Inc. Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies
DE10300711B4 (en) * 2003-01-10 2007-10-04 Infineon Technologies Ag Method for passivating a semiconductor chip stack
JP4419049B2 (en) 2003-04-21 2010-02-24 エルピーダメモリ株式会社 Memory module and memory system
KR100699807B1 (en) * 2006-01-26 2007-03-28 삼성전자주식회사 Stack chip and stack chip package comprising the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990084846A (en) * 1998-05-12 1999-12-06 김영환 Multichip Module
KR20010004562A (en) * 1999-06-29 2001-01-15 김영환 chip size stack package and method of fabricating the same
KR20050104164A (en) * 2004-04-28 2005-11-02 주식회사 하이닉스반도체 Semiconductor chip package of stack type
KR20060007530A (en) * 2004-07-20 2006-01-26 주식회사 하이닉스반도체 Chip stack package

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8125068B2 (en) 2008-08-22 2012-02-28 Samsung Electronics Co., Ltd. Semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack, a semiconductor device package and an electronic apparatus including the semiconductor chip
US8604616B2 (en) 2008-08-22 2013-12-10 Samsung Electronics Co., Ltd Semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack, a semiconductor device package and an electronic apparatus including the semiconductor chip
US8097940B2 (en) 2008-10-14 2012-01-17 Samsung Electronics Co., Ltd. Stack package
WO2014112758A1 (en) * 2013-01-18 2014-07-24 (주)실리콘화일 Dual-substrate stack memory
KR20140110619A (en) * 2013-03-08 2014-09-17 삼성전자주식회사 Semiconductor package
US9391048B2 (en) 2013-03-08 2016-07-12 Samsung Electronics Co., Ltd. Semiconductor package
KR102041500B1 (en) 2013-03-08 2019-11-06 삼성전자 주식회사 Semiconductor package

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