KR100698310B1 - Apparatus controlling data access and method for calling data - Google Patents

Abstract

The present invention relates to a data access control apparatus and a data call method using the apparatus. According to the present invention, when accessing data stored in a table format in a memory device in the form of a multi-embedded interface, that is, repeatedly accessing output data of the interface according to an input argument of an interface stored in a table in a table in the memory device, A data access control device capable of calculating and outputting address information of data output from a memory device with output address information of a next interface, and a data call method using the device are provided. According to the data access control device and the data call method using the device according to the present invention, the memory management device consumes fewer clocks and has a shorter time than the case of repeatedly accessing data stored in a predetermined table format in the memory device. Stored data can be accessed.

Data access, address, index

Description

Apparatus controlling data access and method for calling data}

1 is a view showing a method of accessing data using a direct addressing mode (direct addressing mode) in a conventional data access device

2 is a diagram illustrating a method of accessing data using an indirect addressing mode in a conventional data access apparatus.

3 is a diagram illustrating a method of accessing data using an immediate addressing mode in a conventional data access apparatus.

4 is a diagram illustrating a method of accessing data using a register addressing mode in a conventional data access apparatus;

5 illustrates a method of accessing data using a register indirect addressing mode in a conventional data access apparatus.

6 illustrates a method of accessing data using a relative addressing mode in a conventional data access apparatus.

7 is a structural diagram showing an embodiment of a data access control apparatus according to the present invention;

8 is a structural diagram showing an embodiment of a data address indexing apparatus according to the present invention;

9 illustrates an example of BSAC data stored in a table format in a memory device.

10A is a diagram showing the structure of a pipeline when accessing data in a conventional storage management apparatus;

10B is a view showing the structure of a pipeline when accessing data using a data access control apparatus according to the present invention;

<Description of the symbols for the main parts of the drawings>

100: address and memory space of the memory device

150: register 200: accumulator

300: memory management unit (MMU) 400: memory device

600: data access control device

620: data address indexing device

622: loop counter 625: offset selection multiplexer

627: calculator 650: mode selection multiplexer

The present invention relates to a data access control device and a data call method, and more particularly, to a data access control device and a data call method that can be accessed more quickly when data stored in a memory device needs to be repeatedly accessed in one command. It is about.

Micrporocessor (MPU) and Digital Signal Processor (DSP) show a lot of difference in performance, system complexity, programming technique for the processor, etc. The difference is due to the structural difference of the processors.

The difference in structure is that the MPU is a Reduce Instruction Set Computer (RISC) structure, while the DSP is a Complex Instruction Set Computer (CISC) structure. RISC is a processor built with at least generalization of an instruction set. RISC is often used in general controllers with priority on speed and generality or compatibility of hardware. CISC, on the other hand, has a structure that allows it to function as a complex instruction set, that is, a plurality of RISC instructions combined with one instruction. For the same reason, CISC is being replaced by RISC in many ways, but Digital Signal Processor (DSP) still adopts CISC structure. This is because DSP is used in a limited application called digital signal processing, which is less related to the generality of hardware. Since a single instruction is a powerful structure that serves several RISC instructions, the same task This can be done with a small program size.

DSP instructions access data by a memory indexing structure rather than a load-store structure, so DSPs use different addressing modes to refer to data in a memory device. Use The addressing mode is a mode for generating and referring to an address of data to be loaded or stored. The addressing mode affects the speed at which the processor accesses the operands, and also the speed at which the operands change the address of the stored storage.

Referring to the drawings, a method of accessing data by a processor using a conventional addressing mode will be described below.

In the direct addressing mode illustrated in FIG. 1, an instruction operand field means a data address. This mode is advantageous when attempting to access a small number of data because the operand of the instruction directly expresses the address of the operand and can easily and quickly perform one data access. However, when accessing data due to the above mode, only the number of bits of an operand determined in the command field can be used, so that there is no limit to the number of bits that can be used as an address in a memory device. That is, for example, in case of 16-bit instruction, if 8 bits are used as opcode, only the remaining 8 bits can be generated, and in such case, the number of addresses that can be generated is 2 ⁸ , which is 256 It means only a very small amount of memory space. In addition, if there is a change in address, such as decreasing or increasing, the programmer must write the correct address every time the change is made. Especially, the above operation is not possible in the rpeat / repeat block command among DSP instructions. Therefore, the direct addressing mode is simple, but has a significant limitation in use, which reduces the performance of the DSP.

Referring to FIG. 2, an indirect addressing mode is described below. In the indirect addressing mode, an operand does not directly indicate an address, but a value stored in a register designated by the operand indicates an address in the memory device. In FIG. 2, the data 999h stored in the address 100 hex (hereinafter, denoted as h) means an address in which valid data is stored, not valid data. Thus, address 999h is referred to again, and valid data 10E0h can be accessed at 999h. The indirect addressing mode may be free in access memory size because the range of the accessed memory is not limited by the range of the instruction operand field. It is slow to get data because its memory access is required. Therefore, if the result value of an interface according to the input value (hereinafter referred to as interface argument) of an interface such as a function or a module of a program is obtained, the final result value of a multiple-embedded interface is obtained. Thus, if the indirect addressing mode is used, the processing speed is slow and consumes a very large number of clocks.

Referring to FIG. 3, an immediate addressing mode is described as follows. Immediate address mode is a way of including data in an instruction. In other words, the operand of the instruction is not the address of the data but the data itself required to execute the instruction. This method is often used to set register values or initial values of certain variables in program execution. This method has the advantage of being fast because there is no need to perform memory access to get the data required for the operation. On the other hand, since the representation of the data used is limited by the number of bits in the command operator field, the size of the data is limited. There are many problems.

Referring to FIG. 4, the register addressing mode will be described. The register addressing mode is an access method of data in which data for executing an instruction is stored in a register inputted into an operand field of the instruction. If the data is accessed in the above mode, the data is quickly accessed because there is no data access in the memory device. On the other hand, since the data is stored in the register, the size and storage capacity of the stored data are limited by the bit size of the register.

A register indirect addressing mode will be described with reference to FIG. 5. In the case of accessing data using the above mode, the data input into the operand field indicates the address of the register, and accesses the register to access the data stored in the register. Data stored at the address of the register becomes an address in the memory device. When the data is accessed in this mode, the size that can represent the address of the data is determined according to the bit size of the register. In addition, there is a problem that the data access speed is slow.

Referring to FIG. 6, the relative addressing mode is described as follows. Relative addressing mode requires two operands. One operand is a value stored in a program counter or register, and the other operand is an offset value. When data is accessed in this mode, an offset is calculated on a value stored in a program counter or a register, and the result value is used as an address of the memory device. It is mainly used to access program memory in the next branch, jump, call, etc. instructions.

Data stored in the memory device may be stored in a predetermined table format. In particular, data stored in the memory device in a constant compression format is often stored in a table format defined by the compression format. For example, MPEG-4 Part 10 H.264 / AVC, a video compression format used for DMB transmission, MPEG-4 Part 3 BSAC, an audio compression format, and MPEG-4 BIFS format, a data compression format, are used in a memory device. It is stored in table format. In addition, data may be obtained by repeatedly indexing data in the table. To illustrate this, reference is made to an example of one of the source codes for the audio compression format BSAC of DMB as follows.

CBandModel = AModelCBand [[Cband_si_Cbook_tbl [Cband_si_type [ch]]];

The CBandModel obtains the value by successively accessing data in three tables, Cband_si_type, Cband_si_Cbook_tbl, and AModelCBand. When using this interface in any of the modes described above, the following process is required.

First, index the innermost embedded argument ch to load the result data of Cband_si_type into the accumulator. The address offset is added to Cband_si_type and stored in the accumulator again. The Cband_si_type + address offset value is stored in a memory device. The resultant data of Cband_si_Cbook_tbl is loaded into the accumulator using the stored value as an address. The offset is added to the Cband_si_Cbook_tbl and stored in the accumulator again. The Cband_si_Cbook_tbl + offset value is stored in a memory. The resultant data of AModelCBand is loaded into the accumulator using the stored value as an address. The value loaded in the accumulator is stored in the CBandModel. As long as the data goes through such a long flow to access only one data and the DSP performs this process, the size of the table increases exponentially. Therefore, when data is accessed as described above, it takes a long time to process the data, and many clock cycles are required, resulting in an inefficient problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to access data that can be accessed in a shorter time than a clock number of clocks of a processor when accessing data stored in a predetermined table format in a memory. Control unit And a data call method using the device.

Another object of the present invention is to obtain the address of a table repeatedly in order to obtain a multi-embedded interface value. It is to provide an address generator that can easily access the final interface value.

In order to achieve the above object, the present invention provides a data access control apparatus for storing or outputting data to or from a memory device by a data input / output command of a storage management device, the control method being controlled by address offset information and loop count information. A data address indexing device which receives address information of data stored in the memory device and outputs new address information; And a mode selection multiplexer for dividing and outputting one of the address information of the data to be recalled by the storage management device and the new address information output from the data address indexing device to divide the data access to the memory device. Provided is a data access control apparatus.

The data address indexing apparatus preferably includes an offset selection multiplexer for dividing and outputting a plurality of address offset information by the loop count information. The data address indexing apparatus does not directly output data output from the memory device to the storage management device, but generates a new address in the memory device using the address information of the output data.

The data output from the memory device is preferably stored in a table of a predetermined format in the memory device. An example of the table format is a table format that stores data in a compressed format such as the MPEG-4 Part 10 H.264 / AVC compressed format, the MPEG-4 Part 3 BSAC compressed format, or the MPEG-4 BIFS compressed format.

The new address information output by the data address indexing apparatus is generated by calculating address information of data output from the memory device and address offset information output by the offset selection multiplexer. Therefore, without accessing the memory device continuously and outputting the data many times, it is possible to access the data stored in the form of a table in the memory device continuously with only the address information of the data and output the last accessed data from the memory device to the storage management device. Can be.

In addition, the present invention executes a code including a multi-interface format in which a result of an interface that receives data stored in a table format in a memory device and outputs data stored in the table format in the memory device is used as input data of another interface. In the method of calling data in the multiple interface,

(a) generating a table address of argument data of multiple interfaces stored in a table format in the memory device;

(b) generating an address of the table in which result data for the input value of the interface whose data having the generated address is an input value is stored;

(c) It is determined whether the data having the address generated in step (b) is an input value of the interface to be outputted. If the result of the determination is not, repeating step (b) and If an input value, goes to step (d); And

and (d) outputting an interface value for the input value when the generated address is an address for an input value of an interface to be output as a result of the determination of step (c). To provide.

Preferably, the table address generated in step (b) is determined by calculating a predetermined address offset from the address information generated in step (a). The predetermined address offset is a base address in the table in which an interface result value is stored. More preferably, the format in which the data is stored in the table is one of an MPEG-4 Part 10 H.264 / AVC compression format, an MPEG-4 Part 3 BSAC compression format, or an MPEG-4 BIFS compression format. The present invention may be in any form, and any other form may be applied to the present invention.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described.

Referring to FIG. 7, an embodiment of a data access control apparatus according to the present invention will be described. First, for ease of explanation, it is assumed that data stored in the memory device is stored in a predetermined table format.

In an embodiment of the present invention as shown in FIG. 7, the data access control apparatus 600 includes a data address indexing apparatus 620 and a mode selection multiplexer 650. The data access control device 600 may be electrically connected to a memory management unit 300 and a memory device 400. The storage management device 300 accesses data stored in the memory device 400 using address information. The mode selection multiplexer 650 receives the access information for the data initially requested by the storage management device 300 and transmits the received access information to the memory device 400. The memory device 400 outputs data stored in the input address information. If the data requested by the storage management device 300 is the data finally requested by the storage management device 300, the data output from the memory device 400 is input to the storage management device 300. However, there is a case where data output from the memory device 400 becomes an interface input value of other data stored in the memory device 400, such as when the interface is embedded in multiple times. In this case, the data output from the memory device 400 is not output to the storage management device 300, but is input to the data address indexing device 620, and the data input to the data address indexing device 620. By using the address information, address information in the memory device 400 in which the interface result value is stored may be obtained, and the interface result value may be obtained according to the address information. Therefore, the memory management device consumes a large number of clocks and can access the data desired for output without requiring the memory device 400 to input / output data. In order to determine how many times the data address indexing device 620 should repeat the above-described process, and to obtain address information of data to be finally outputted, an address offset value is provided to the data address indexing device 620. And loop count information must be entered. The offset value and the loop count information may be set as an operand in an instruction in advance, or may be set as an already set register value, or may be calculated in a code to be executed.

The data address indexing apparatus 620 calculates an address offset value from the address information input to the apparatus, and outputs new address information. The number of times such a process is repeated is determined by loop count information. Therefore, the data address indexing apparatus 620 uses the input loop count information as to whether the data output from the memory device 400 should be sent to the storage management apparatus or whether the new address information should be output using the address of the data. Decide The data address indexing device 620 outputs the calculated address information and loop count information to the mode selection multiplexer 650. The mode select multiplexer 650 uses the input loop count information to input data access information of the storage management apparatus input to the mode select multiplexer 650 and new address information output from the data address indexing apparatus 620. The data access information for the data is divided and output to the memory device 400.

An embodiment of a data address indexing apparatus included in a data access control apparatus will be described with reference to FIG. 8.

The data address indexing apparatus 620 according to the present invention includes a loop counter 622, an offset selection multiplexer 625, and an operator 627. The data address indexing device 620 receives address offset information, and the loop counter 622 receives the initial value of the loop count and the total loop count information within the device 620, and the address of the data address indexing device 620. Whether the output process is repeated by the total number of loops is counted from the initial value and the counted value is output. Accordingly, the loop counter 622 compares the total number of loops with the counted value to determine whether the data access control device according to the present invention should repeat the looping process to output a new address or finally output the data output from the memory device. It is possible to determine whether to output to the memory management device 300. The offset selection multiplexer 625 selects and outputs an address offset value corresponding to address information of data input from among a plurality of address offset information based on the set loop count information. The operator 627 outputs new address information by calculating address information of data input to the data address indexing device 620 and an address offset value selected by the offset selection multiplexer 625. In FIG. 8, an example of expressing a new address using an adder is shown. Since the new address information may be calculated by various calculation laws, another calculator may be used.

When the new address information is output, the loop counter increments the output number once and counts the number of times. The counted number of times is output to the mode selector multiplexer 650 of FIG. 7, and the mode selector multiplexer accesses data of the storage management apparatus 300 or the data address indexing apparatus 620 according to the counted count. Split it up.

In order to describe in detail an embodiment of a data access control device and a data address indexing device according to the present invention, a process of accessing data using the same example described in the related art will be described. Data access control apparatus according to the present invention of the source code (source code) for the BSAC in the process of accessing data stored in the MPEG-4 Part 3 BSAC in the memory device

CBandModel = AModelCBand [[Cband_si_Cbook_tbl [Cband_si_type [ch]]];

In this process, the AModelCBand value is accessed to explain how the storage device obtains the CBandModel value. For ease of explanation of the present invention, the table stored in the memory device uses an example of the MPEG-4 Part 3 BSAC table in the memory device of FIG. 9. In FIG. 9, the Cband_si_type table has a base address of 1000h, the Cband_si_Cbook table has a base address of 1500h, and the AModelCBand table of 4000h. The address of the data initially output from the storage management apparatus is ch, and the value of ch will be any value in the range of 1000h of the first digit of the Cband_si_type table. Data Cband_si_type [ch] corresponding to the address is output from the memory device and input to the data access control device. In this case , a value of 2, which is the total number of loops, is input or set to the loop counter in the data address indexing apparatus. In addition, the data address offset value input to the data address indexing apparatus includes a base address of 1000h for the Cband_si_type table, a base address of 1500h for the Cband_si_Cbook_tbl table, and a base address of 4000h for the AModelCBand table. Is 1500h and offset 2 may have an offset value of 4000h. That is, the data address indexing apparatus adds an offset 1 (1500h) to the Cband_si_type [ch] in order to know the address information in which the Cband_si_Cbook value having the Cband_si_type [ch] as an input is stored. At that time, the loop count value is converted to 1 from the initial value.

The mode selection multiplexer receives address information of Cband_si_Cbook (Cband_si_type [ch]) and outputs it to the memory device.

The memory device outputs Cband_si_Cbook (Cband_si_type [ch]), and information on the output data is input to the data address indexing device. The data address indexing apparatus adds offset 2 (4000h) to Cband_si_Cbook (Cband_si_type [ch]) and outputs the offset. At that time, the loop count value is converted from 1 to 2. Therefore, since the output address is a data address in which the value of AModelCBand is stored, the value of AModelCBand can be obtained from a memory device. That is, even if the data generated during the process is not outputted to the storage management apparatus, the value of AModelCBand can be obtained if only the address information of the generated data is obtained through the operation in the data address indexing apparatus.

If the ch value is not directly output from the memory management device in the process of processing one source code, but the interface of the source code is accessed by accessing the value stored in the memory device, the address is indexed. Is repeated three times (loop count is 3), and each address offset value is set such that offset 1 is 1000h, offset 2 is 1500h, and offset 3 is 4000h.

The data access control apparatus according to the present invention can prevent the clock number of the storage management apparatus from being unnecessarily consumed. Referring to FIGS. 10A and 10, a process of reducing the number of clocks required by the memory management apparatus when using the data access control apparatus according to the present invention will be described below. Fig. 10 shows that the number of clocks of the storage management device is required in the structure of the pipeline. If the storage management apparatus accesses data in the memory apparatus in the conventional apparatus, the process as shown in FIG. 10A is performed. 10A illustrates a process of accessing and outputting one piece of data. If the interface process embedded in a single command in the program code is processed, the process of outputting one data in the memory device must go through the pipeline process of FIG. 10A. And, the pipeline process of FIG. 10A is repeated by the number of multiple embedded interfaces. Therefore, the clock consumption of the storage management device becomes large. In addition, if the data that is to be finally outputted by repeating the process as shown in FIG. 10A is updated by another instruction before the process ends, an error in data processing occurs. However, according to the present invention, even if the process of multiple embedded interfaces is processed in the program code, the data in the memory device is output to the storage management device, and there is no need to repeat the process of inputting the data to the memory device. A process of performing the data access control apparatus according to the present invention will be described in the pipe structure of FIG. 10B as follows. Fig. 10B shows that the clock number of the storage management device is required when the loop count is 3, that is, when the data addressing indexing device outputs a new data address three times in succession.

If the pipeline process shown in FIG. 10A is not repeated, the pipeline process shown in FIG. 10A can be processed on a single pipeline structure by passing through the loops 1, 2, and 3 using only the address of the output data before finally outputting the data in FIG. 10B. Accordingly, in the pipeline structure shown in FIG. 10B, the final data (data 3) can be obtained while the number of clocks of the storage management apparatus is stalled for about three cycles.

Other modifications and variations of the present invention are possible to those skilled in the art. Therefore, although the embodiments of the present invention have been described clearly as described above, changes and modifications to the above description are included within the spirit of the present invention without departing from the spirit and viewpoint of the present invention.

The effects of the data access control device and the data call method using the device according to the present invention are as follows.

First, according to the data access control device and the data call method according to the present invention, the number of clocks of the memory management device consumes less data and the data stored in the memory device in a shorter time than the case of repeatedly accessing data stored in a predetermined table format in the memory device. Can be accessed.

Secondly, according to the data access control apparatus and the data call method according to the present invention, in order to obtain the embedded interface value, the multiple data access control apparatus does not directly load the necessary data in the above process, and generates only the addresses necessary for successive interface values. Easy to access

Third, according to the data access control apparatus and the data call method according to the present invention, the data access operation on the pipeline is stopped until the final data is output by stopping the pipeline during the data access process. I will wait.

Claims (11)

A data access control device for storing or outputting data to a memory device by a data input / output command of a storage management device. A data address indexing device capable of repeatedly calculating address information and address offset information of data output from the memory device by the set loop count information and outputting new address information; And And a mode selection multiplexer for dividing and outputting one of the address information of the data to be recalled by the storage management device and the new address information output by the data address indexing device to divide the data access to the memory device. Data access control device, characterized in that. The method of claim 1, The data address indexing apparatus includes an offset selection multiplexer for dividing and outputting a plurality of address offset information by the loop count information. The method of claim 2, And the new address information is calculated by calculating address information of data output from the memory device and address offset information output by the offset selection multiplexer. The method of claim 3, And the data output from the memory device is stored in a table of a predetermined format in the memory device. The method of claim 4, wherein The table format in the memory device is the same as the table format in which the data in one of the H.264 / AVC compression format of MPEG-4 Part 10, the MPEG-4 Part 3 BSAC compression format, or the MPEG-4 BIFS compression format is stored. Data access control device, characterized in that. A device for storing data in a predetermined table format by a data input / output command of a storage management device or by generating an address index of data for causing the data to be output. An offset selection multiplexer for dividing and outputting a plurality of address offset information by loop count information; And And a calculator which receives address information of data stored in the memory device, calculates the address information and the address offset information, and outputs new address information in the table. The method of claim 6, The address information generated by the data address indexing apparatus stores data in one of an MPEG-4 Part 10 H.264 / AVC compressed format, an MPEG-4 Part 3 BSAC compressed format, and an MPEG-4 BIFS compressed format. And data indexing address information of a table. When the result of the interface for receiving data stored in the table format in the memory device and outputting the data stored in the table format in the memory device performs a code including a multiple interface format used as input data of another interface, the multiple interface In the method of calling data in, (a) generating a table address of argument data of multiple interfaces stored in a table format in the memory device; And (b) generating an address of said table in which result data for said input value of an interface whose data having said generated address is taken as an input value; (c) It is determined whether the data having the address generated in step (b) is an input value of the interface to which the output is desired. If the result of the determination is not, the step (b) is repeated. (D) step if the input value of; And and (d) outputting an interface value for the input value when the generated address is an address for an input value of an interface to be output as a result of the determination of step (c). . The method of claim 8, The table address generated in the step (b) is determined by calculating a predetermined address offset to the address information generated in the step (a). The method of claim 9, And the predetermined address offset is determined by a base address in the table in which an interface result value is stored. The method of claim 10, The table format in the memory device is the same as the table format in which data is stored in any one of the MPEG-4 Part 10 H.264 / AVC compression format, the MPEG-4 Part 3 BSAC compression format, or the MPEG-4 BIFS compression format. Data call method, characterized in that.

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