KR100665442B1 - Method and apparatus for controlling a error correction memory - Google Patents

Abstract

The present invention relates to an error correction memory control apparatus and method, comprising: partitioning an external memory used for error correction into a plurality of recording areas according to recording characteristics of the memory; Generating a memory control address corresponding to each of the allocated recording areas; And three steps of recording or reading out data for outer parity encoding in a corresponding recording area based on the generated memory control address, wherein errors of digital data recorded on a DVD, a high-density optical recording medium, are included. In consideration of the write characteristics of an external memory such as SDRAM used for correction, a memory map suitable for the write characteristics is partitioned, and data storage and read addresses corresponding to the partitioned memory map are assigned. By generating an error correction of digital data, in particular, an encoding operation for outer parity (PO), it is possible to shorten the error correction processing time by using a simple algorithm even when performing an error correction encoding operation at a high speed. It is a very useful invention that can be made.

DVD, error correction, inner parity, outer parity, memory map, address

Description

Memory control device and method for error correction {Method and apparatus for controlling a error correction memory}             

1 and 2 show a configuration of an error correction (ECC) block in a general DVD (DVD),

3 shows a configuration of an error correction encoder in a general DVD,

4 is a block diagram of an embodiment of an outer parity encoder including an error correction memory control device according to the present invention.

FIG. 5 illustrates a memory map for an SDRAM to which an error correction memory control method according to the present invention is applied.

6 shows a memory map for a main data recording area according to the present invention;

7 shows a memory map for a sector information recording area according to the present invention,

8 shows a memory map for an outer parity data recording area according to the present invention,                 

9 is a diagram illustrating an outer parit encoding sequence according to the present invention.

※ Explanation of code for main part of drawing

1: data interface unit 2: buffer unit

3: PO encoder part 4: PI encoder part

5: modulation section 6: recording encoder section

7: memory controller 8: SDRAM

31, 32, 33: address generator 34: timing controller

35: PO encoder generating unit

The present invention relates to a control apparatus and method for an error correction memory such as SDRAM (SDRAM) used for error correction of digital data recorded on a high density optical recording medium such as a DVD (Digital Versatile Disc).

In general, an error correction code (ECC) suitable for a DVD format uses a Read Solomon code (RS Code). The error correction in the DVD is RS (182, 172, 11). Interleaved with an inner code consisting of) and an outer code consisting of RS (192, 208, 17), it is possible to correct up to five errors in the inner, and eight errors and Up to 16 Erasers can be corrected, and the structure is expressed by the following equation.

--- 식 1

--- Equation 1

-- 식 2

Equation 2

On the other hand, one error correction block (ECC Block), as shown in Fig. 1, is added to the scrambled source data of 172 X 192 bytes each 16 outer parity (PO: Parity Outer) per vertical And a total of 182 X 208 byte code words, that is, code words, to which 10 inner parity inners (PI) are added per horizontal line. The code words configured as described above are illustrated in FIG. As one example, 16 outer parities have a configuration scheme interleaved to 12 inner codewords. A total of 208 inner codewords consist of 16 sectors and one sector consists of 13 inner codewords. do.

That is, one error correction block has 16 sectors, and one sector has 13 codewords. One inner codeword is 182 bytes, and the error correction operation for the error correction block constructed as described above is for implementing the above equations.

Hereinafter, a process of encoding an error correction block configured as described above will be described in detail with reference to the accompanying drawings.

FIG. 3 shows a configuration of an embodiment of an error correction encoder in a general DVD. First, when data to be encoded is transmitted to the data interface unit 1 for error correction, the buffer unit 2 starts from the necessary portion. When the data corresponding to one error correction block is stored in the SDRAM 8, the PO encoder 3 performs an encoding operation on the outer parity PO. Will be performed.

Subsequently, when the data of the next block is stored in the SDRAM 8, since the encoding for the second outer parity is repeatedly performed, the encoding operation for the outer parity is repeatedly performed as many as the number of data blocks.

After all data to be stored in the DVD is transmitted, the buffering operation of the data and the encoding operation for the outer parity are stopped. In the memory controller 7, the buffer unit 2, the P0 encoder unit 4, and After muxing the signals output from the PI encoder unit 3, the signals are output to the SDRAM 8 at a time required.

In addition, when storing data in the SDRAM (8), it is confirmed how much data is stored, and if a certain amount of data is stored, the modulator (5) and the write controller (6) read and signal the data. By outputting the data as recording data, error corrected digital data can be recorded on the DVD. On the other hand, the encoding operation in the PI encoder 3, that is, the encoding operation for the inner parity (PI), as shown in Figure 1, after sequentially reading 172 pieces of data, is added in the horizontal direction Encoding is done using inner parity.

However, as described above, the encoding operation for the outer parity PO should be encoded by reading the outer parr PO vertically added to the error correction block, as shown in FIG. When the data is stored in the SDRAM 8, which must be controlled to be stored in units of 8 to 16 codewords, that is, 16 to 32 bytes, due to the characteristics of the SDRAM, a complicated algorithm is required, and encoding processing for outer parity is also required. When a long time is required and the error correction is processed at a high speed, there is a problem that the overall processing speed for error correction is lowered.

Accordingly, the present invention was created to solve the above problems, and to quickly process the encoding operation on the outer parity (PO) during error correction of digital data recorded on a DVD (DVD), which is a high-density optical recording medium. By allocating a memory map to suit the recording characteristics of external memory such as SDRAM and generating an address so that data can be written and read according to the partitioned memory map, simple algorithm use and error correction processing time can be achieved. It is an object of the present invention to provide a memory control apparatus and method for error correction that can be shortened.

An error correction memory control method according to the present invention for achieving the above object comprises the steps of partitioning an external memory used for error correction into a plurality of recording areas according to the recording characteristics of the memory; Generating a memory control address corresponding to each of the allocated recording areas; And recording or reading processing data for outer parity encoding in a corresponding recording area based on the generated memory control address.

In addition, the error correction memory control apparatus according to the present invention comprises: storage means for partitioning into a plurality of recording areas according to the recording characteristics of the memory, for storing and storing data necessary for error correction; Address generating means for generating a memory control address for storing or reading data in the plurality of recording areas; Memory control means for storing or reading error correction data for outer parity encoding based on the generated memory control address; And encoding means for performing outer parity encoding on the read error correction data.

Hereinafter, a preferred embodiment of an error correction memory control apparatus and method according to the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 4 shows a detailed configuration of an embodiment of an error correction memory control apparatus according to the present invention, in particular the PO encoder unit 3 described above with reference to FIG. When the buffer unit 2 stores input data for one error correction block, the information is transmitted to the PO encoder unit 3, and the PO encoder unit 3 reads one error correction block data to output outer parity. In this case, as shown in FIG. 4, in the sector information address generator 31, the sector ID and ID error detection (IED) are detected. And ID, IED, RSV, and EDC data addresses for recording and storing sector information such as a reserved area (RSV: Reserved) and an error detection code (EDC), etc., are transmitted to the memory controller unit 7. And the address is S The data is transferred to the DRAM 8 to store the data in the SDRAM.

On the other hand, the timing controller 34 controls the memory controller 7 every predetermined time so that a desired address is output, while the main data address generator 32 generates an address when reading the main data, and the PO data. The address generator 33 reads 192 pieces of data and generates an address for storing a result of performing an encoding operation on outer parity.

FIG. 5 illustrates an embodiment of a memory map according to the present invention, for example, a memory map of a 64 MB SDRAM, which divides the entire SDRAM memory into four parts and stores data. First, main data to be stored in the SDRAM is stored in units of blocks, for example, 210 error correction blocks. The main data is divided into sectors again as shown in FIG. Conveniently subdivided into four parts.

That is, since the column address per row of the SDRAM 8 becomes 256, it divides one sector into four rows, and one row becomes 256 words, and eventually 512 bytes, and so on. Four rows will be 2048 bytes, allowing one sector to be stored in four rows.

In this way, when the memory area of the SDRAM is partitioned, data can be stored in the unit of a sector in a row unit when buffering the data, thereby facilitating management. The data of one sector is composed of 2048 bytes of main data, 6 bytes of ID data, 2 bytes of IED data, 6 bytes of RSV data, and 4 bytes of EDC data. As shown in the figure, the data is stored in the ID, IED, RSV, and EDC areas, that is, the sector information data area.                     

On the other hand, as shown in Fig. 7, each area stores one block of information in one row, and the information on one sector becomes an ID 2 word, an IED 1 word, an RSV 3 word, and an EDC 2 word. Since it is 8 words per sector, it is 128 words for one block.

Therefore, only half of one row is written and half is not used, and the PI data area generates and stores data in the PI encoder 3, and the outer parity (PO) data is generated 172 bytes per sector. It is possible to store two sectors of PO data in one row of SDRAM, so that one block of data can be stored in all eight rows of SDRAM, and the last MCU area can be used later when required by a microcomputer (not shown). do.

Meanwhile, the sector information address generator 31 generates an address for reading the ID, IED, RSV, and EDC data of the sector stored in the sector information area under the control of the timing controller 34. FIG. As shown in the figure, PO encoding performs error correction in the vertical direction, so that ID 0 is first read, and then data is read main data of the 18th column of the first row of the SDRAM in each sector.

Then, the next data reads the main data of the 166th column of the first row, the next data reads the main data of the 252th column of the first row, and the next data reads the main data of the 82nd column of the second row. do.

In this way, the PI encoding operation is performed by sequentially reading the addresses shown in FIG. 9, but in the same row, data can be read without pre-charging in the same row. By sequentially giving the column addresses of 166 and 252, three words of data can be read in three clocks, thereby increasing the data read speed of the SDRAM by three times or more.

On the other hand, the second reads the data of the column addresses 82,168,254 of the second row, the second reads the data of the column addresses 84,168 of the third row, and the second reads the data of the column addresses 0,86,172 of the fourth row. The data is read and the next data is read again in the second sector.

In the second sector, the ID 0 address is the same as the row address, only the column address is increased by 8 than the first sector, the address of the main data is the same as the row address, and only the column address is 1 greater than the row address of the first sector. The column address increases by one than the last row address of the first sector, and the column address outputs 80,166,252 to read three data sequentially.

Therefore, after reading the first data of one block, that is, 12 X 16 sectors in this manner, and encoding the PO, the data is stored in the address generated by the PO address generator 33. Since 16 pieces of data are output per line in the vertical direction, PO data is generated and stored for each of 16 addresses. As a result, in the sector information address generator 31, the row address of the SDRAM is increased by 1 for each block processing. As shown in FIG. 9, the ID 0 and ID 1 are different from each other by one column address. Therefore, it increases by 1, reads the second 192 vertical data in the same manner as above, encodes the PO, saves it again, and performs the PO encoding in the third to 84th directions in one block. This completes the POI encoding for the.

On the other hand, the sector information address generator 31 generates an address for the first six longitudinal directions, stops the operation, and operates again when the last two longitudinal PO encodings are performed. PO encoding is performed by reading the last EDC data.

In the main data address generator 32, the row address is incremented by 1 for each SDRAM read period, and the column address is output as shown in FIG.

After reading 192 pieces of data and performing PO encoding, the row address becomes the head value of the block, and is incremented by one each time the column address is changed. In this way, we end up with 86 vertical PO encodings. In the PO address generator 33, an address generator for storing PO data generated by reading 192 pieces of data vertically, the row address is incremented by one each time two words of data are written, and the column address is an odd sector. In E, it starts with 0 and ends 192 PO encodings in the longitudinal direction, and increases by 1, and in even sectors, it starts with 80 (Hexa) and ends with 192 PO encodings in the longitudinal direction and increases by 1.

As shown in Fig. 9, the timing controller 34 outputs the output of the main data address generator 32 to the SDRAM 8 when reading ID, IED, RSV, and EDC data, and other main data. When reading the data, the output of the main data address generator 32 is output to the SDRAM.                     

After the PO encoding for 192 vertical data ends, the PO data is stored by the address output from the PO data address generator 33, and the PO encoder generator 36 reads data from the SDRAM. After performing PO encoding, 192 pieces of data are output to the modulator 5.

Therefore, PO encoding is not a problem when the encoding operation is operated at a low speed, but when the encoding operation is operated at a high speed, the time required for PO encoding limits the entire encoding time. By largely allocating the memory area into four areas and storing and reading data appropriately, the PO data can be read and encoded quickly by about three times, thereby enabling error correction at high speed.

As mentioned above, preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art can improve and change various other embodiments within the spirit and technical scope of the present invention disclosed in the appended claims below. , Replacement or addition would be possible.

An error correction memory control apparatus and method according to the present invention constituted and constructed as described above may include an external memory such as an SDRAM used for error correction of digital data recorded on a DVD, a high-density optical recording medium. In consideration of the recording characteristics, a memory map suitable for the recording characteristics is partitioned, and data storage and reading addresses corresponding to the partitioned memory maps are generated to correct errors of digital data, in particular, outer parity (PO). It is a very useful invention that it is possible to shorten the error correction processing time by using a simple algorithm even when performing the error correction encoding operation at a high speed by allowing the encoding operation to be processed quickly.

Claims (10)

Partitioning the external memory used for error correction into a plurality of recording areas according to the recording characteristics of the memory; Generating a memory control address corresponding to each of the allocated recording areas; And And recording or reading processing data for outer parity encoding in a corresponding recording area based on the generated memory control address. The method of claim 1, And the external memory is SDRAM. The method of claim 1, The plurality of recording areas may include a first recording area in which main data for error correction is recorded, a second recording area in which information about a sector of the main data is recorded, and an outer parity data in which error correction is recorded. And a recording area comprising at least three recording areas. The method of claim 3, wherein And a fourth recording area in which the control data for the optical recording medium on which the error corrected data is to be recorded is recorded in the plurality of recording areas. The method of claim 3, wherein And the memory control address is generated at predetermined intervals to record or read data in the first recording area, the second recording area, and the third recording area. Storage means partitioned into a plurality of recording areas according to recording characteristics of the memory, for storing and storing data necessary for error correction; Address generating means for generating a memory control address for storing or reading data in the plurality of recording areas; Memory control means for storing or reading error correction data for outer parity encoding based on the generated memory control address; And And encoding means for performing outer parity encoding on the read error correction data. The method of claim 6, The storage means includes a first recording area in which main data for error correction is recorded, a second recording area in which information about a sector of the main data is recorded, and a third recording in which outer parity data for error correction is recorded. An error correction memory control device, characterized in that the area includes at least an SDRAM. The method of claim 7, wherein The address generating means, A first address generator for generating an address for recording or reading main data in the first recording area; A second address generator for generating an address for recording or reading information about a sector in the second recording area; A third address generator for generating an address for recording or reading outer parity data in the third recording area; And And a memory controller for generating an address for writing or reading data to the storage means based on the respective addresses generated by the first, second and third address generators. Correction memory controller. The method of claim 7, wherein In the second recording area, information on sector ID (ID), ID error detection (IED), free area (RSV), and error detection code (EDC) of the recorded data is recorded. Control unit. The method of claim 7, wherein And the outer parity data is recorded and stored by 16 sectors in the third recording area.

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