KR100661519B1 - A processor apparatus having a function of restoring buffer mismatch between the core processor and the communication processor and the method thereof - Google Patents

Abstract

A processor system having a buffer descriptor mismatch recovery function for a core processor and a CPM(Communication Processor Module) and a method thereof are provided to prevent a fault from being generated in a communication system by making a receiving-side processor compare its own buffer descriptor pointer with the other side's buffer descriptor pointer in case that a buffer descriptor mismatch state occurs, recover the mismatch, and exactly read target Tx data stored in a buffer. A processor system(10) having a buffer descriptor mismatch recovery function comprises a core processor(11), a CPM(12), a buffer(13), and a BD(Buffer Descriptor)(14). The core processor(11) executes data operation processing according OS(Operating System) codes. The CPM(12) executes data communication with the external according to a communication protocol. The buffer(13) stores the data transmitted and received between the core processor(11) and the CPM(12). The BD(14) stores information for target Tx/Rx data, stored in the buffer(13).

Description

A processor apparatus having a function of restoring buffer mismatch between the core processor and the communication processor and the method approximate

1 is a block diagram of a conventional base station controller (BSC),

2 is a block diagram of a processor device,

FIG. 3 is a diagram illustrating a structure of a buffer descriptor of the processor device of FIG. 2.

4 is a flowchart illustrating a detailed process of a method of recovering a buffer descriptor mismatch between a core processor and a communication processor of the processor device of the present invention.

Description of the main symbols in the drawings

1: Base Station Controller (BSC)

2: ATM Low Speed Subsystem Block (ALSB)

3: ATM Switch Module Block (ASMB)

4: Call Control & No.7 Signaling Block (CCSB)

5: Selector Block (SLB)

6: Vocoder Block (VCB)

10: processor unit

11: Core Processor

12: Communication Processor Module (CPM)

13: Buffer

14: Buffer Descriptor (BD)

14a-14n... : Buffer Descriptor Field

14a '~ 14n' ....: empty bit

* Base Station Transceiver Subsystem (abbreviated as "Base Station") (BTS: Base Station Transceiver Subsystem)

* Base Switching Center (MSC: Mobile Switching Center)

The present invention relates to a processor of a communication system, and more particularly, a processor having a buffer descriptor mismatch recovery function of a communication processor (CPM) and a core processor (Core). An apparatus and a method thereof are provided.

FIG. 1 is a block diagram of a base station controller (BSC) of the related art, and FIG. 2 is a block diagram of a processor device in which a core processor and a communication processor are separated among the processors of the above-described communication system. .

As shown in FIG. 1, a base station controller (BSC) 1 as an example of a communication system includes an ATM switch module block (ASMB) 3 and a base station transceiver (BTS). an ATM Low Speed Subsystem Block (ALSB) 2 for performing multiplexing and muxing / demuxing on ATM cells inputted through relay lines between subsystems; ATM Switch Module Block (ASMB), which performs the ATM switching function to transfer all traffic and control data in the form of ATM cells to the destination. )and; A call and signal block (CCSB) (4) which performs a call processing control function, a resource management function, and the like; A selecting block (SLB) 5 for performing a soft handoff (Soft H / O) function and radio link protocol termination; It includes a Vocoder Block (VCB) 6 that performs communication with a Mobile Switching Center (MSC) by encoding / decoding voice data into PCM data. It is configured by.

The base station controller (BSC) of FIG. 1 is an example of transmitting and receiving data using an ATM protocol, and converting an AAL frame into an STM-1 signal in another processor device. Transmit the STM-1 signal received from the other building blocks to the AAL frame using ATM communication protocol, extract the data, perform the signal processing, and then convert the STM-1 signal to another building block again. To transmit to the network.

In a general communication system such as the BSC 1 described above, each of the building blocks 2 to 6 includes a processor device for data processing for each unique function and data communication with an external function block.

To this end, a processor device used in each component block of the communication system as described above is a host processor (hereinafter referred to as a "core processor (Core)) which reads an operating system code and performs arithmetic processing. It is configured to perform a "Communication Processor Module" (hereinafter referred to as "CPM") function that is responsible for communication by using the "") function and external and various protocols. The core processor function and the communication processor function may be configured as one processor or may be separately configured as a core processor and a communication processor.

Motorola's MPC8260, for example, has a core processor and a communication processor (CPM) in one processor. However, the MPC750 has only a core processor and uses a communication processor (CPM) suitable for various communication protocols externally.

FIG. 2 is a diagram illustrating a configuration of a processor device 10 in which a communication processor function and a core processor function are separated as described above. In this case, the core of the MPC8260 is disabled to disable the communication processor (CPM). For example, the MPC750 can be used externally, and the core can be used externally.

As shown in FIG. 2, a processor device 10 having a core processor and a communication processor function separated from each other may include a core processor 11 that performs arithmetic operations on data by an operating system code. ; A communication processor (CPM) 12 for performing data communication by a communication protocol for communication with the outside; A buffer 13 for storing transmission and reception data between the core processor 11 and the communication processor 12; And a buffer descriptor (BD) 14 for storing information on the data to be transmitted / received stored in the buffer 13.

The buffer 13 stores data to be actually sent and received. In the buffer descriptor 14, information about the data stored in the buffer 13 and data storage position information of the buffer 13 are recorded.

3 is a diagram showing the structure of the above-described buffer descriptor (BD) 14, and as shown in FIG. 3, the buffer descriptor (BD) 14 is a buffer descriptor pointer corresponding buffer descriptor field 14a to 14n. ....), and each of the buffer descriptor fields 14a to 14n ... has an empty bit (14a 'to 14n' ....) indicating whether the buffer descriptor field is recorded or empty and the buffer recording. A data field in which information such as size information, a CRC, a rap bit, and a pointer of data is recorded is recorded. At this time, if the empty bit is '0', it indicates a recorded state, and if it is '1', it indicates an empty state.

In the position of reading data from the structure of the buffer descriptor field described above, if the empty bit is '0', the buffer corresponding to the fields 14a to 14n ... of the corresponding buffer descriptor BD ( buffer (13) indicates that data has been read in the storage location, and if the empty bit is set to '1', the fields of the corresponding buffer descriptor (BD) (14a to 14n ...) Indicates that there is no data read in the storage location of the buffer 13 corresponding to the.

In the entry to the buffer (transmission side), if the empty bit is '0', the buffer 13 corresponding to the fields 14a to 14n ... of the corresponding buffer descriptor BD may be used. ) Means that the data cannot be recorded because the data is recorded at the position of), and if the empty bit is set to '1', it corresponds to the corresponding buffer descriptor (BD) field (14a to 14n ...). Indicates that data can be written to the storage location of the buffer 13 to be stored.

Accordingly, the counterpart processor can read the data correctly from the buffer 13 when looking at the buffer descriptor 14.

That is, in the processor device in which the communication processor and the core processor are separately configured as described above, the core processor 11 and the communication processor 12 store the buffer write information in the buffer 13 when the transfer target data is stored in the buffer 13 (BD). ) And then outputs an interrupt signal to the other party. When the other party receives the interrupt signal, the other party reads the data written in the buffer by using the buffer descriptor pointer. That is, as shown in FIG. 2, the core processor 11 and the communication processor CPM 12 are organic to each other with a buffer 13 and a buffer descriptor (BD) 14 therebetween. To operate.

At this time, the storage position of the buffer write information of the buffer descriptor BD is identified by the buffer descriptor pointer which is controlled independently by the promised control of the core processor 11 and the communication processor 12 and coincides with each other.

Referring to FIGS. 1 and 3, a process of transmitting and receiving data between the core processor 11 and the communication processor 12 in the above-described processor device 10 is as follows.

First, assuming that the core processor transmits data, since FIG. 1 illustrates a case of transmitting and receiving data by an ATM cell, a frame generated by the core processor 11 may be an AAL frame ( frame is converted and then the converted AAL frame is stored in the buffer 13. Then, the empty bit is written as '0' in the corresponding buffer descriptor fields 14a to 14n ... of the buffer descriptor (BD) 14, and the buffer 13 write data information is recorded, and then the communication processor Send an interrupt signal to (12). The communication processor (CPM) 12 then looks at the empty bit of the buffer descriptor (BD) 14, and if the empty bit is '0', the buffer descriptor field 14a-14n. After reading the information recorded in ..), it reads the frame to be transmitted from the storage location of the buffer 13, converts it into ATM cell, converts it into STM-1 signal, and converts it into OSI. It is transmitted to the processor device of another component block through the physical layer of the seventh layer.

In the case of receiving data from the core processor, the above-described processing is performed in reverse, and ATM data received through the physical layer of the OSI 7 layer is communicated with the processor device 10. The APM frame is converted by the processor (CPM) 12. The converted data is stored in the buffer's predetermined storage location, the contents are written in the buffer scripter (BD) 14, and finally the empty bit is set to '0'. Record it. In addition, an interrupt signal is output to the core processor Core 11. The core processor (Core) 11 that detects the interrupt signal sees an empty bit in the interrupt target buffer descriptor fields 14a to 14n .... of the buffer descriptor (BD) 14 and '0'. After reading the remaining information in the buffer descriptor (BD) fields (14a to 14n ...), AAL frames are read from the storage location of the buffer (13) where the actual data is stored. Do this.

However, as described above, when the core processor and the communication processor are separately configured to transmit and receive data by the buffer and the buffer descriptor, the data transfer side processor writes the data to the buffer 13 and then buffers the data. Send an interrupt signal to the receiving processor without writing the empty bits 14a 'to 14n' ... of the descriptor (BD) 14 as '0', or buffer of the buffer descriptor (BD). If one skips one of the descriptor fields (14a to 14n ....), writes data to the next buffer descriptor field, and outputs an interrupt signal to the receiving processor, the buffer descriptor pointer of the sending processor. And a buffer descriptor mismatch phenomenon, in which a buffer descriptor pointer (BD pointer) of a receiving side processor is mismatched.

If the above-described buffer descriptor mismatch occurs, the empty bit becomes '1' when the receiving processor sees the corresponding buffer descriptor fields 14a to 14n ... of the buffer descriptor BD. Therefore, it is determined that there is no data to be read from the buffer 13, and thus the transfer target data data recorded in the buffer 13 cannot be read. When the situation described above occurs, even if other data comes next, the receiving processor stops forever without recovering.

Accordingly, the present invention is to solve the above-described problems of the prior art, in the processor device configured to separate the core processor and the communication processor, when a buffer descriptor mismatch occurs, a transmission-side buffer descriptor pointer (Buffer Descriptor Pointer) If the buffer descriptor pointer is the same, the interrupt signal wait state is reached. If the buffer descriptor pointer is inconsistent, the buffer descriptor pointer is buffered. Increasing the value by 1 and increasing the buffer descriptor mismatch ((Buffer Descriptor Mismatch) when the sender reads all the data stored in the buffer and enters the interrupt wait state. Buffer It is an object of the present invention to provide a processor device having a core descriptor and a buffer descriptor mismatch recovery function of a communication processor capable of recovering a situation, and a method thereof.

A processor device having a buffer descriptor miss match recovery function of a core processor and a communication processor of the present invention for achieving the above object includes a core processor for performing data operation processing by the operating system code; A communication processor for performing data communication with an external communication protocol; A buffer in which the core processor and the communication processor record and read transmission data to be transmitted to a counterpart processor; The core processor and the communication processor is configured to include a buffer descriptor (Buffer Descriptor) for recording the transmission target data information, the core processor and the communication processor is a processor that is the receiving side when a buffer descriptor mismatch situation occurs And a buffer descriptor mismatch recovery function operable to read data after recovering a buffer descriptor mismatch situation by comparing the buffer descriptor pointer with its buffer descriptor pointer.

The buffer descriptor mismatch recovery function may include a buffer descriptor pointer of a transmitting processor when a buffer descriptor mismatch for buffer stored data occurs. If it matches and compares its own Buffer Descriptor Pointer, if it is matched, it will be interrupted. If it does not match, it will increase its Buffer Descriptor Pointer and correspond to the Buffer Descriptor allocated for data recording. After the input, when the empty bit is in a state where data is not written, an interrupt wait state is provided.

A buffer descriptor miss match recovery method of a processor device having a core processor and a communication processor of the present invention for achieving the above object is a processor device in which a core processor and a communication processor are separated, and receives an interrupt signal of a counterpart processor. A first empty bit determining step of a receiving processor checking an empty bit of a buffer descriptor pointer (Buffer Descriptor Point) target buffer descriptor field; If the empty bit of the first empty bit determination process is in the write state, the data is read and the processing is terminated. If the empty bit is in the unrecorded state, the buffer descriptor pointer of the counterpart processor is compared with its buffer descriptor pointer. If the process is terminated, and if there is a mismatch, the buffer descriptor mismatch recovery process of recovering the buffer descriptor mismatch situation and reading data by sequentially increasing the buffer descriptor pointers thereof; It features.

The buffer descriptor field is set to indicate a recorded state when the empty bit is '0', and an empty state when the empty bit is '1', and the buffer 13 recorded in the buffer descriptor fields 14a to 14n .... For information on the recording data, information such as size, CRC, rap bit, and pointer of the buffer recording data is recorded.

The buffer descriptor mismatch recovery process is a buffer that compares a buffer descriptor pointer of a counterpart processor with a buffer descriptor pointer of its own (receive side processor) when an empty bit is unrecorded as a result of the determination of the first empty bit determination process. A descriptor pointer comparison process; As a result of the comparison of the buffer descriptor pointers, if the buffer descriptor pointers are matched, the process is interrupted and the process ends. If the buffer descriptor pointers do not match, the target buffer descriptor field is increased by one (1). A second empty bit determining step of determining whether an empty bit of the recording state is a recorded state or an unrecorded state; As a result of the determination of the second empty bit determination process, when the empty bit is in the unrecorded state, the empty bit enters the interrupt wait state and terminates the processing. And a buffer read process for returning to the second empty bit determination process.

The buffer reading process includes: a data reading process of reading stored data of a buffer corresponding to the buffer descriptor field when an empty bit of the buffer descriptor field is in a write state; And an empty bit initialization process of setting an empty bit of the data information corresponding buffer descriptor field to an unrecorded after the data reading process and then moving to the second empty bit determining process.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

The structures of the processor device and the buffer descriptor of the present invention have the same configuration as those of FIGS. 2 and 3 except for the functions. Accordingly, the processor device of the present invention will be described with reference to FIGS. 2 and 3 as follows.

As shown in FIG. 2, the processor device 10 of the present invention includes a core processor 11; A communication processor 12 which performs data transmission and reception with the core processor 11 by an interrupt signal; A buffer 13 for temporarily storing data transmitted and received between the core processor 11 and the communication processor 12; The core processor 12 and the communication processor 14 record information on the data stored in the buffer 13 and are read by the core processor 11 or the communication processor 12 by the buffer descriptor pointer, and the counterpart is read. And a buffer descriptor 14 that allows the processor to read data written in the buffer 13 from the buffer 13.

As shown in FIG. 3, the buffer descriptor 14 includes at least one buffer descriptor field 14a to 14n... And a buffer descriptor field 14a to 14n. Each field has an empty bit for indicating the recording state of data and an area for storing data information recorded in the buffer, so that the core processor 11 and the communication processor 12 use the buffer descriptor pointer. In this way, data to be transmitted to the counterpart processor is recorded in the buffer 13, and data transmitted from the counterpart processor can be read from the buffer 13. In this case, when the empty bit is '0', the recorded state is displayed. If the empty bit is '1', the empty state is displayed. The information on the buffer 13 recorded data recorded in the buffer descriptor fields 14a to 14n. As described above, the size information, the CRC, the rap bit, and the pointer of the buffer write data are recorded. The buffer descriptor pointer is maintained such that the core processor and the communication processor have the same value by a preset counter.

Referring to Figures 2 and 3 will be described in more detail for each configuration of the above-described processor device 10 of the present invention.

The core processor 11 performs data operation by an operating system code. And when a buffer descriptor mismatch occurs in which a buffer descriptor pointer of a core processor and a communication processor are inconsistent when data is transmitted through the buffer 13 and the buffer descriptor 14 from the communication processor 12. Compare the buffer descriptor pointer of the processor 12 with the buffer descriptor pointer of the processor 12 to recover the buffer descriptor mismatch, and then read the data from the buffer 13. And a buffer descriptor mismatch recovery function.

The communication processor also has a buffer descriptor miss match recovery function that performs buffer descriptor mismatch recovery by the same method.

The communication processor module (CPM) 12 performs data communication using a communication protocol for communication with the outside. The communication processor (CPM) may also detect the occurrence of a buffer descriptor mismatch in the data transmission via the buffer 13 and the buffer descriptor 14 from the core processor 11. Buffer descriptor mismatch, which reads data from the buffer 13 by restoring the Buffer Descriptor Mismatch by comparing the Buffer Descriptor Pointer and its own Buffer Descriptor Pointer. It is characterized by having a recovery function.

The core processor 11 and the communication processor 12 record the target data in the buffer 13 and the information on the target data in the buffer descriptor 14 when the data to be transmitted to the counterpart processor is generated, and then interrupt the signal to the counterpart processor. By notifying that the data to be transmitted is stored in the buffer 13. The processor on the other side (processor to read the buffer 13 stored data) reads the information of the buffer descriptor 14 using a predetermined buffer descriptor pointer when an interrupt signal is generated, and then stores the buffer 13 information. Read

The core processor 11 and the communication processor 12 performing the operation as described above store the data to be transmitted to the counterpart processor in the buffer 13 in the buffer 13 and then the empty buffer target field corresponding to the buffer descriptor pointer. When outputting an interrupt signal to the other processor without setting the bit to be written (Ah write is set to '0' and Unrecorded is set to '1'), or the buffer buffer pointer target buffer descriptor field is skipped. Then, when the buffer 13 write data information is recorded in the buffer descriptor field and the interrupt signal is output to the partner processor, a buffer descriptor mismatch situation occurs in which the partner processor cannot read the write data of the buffer 13.

At this time, a processor operating as a receiving processor among the core processor 11 and the communication processor 12 of the processor device receives buffer descriptor pointer information of the transmitting processor from the transmitting processor and receives the buffer descriptor pointer of the transmitting processor. Compares its buffer descriptor pointers.

In the situation where the buffer descriptor pointers match, the empty bit in the corresponding buffer descriptor field is set to '1'. At this time, it is determined that data writing has not normally occurred, and the process ends.

If the empty bit of the buffer descriptor field corresponding to its buffer descriptor pointer is set to '0' when the buffer descriptor pointer does not match as a result of the comparison, the address of the buffer 13 having the corresponding buffer descriptor field information is stored. After reading the recorded data, set the empty bit in the corresponding buffer descriptor field to '1', and then increase the buffer descriptor pointer by one. When the empty bit of the buffer descriptor corresponding to the increased buffer descriptor pointer is '0', the process of reading data, setting empty bit '1', and increasing the buffer descriptor point 1 is repeated as described above. If the value is '1', the process terminates the process to recover the corresponding buffer descriptor mismatch and read the data to be received. In this case, the receiving processor increases the buffer descriptor pointer by 1 in the buffer descriptor mismatch situation because the buffer descriptor pointer of the receiving processor is always smaller than the buffer descriptor pointer value of the transmitting processor in the buffer descriptor mismatch situation.

4 is a flowchart illustrating a detailed process of a buffer descriptor miss match recovery method of a processor device including a core processor and a communication processor of the present invention having the above-described process.

Processing of a buffer descriptor miss match recovery method of a processor having a core processor and a communication processor of the present invention with reference to FIGS. 2 to 4 as a processor device configured in the BSC transmitting data by an ATM cell according to the present invention. The process is as follows.

First, when the core processor 11 or the communication processor 12 generates data to be transmitted to the counterpart processor (in this case, the processor that writes the data to the buffer 13 is called the "transmitter processor", and the processor that reads the "receiver" is received). Side processor " (S1), the transfer side processor writes the target data into the buffer 13 (S2).

Since the transmission target data generated in the above-described process is assumed to be an example of transmitting and receiving data by an ATM cell, the transmission target data becomes an AAL frame.

Thereafter, the empty bits of the corresponding buffer descriptor fields 14a to 14n .... of the target buffer descriptor 14 are set to '0' with reference to the buffer descriptor pointer, and the buffer 13 is recorded. Record the data information. In this case, when the empty bit is '0', the recorded state is displayed. If the empty bit is '1', the empty state is displayed. The information on the buffer 13 recorded data recorded in the buffer descriptor fields 14a to 14n. As described above, the size information, the CRC, the rap bit, and the pointer of the buffer write data are recorded (S3).

When the recording of the buffer 13 for the transmission target data and the recording of the buffer descriptor fields 14a to 14n .... of the transmission data are finished by the S3 process, the transmitting processor sends an interrupt signal to the receiving processor. Outputs (S4).

After receiving the interrupt signal by the S4 process, the receiving processor reads an empty bit of the buffer descriptor fields 14a to 14n ... corresponding to the predetermined buffer descriptor pointer (S5). It is determined whether the read empty bit is '0' or '1' (S6).

If the empty bit is written as '0' as a result of the determination in S6, after reading the information recorded in the buffer descriptor pointer corresponding buffer descriptor fields 14a to 14n .... (S7), the corresponding buffer (buffer) is read. (13) A transmission target frame is read out from (13).

After the buffer 13 record information of the buffer descriptor field 14a to 14n .... corresponding position is read by the process S8, the empty bit of the corresponding buffer descriptor field 14a to 14n. After setting to go to step S13 (S8).

Thereafter, the receiving processor increases the buffer descriptor pointer by 1 and determines whether the empty bits of the increased buffer descriptor corresponding buffer descriptor fields 14a to 14n ... are '0' (second empty bit determination process). (S13).

If the empty bit is '0' as a result of the determination in step S13, the process proceeds to step S7 to repeat the process to read all the write data of the buffer descriptor field correspondence buffer 13 in which the empty bit is set to '0'. The empty bits in the buffer descriptor fields 14a to 14n ... are set to '1'.

In contrast, when the empty bit is '1' as a result of the determination of S13, the process enters the interrupt standby state and ends the process (S14).

The above-described processing becomes the processing of the present invention in the case where a buffer descriptor mismatch situation does not occur.

Next, when a buffer descriptor mismatch situation occurs and the empty bit is not '0' as a result of the determination in step S6, the process moves to step S10 to read the buffer descriptor pointer of the transmitting processor (S10).

Thereafter, the receiving processor determines whether the transmitting descriptor descriptor read in S10 and the buffer descriptor pointer of its own (receiving processor) match, and if so, the process moves to S14 to enter the interrupt wait state, and then proceeds with processing. It ends (S11).

On the contrary, when the determination result of step S11 is that the sender descriptor descriptor read in step S10 does not coincide with the buffer descriptor pointer of the self (receive processor), the receiver processor increments its own buffer descriptor pointer by one (S12). .

Thereafter, the receiving processor determines whether an empty bit of the increased buffer descriptor pointer corresponding buffer descriptor fields 14a to 14n .... is recorded as '0' (S13).

If the empty bit is '0' as a result of the determination in step S13, the process proceeds to step S7 to repeat the process to read the write data of the buffer descriptor field corresponding buffer 13 in which the empty bit is set to '0' By sequentially setting the empty bits in the descriptor fields 14a to 14n ... to '1', the buffer stored data is read while the buffer descriptor mismatch is restored.

In contrast, when the empty bit is '1' as a result of the determination of S13, the process enters the interrupt wait state and ends the process (S14).

As described above, according to the present invention, when a buffer descriptor mismatch situation occurs in a processor device in which the core processor 11 and the communication processor 12 are separately configured, the receiving processor compares a buffer descriptor pointer with its own buffer descriptor pointer and a buffer. By recovering the mismatch of the descriptor pointer and at the same time, it is possible to accurately read the transmission target data ("reception target data" from the transmission processor side and the reception processor side) recorded in the buffer 13. Provides the effect of preventing it.

Claims (5)

A core processor performing data operation processing by an operating system code; A communication processor for performing data communication with an external communication protocol; A buffer in which the core processor and the communication processor record and read transmission data to be transmitted to a counterpart processor; And a buffer descriptor in which the core processor and the communication processor record the transmission target data information. The core processor and the communication processor are configured to read data after recovering the buffer descriptor mismatch situation by comparing the buffer descriptor pointer of the counterpart processor with the buffer descriptor pointer of the counterpart processor when the buffer descriptor mismatch situation occurs. And a buffer descriptor miss match recovery function of a core processor and a communication processor. The method of claim 1, wherein the buffer descriptor miss match recovery function When a buffer descriptor mismatch occurs for the buffer stored data, the core processor and the receiving processor among the communication processors may use a buffer descriptor pointer and a buffer descriptor pointer of the transmitting processor. If Descriptor Pointer is compared and it is interrupted, it becomes interrupt waiting state.If it is not matched, its descriptor pointer is increased so that stored data of buffer descriptor corresponding buffer is read sequentially until empty bit is unwritten. And a processor descriptor match recovery function of a core processor and a communication processor. A processor device in which a core processor and a communication processor are separately configured, A first empty bit determining step of receiving, by the receiving processor, the receiving processor's interrupt signal, an empty bit of a buffer descriptor pointer target buffer descriptor field; If the empty bit of the first empty bit determination process is in the write state, the data is read and the processing is terminated. If the empty bit is in the unrecorded state, the buffer descriptor pointer of the counterpart processor is compared with its buffer descriptor pointer. If the process is terminated, and if there is a mismatch, the buffer descriptor mismatch recovery process of recovering the buffer descriptor mismatch situation and reading data by sequentially increasing the buffer descriptor pointers thereof; Characterized in that a buffer descriptor mismatch recovery method of a processor device having a core processor and a communication processor. The method of claim 3, wherein the buffer descriptor mismatch recovery process is performed. A buffer descriptor pointer comparing step of comparing a buffer descriptor pointer of a counterpart processor with a buffer descriptor pointer of a self (receiving processor) when an empty bit is in an unrecorded state as a result of the determination of the first empty bit determination process; As a result of the comparison of the buffer descriptor pointer comparison process, if the buffer descriptor is matched, the process is interrupted and the process is terminated. If there is a mismatch, the buffer descriptor pointer of the own (receiving processor) is increased by 1, A second empty bit determining step of determining whether the empty bit is in a recorded state or an unrecorded state; As a result of the determination of the second empty bit determination process, when the empty bit is in the unrecorded state, the empty bit enters the interrupt wait state and terminates the processing. And a buffer reading process of returning to the second empty bit determination process after the buffer descriptor mismatch recovery method of the processor device having a core processor and a communication processor. The method of claim 4, wherein the reading of the buffer comprises: A data reading process of reading stored data of the buffer corresponding to the buffer descriptor field when the empty bit of the buffer descriptor field is in a write state; And an empty bit initialization process of setting an empty bit of the data information corresponding buffer descriptor field to an unrecorded after the data reading process and moving to the second empty bit determining process. A method of recovering a buffer descriptor miss match for a processor device having a processor and a communication processor.

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