KR100659181B1 - Demodulator for demodulating amplitude shift keying-radio frequency signal and reader system having the same - Google Patents

Abstract

An ASK RF demodulator and a reader system comprising the same are provided to clip an ASK RF signal received from an RF tag with a desired signal range, by using a demodulator comprising a clipping circuit implemented with a PMOS transistor. A control voltage generator(110) generates a control voltage in response to an N bit control signal. A clipping circuit(120) generates a clipped signal by clipping an ASK RF(Amplitude Shift Keying Radio Frequency) signal based on the control voltage. A DC remover(130) receives the clipped signal, and removes a DC signal included in the received clipped signal, and generates a signal without a DC signal. A low pass filter block(140) performs low pass filtering by receiving the signal without the DC signal. A variable gain amplifier(150) amplifies an output signal of the low pass filter block on the basis of a gain control signal. A comparator(160) generates a digital modulation signal by comparing an output signal of the variable gain amplifier with a first reference voltage.

Description

ASVR RF signal demodulator and reader system having same {demodulator for demodulating amplitude shift keying-radio frequency signal and reader system having the same}

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a functional block diagram of a demodulator according to an embodiment of the present invention.

2 is a graph illustrating a waveform in which an ASK RF signal is clipped according to an embodiment of the present invention.

3 is a functional block diagram of a reader system according to an embodiment of the present invention.

4 is a functional block diagram illustrating a receiver of a reader system according to an embodiment of the present invention.

5 is a functional block diagram illustrating a digital block of a reader system according to an embodiment of the present invention.

The present invention relates to an ASK RF (Amplitude Shift Keying Radio Frequency) signal demodulation technique, and more particularly, to an ASK RF signal demodulator capable of demodulating the ASK RF signal output from an RF tag and the ASK RF signal demodulator It is about a reader system.

In general, RFID (radio frequency identification) system can be divided into an inductively coupled method and an electromagnetic wave method according to a wireless access method. The mutual induction method is used in a short range (within 1m) RFID system, the wireless communication between the reader and the RF tag using a coil antenna.

The mutually induced RF tag is operated almost manually. That is, all the energy required for the operation of the IC chip of the RF tag is supplied by a reader. Therefore, the antenna coil of the reader generates a strong magnetic field in the surrounding area.

A part of the magnetic field emitted from the antenna coil generates an inductive voltage in the coil antenna of the RF tag away from the reader, and the generated inductive voltage is rectified and then supplied as energy for the IC chip.

The electromagnetic wave method is used in a medium and long distance RFID system, and the reader and the RF tag wirelessly communicate using a high frequency antenna.

Since the electromagnetic wave RF tag does not receive sufficient power from the reader to drive the IC chip, there is also an RF tag (eg, active) including an additional battery for long range recognition.

Each of the reader and the RF tag processes baseband data using various digital coding schemes. Electromagnetic waves generated by the reader are mainly converted into a high frequency signal and transmitted based on three basic digital modulation schemes: ASK (Amplitude Shift Keying), FSK (Frequency Shift Keying), or PSK (Phase Shift Keying).

In particular, the ASK modulation method is a modulation method that changes amplitude only by leaving a phase of a sinusoidal carrier or frequency in correspondence with a binary digital code, and is widely used in an RF reader system due to its simple circuit implementation and low cost.

The ASK signal by the ASK modulation method is a high frequency signal and distinguishes between '1' and '0' of the digital signal through a large amplitude and a small amplitude. Typically, the ASK modulation method is used ASK 100 and ASK 10, the ASK 100 means a level difference of 100%, the ASK 10 means a level difference of 10%.

The ASK RF signal output from the RF tag is clipped and demodulated into a predetermined signal by a demodulator or an envelope detector. Typically, the demodulator clips the ASK RF signal through a diode to demodulate the information of the RF tag based on the clipped ASK RF signal.

When clipping the ASK RF signal through the diode, since the ASK RF signal is clipped according to a predetermined capacitance of the diode, it may be difficult to select and demodulate a desired signal range in some cases.

Accordingly, a technical problem of the present invention is to use a demodulator having a clipping circuit implemented with a PMOS transistor to clip an ASK RF signal received from an RF tag to a desired signal range and to grasp information of the RF tag. It is to provide a demodulator and a reader system having the same.

The demodulator for achieving the technical problem is a control voltage generator for generating a control voltage in response to an N-bit (N is a natural number) control signal; A clipping circuit for clipping the ASK RF signal based on the control voltage to generate a clipped signal; A DC remover which receives the clipped signal and removes the DC signal included in the received clipping signal to generate a signal from which the DC signal has been removed; A low pass filter block receiving the signal from which the DC signal has been removed and performing low pass filtering; A variable gain amplifier for amplifying an output signal of the low pass filter block and outputting the amplified signal based on a gain control signal; And a comparator for receiving and comparing the output signal of the variable gain amplifier with a first reference voltage to generate a digital modulated signal.

The first reference voltage is the control voltage generated by the control voltage generator, and the clipping circuit outputs a gate for receiving the control voltage, a first terminal for receiving the ASK RF signal, and the clipped signal. It is implemented with a PMOS transistor having a second terminal for.

The control voltage generator includes a band gap reference (BGR) for generating a second reference voltage; And a voltage level regulator which receives the voltage output from the BGR and adjusts the voltage output from the BGR to a predetermined level based on the N bit (N is a natural number) control signal to output the control voltage.

The low pass filter block has at least two low pass filters connected in series.

An integrated circuit card reader for achieving the technical problem is a digital block for generating a transmission control signal, a control voltage and a gain control signal in response to the N-bit (N is a natural number) control signal output from the controller; A transmitter generating a first digital signal in response to the transmission control signal; And a receiver for modulating the input ASK RF signal into a second digital signal, the receiver clipping the ASK RF signal based on the control voltage and generating a clipped signal; A DC remover for receiving the clipped signal and removing a DC signal included in the received clipping signal to generate a signal from which the DC signal has been removed; A low pass filter block receiving the signal from which the DC signal has been removed and performing low pass filtering; A variable gain amplifier for amplifying an output signal of the low pass filter block and outputting the amplified signal based on a gain control signal; And a comparator for receiving and comparing an output signal of the variable gain amplifier and a first reference voltage to generate a second digital modulated signal, wherein the digital modulated signal is input to the digital block and the digital block is subjected to the digital modulated signal. The converted bits are converted into bits of a predetermined unit corresponding to the digitally modulated signal, and output the converted bits.

The first reference voltage is the control voltage, and the clipping circuit includes a gate for receiving the control voltage, a first terminal for receiving the ASK RF signal, and a second terminal for outputting the clipped signal. It is implemented as a PMOS transistor.

The digital block includes a signal generation block for generating the transmission control signal based on the N bit (N is a natural number) control signal; A control voltage generator configured to output the control voltage based on the N bit (N is a natural number) control signal; A gain control signal generation block for generating the gain control signal based on the N bit (N is a natural number) control signal; And a decoding block converting the bits into bits of a predetermined unit corresponding to the digital modulated signal based on the second digital modulated signal and outputting the converted bits.

The control voltage generator includes a BGR for generating a second reference voltage; And a voltage level regulator which receives the voltage output from the BGR and adjusts the voltage output from the BGR to a predetermined level based on the N bit (N is a natural number) control signal to output the control voltage.

A reader system for achieving the technical problem is a controller for generating an N bit (N is a natural number) control signal; An integrated circuit card reader configured to generate a first digital signal in response to the N bit (N is a natural number) control signal; An LC filter generating a first ASK RF signal based on the first digital signal; An antenna for outputting a first ASK RF signal output from the LC filter as an RF tag or for receiving a second ASK RF signal output from the RF tag; And an attenuator for attenuating the second ASK RF signal output from the antenna and outputting a third ASK RF signal to the integrated circuit card reader, wherein the integrated circuit card reader is configured to include the N bits (N is a natural number). A digital block for generating a transmission control signal, a control voltage, and a gain control signal in response to the control signal; A transmitter for generating the first digital signal in response to the transmission control signal; And a receiver for demodulating the third ASK RF signal into a second digital signal, the receiver clipping the third ASK RF signal based on the control voltage and generating a clipped signal; A DC remover receiving the clipped signal and removing a DC signal included in the received clipping signal to generate a signal from which the DC signal has been removed; A low pass filter block receiving the signal from which the DC signal has been removed and performing low pass filtering; A variable gain amplifier for amplifying an output signal of the low pass filter block and outputting the amplified signal based on a gain control signal; And a comparator for receiving and comparing the output signal of the variable gain amplifier and the first reference voltage to generate a second digital modulated signal.

The digital block includes a signal generation block for generating a transmission control signal based on the N bit (N is a natural number) control signal; A control voltage generator configured to output the control voltage based on the N bit (N is a natural number) control signal; A variable gain control signal generation block for outputting the gain control signal based on the N bit (N is a natural number) control signal; And a decoding block converting the bits into bits of a predetermined unit corresponding to the second digital signal based on the second digital signal and outputting the converted bits.

The control voltage generator includes a BGR for generating a second reference voltage; And a voltage level regulator which receives the voltage output from the BGR and adjusts the voltage output from the BGR to a predetermined level based on the N bit (N is a natural number) control signal to output the control voltage.

The first reference voltage is the control voltage, and the clipping circuit includes a gate for receiving the control voltage, a first terminal for receiving the third ASK RF signal, and a second terminal for outputting the clipped signal. It is implemented with a PMOS transistor having a.

RF tag read method for achieving the technical problem comprises the steps of generating an N-bit (N is a natural number) control signal; Generating a transmission control signal in response to the N bit (N is a natural number) control signal; Generating a first digital signal in response to the transmission control signal; Outputting a first ASK RF signal as an RF tag based on the first digital signal; Attenuating a second ASK RF signal output from the RF tag and generating a third ASK RF signal; Generating a control voltage based on the N bit (N is a natural number) control signal; Clipping the third ASK RF signal based on the control voltage to generate a clipped signal; Receiving the clipped signal and removing a DC signal included in the received clipping signal to generate a signal from which the DC signal has been removed; Receiving the signal from which the DC signal has been removed and performing low pass filtering; Receiving the low-pass filtered signal and the variable gain control signal and amplifying the signal into a predetermined signal; Receiving and comparing an output signal and a control signal of the variable gain amplifier to generate a second digital signal; And outputting bits converted into bits of a predetermined unit corresponding to the second digital signal based on the second digital signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the embodiments of the present invention, reference should be made to the accompanying drawings that illustrate embodiments of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a functional block diagram of a demodulator according to an embodiment of the present invention, and FIG. 2 is a graph showing a waveform in which an ASK RF signal is clipped according to an embodiment of the present invention.

1 and 2, the demodulator 100 or envelope detector 100 includes a control voltage generator 110, a clipping circuit 120, a DC remover 130, and a low pass filter block 140. ), A variable gain amplifier 150, and a comparator 160. The demodulator 100 may also be called an envelope detector because it performs a function for detecting an envelope.

The control voltage generator 110 generates a control voltage Vr1 corresponding to the N-bit control signal Cin in response to an N (N is a natural number) bit control signal Cin. The control voltage generator 100 includes a band gap reference (BGR) 112 and a voltage level controller 114.

The BGR 112 generates a first reference voltage Vro. Preferably, the first reference voltage Vro is a constant voltage. Thus, the BGR 112 performs the function of a voltage regulator.

The voltage level regulator 114 receives an N-bit control signal Cin and the first reference voltage Vro and generates a control voltage Vr1 corresponding to the N-bit control signal Cin. The voltage level regulator 114 may be implemented as a voltage divider. Therefore, the voltage divider divides the first reference voltage Vro into a plurality of levels, and in response to the N-bit control signal Cin, converts any one level among the plurality of levels to the control voltage Vr1. You can print

The clipping circuit 120 receives an ASK RF (Amplitude Shift Keying Radio Frequency) signal, for example, an ASK RF signal Vin output from an RF tag, and clips the received ASK RF signal based on the control voltage Vr1. And generate a clipped ASK RF signal Vc1. The clipping circuit 120 may be implemented with a PMOS transistor Mp.

The PMOS transistor Mp may include a gate for receiving a control voltage Vr1, a first terminal for receiving an ASK RF signal Vin (eg, one of a drain and a source), and a clipped ASK RF signal Vc1. ) Is provided with a second terminal (eg, the other of the drain and the source).

The clipping circuit 120 receives the ASK RF signal Vin to clip the ASK RF signal Vin by the control voltage Vr and the threshold voltage Vth of the PMOS transistor, and the clipped signal Vc1. ).

For example, the waveform of the ASK RF signal Vin input to the clipping circuit 120 is an ASK RF signal having the information signal Vtag of the RF tag, as shown in the waveform of Vin shown in FIG. 2.

The clipping circuit 120 clips the input ASK RF signal Vin by the voltage Vr1 + Vth plus the control voltage Vr1 and the threshold voltage Vth of the PMOS transistor Mp of the clipping circuit. Generates the ASK RF signal Vc1.

The ASK RF signal Vc1 of FIG. 2 is a sinusoidal signal (for example, 13.56MHZ) and may include not only the information signal Vtag of the RF tag but also the sinusoidal signal VL remaining after clipping.

The sinusoidal signal VL of the ASK RF signal Vc1 is removed by low pass filtering of the low pass filter block 140 after AC coupling and DC bias reset by the DC remover 130.

The DC remover 130 receives the clipped ASK RF signal Vc1 output from the clipping circuit 120, removes the DC signal included in the received signal Vc1, and removes the DC signal. (Vc3) is generated.

The low pass filter block 140 receives the signal Vc3 from which the DC signal has been removed and performs low pass filtering. The low pass filter block 140 has at least two low pass filters 141 and 143 connected in series. Accordingly, the low pass filter block 140 may improve low pass characteristics and skirt characteristics. The low pass filter block 140 may be implemented as one low pass filter.

The variable gain amplifier 150 receives and amplifies the output signal Vc5 of the low pass filter block 140 based on the gain control signal Cv and outputs the amplified signal Vc7.

The comparator 160 receives the output signal Vc7 and the second reference voltage Vr1 of the variable gain amplifier 150, compares them, and generates a digital modulated signal Vout.

As shown in FIG. 1, the second reference voltage Vr1 may be a control voltage Vr1 generated by the voltage generator 110 or a voltage supplied through a separate voltage generator (not shown). It may be a DC voltage or a level different from the control voltage Vr1 (eg, a voltage having Vr1 / 2).

For example, the comparator 160 receives and compares the output signal Vc7 and the control voltage Vr1 of the variable gain amplifier 150, and if the output signal Vc7 is greater than the control voltage Vr1, the comparator 160 outputs a high logic level ("1"). In addition, when the output signal Vc7 is smaller than the control voltage Vr1, the comparator 160 outputs a low logic level “0”, so that the comparator 160 pulses the output signal Vc7. Modulates the width.

3 is a functional block diagram of a reader system according to an embodiment of the present invention, and FIG. 4 is a functional block diagram showing a receiver of the reader system. 5 is a functional block diagram illustrating a digital block of the reader system.

3 to 5, the reader system 200 includes a controller (MCU) 210, a signal processing block 220, an LC filter 230, an antenna 240, and an attenuator 250. It is provided. The signal processing block 220 may be implemented as one integrated circuit chip, but is not limited thereto.

The controller (MCU) 210 generates an N bit (N is a natural number) control signal C1.

The signal processing block 220 generates a first digital signal D1 in response to the N-bit control signal C1, receives the ASK RF signal V5 output from the attenuator 250, and receives a predetermined unit of a predetermined unit. The bits C3 converted into bits are outputted to the controller MCU 210.

The signal processing block 220 includes a digital block 222, a transmitter 224, and a receiver 226.

The digital block 222 generates a transmission control signal D1, a control voltage Va, and a gain control signal Cx in response to the N bit (N is a natural number) control signal C1, and the receiver 226 Receives the second digital signal (Vb) output from the () and converts the received second digital signal (Vb) to a predetermined unit of bits and outputs the converted bits (C3) to the controller 210.

As shown in FIG. 5, the digital block 222 includes a signal generating block 310, a control voltage generator 320, a gain control signal generating block 330, and a decoding block. (Decoding Block) 340 is provided.

The signal generation block 310 generates a transmission control signal D1 based on the N-bit control signal C1.

The control voltage generator 320 outputs a control voltage Va corresponding to the N-bit control signal C1 in response to the N-bit control signal C1. The control voltage generator 320 includes a BGR 322 and a voltage level regulator 324.

The BGR 322 generates a first reference voltage Vrf. The first reference voltage Vrf is preferably a constant voltage. Thus, the BGR 322 performs the function of a voltage regulator.

The voltage level regulator 324 receives the N-bit control signal C1 and the first reference voltage Vrf and generates a control voltage Va corresponding to the N-bit control signal C1. The voltage level regulator 324 may be implemented as a voltage divider. Therefore, the voltage divider divides the first reference voltage Vrf into a plurality of levels, and controls any one of the plurality of levels in response to the N-bit control signal C1. You can output

The gain control signal generation block 330 outputs a gain control signal Cx in response to the N-bit control signal C1, and the decoding block 340 generates the gain control signal Cx based on the second digital signal Vb. The bits C3 converted into bits of a predetermined unit corresponding to the second digital signal Vb are output.

The transmitter 224 generates a first digital signal V1 in response to the transmission control signal D1. The receiver 226 receives the ASK RF signal V5 output from the attenuator 250 and demodulates the second digital signal Vb.

The receiver 226 includes a clipping circuit 228, a DC remover 231, a low pass filter block 232, a variable gain amplifier 234, and a comparator 236 as shown in FIG. 4.

The clipping circuit 228 receives the ASK RF signal V5 output from the attenuator 250, clips the received ASK RF signal V5 based on the control voltage Va, and clips the ASK RF signal. Generate signal V7. The clipping circuit 228 may be implemented with a PMOS transistor Mp.

The PMOS transistor Mp has a gate for receiving a control voltage Va, a first terminal for receiving an ASK RF signal V5, and a second terminal for outputting a clipped ASK RF signal V7. do.

The clipping circuit 228 receives the ASK RF signal V5 and clips the ASK RF signal 5 by the threshold voltage of the control voltage Va and the PMOS transistor, and the clipped ASK RF signal V7. ).

The ASK RF signal V7 may have not only an information signal of the RF tag but also a sinusoidal signal remaining after clipping. The sinusoidal signal of the ASK RF signal V7 is removed by low pass filtering of the low pass filter block 232 after AC coupling and DC bias reset by the DC remover.

The DC remover 231 receives the clipped ASK RF signal V7 output from the clipping circuit 228, removes the DC signal included in the received signal V7, and removes the DC signal. (V9) occurs.

The low pass filter block 232 receives the signal V9 from which the DC signal has been removed and performs low pass filtering. The low pass filter block 232 has at least two low pass filters 232-1 and 232-2 connected in series. Accordingly, the low pass filter block 232 may improve low pass characteristics and skirt characteristics. The low pass filter block 232 may be implemented as one low pass filter.

The variable gain amplifier 234 receives and amplifies the output signal V11 of the low pass filter block 232 based on the gain control signal Cx and outputs the amplified signal V13.

The comparator 236 receives the output signal V13 and the second reference voltage Va of the variable gain amplifier 234, compares them, and generates a second digital modulated signal Vb.

As shown in FIG. 4, the second reference voltage Va may be a control voltage Va generated by the voltage control generator 320 or a voltage supplied through a separate voltage generator (not shown). For example, the voltage may be a DC voltage or a level different from the control voltage Va (eg, a voltage having Va / 2).

For example, the comparator 236 receives and compares the output signal V13 of the variable gain amplifier 234 with the control voltage Va, and if the output signal V13 is greater than the control voltage Va, the comparator 236 outputs a high logic level ("1"). In addition, when the output signal V13 is smaller than the control voltage Va, the comparator 236 outputs a low logic level "0", whereby the comparator 236 pulses the output signal V13. Modulates the width.

The LC filter 230 generates a first ASK RF signal V2 based on the first digital signal V1, and the antenna 250 outputs the first ASK RF signal V2 output from the LC filter 230. ) Is output as an RF tag and a second ASK RF signal V4 output from the RF tag is received.

A matcher (not shown) may be connected between the LC filter 230 and the antenna 250, and the matcher sets the first ASK RF signal V2 output from the LC filter 230 to a predetermined impedance. Impedance matching may be output to the antenna 250.

The attenuator 250 receives the second ASK RF signal V4 to generate a predetermined attenuated third ASK RF signal V5.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, by implementing the ASK RF demodulator according to the present invention, it is possible to clip the ASK RF signal received from the RF tag to a desired signal range and easily grasp information of the RF tag from the clipped signal.

As described above, by implementing the reader system having the ASK RF demodulator according to the present invention, the ASK RF signal can be clipped to a desired signal range using a digital control signal, and the information of the RF tag can be easily identified from the clipped signal. .

Claims (16)

A control voltage generator for generating a control voltage in response to an N bit (N is a natural number) control signal; A clipping circuit for clipping an ASK RF (Amplitude Shift Keying Radio Frequency) signal based on the control voltage to generate a clipped signal; A DC remover for receiving the clipped signal, removing a DC signal included in the received clipping signal, and generating a signal from which the DC signal has been removed; A low pass filter block configured to receive the signal from which the DC signal has been removed and perform low pass filtering; A variable gain amplifier receiving and amplifying an output signal of the low pass filter block based on a gain control signal and outputting an amplified signal; And And a comparator configured to receive and compare an output signal of the variable gain amplifier and a first reference voltage to generate a digital modulated signal. The demodulator of claim 1, wherein the first reference voltage is the control voltage generated by the control voltage generator. The method of claim 1, wherein the clipping circuit, And a PMOS transistor having a gate for receiving the control voltage, a first terminal for receiving the ASK RF signal, and a second terminal for outputting the clipped signal. The control apparatus of claim 1, wherein the control voltage generator comprises: a band gap reference (BGR) for generating a second reference voltage; And And a voltage level regulator configured to receive the voltage output from the BGR and adjust the voltage output from the BGR to a predetermined level based on the N-bit (N is a natural number) control signal to output the control voltage. 2. The demodulator of claim 1, wherein the low pass filter block comprises at least two low pass filters connected in series. A digital block for generating a transmission control signal, a control voltage, and a gain control signal in response to an N bit (N is a natural number) control signal output from the controller; A transmitter generating a first digital signal in response to the transmission control signal; And A receiver for modulating the input ASK RF signal into a second digital signal, The receiver, A clipping circuit for clipping the ASK RF signal and generating a clipped signal based on the control voltage; A DC remover for receiving the clipped signal, removing a DC signal included in the received clipping signal, and generating a signal from which the DC signal has been removed; A low pass filter block configured to receive the signal from which the DC signal has been removed and perform low pass filtering; A variable gain amplifier receiving and amplifying an output signal of the low pass filter block based on a gain control signal and outputting an amplified signal; And A comparator for receiving and comparing an output signal of the variable gain amplifier and a first reference voltage to generate a second digital modulated signal, wherein the digital modulated signal is input to the digital block and the digital block is applied to the digital modulated signal. And converting the bits into bits of a predetermined unit corresponding to the digitally modulated signal and outputting the converted bits. The integrated circuit card reader of claim 6, wherein the first reference voltage is the control voltage. The method of claim 6, wherein the clipping circuit, And a PMOS transistor having a gate for receiving the control voltage, a first terminal for receiving the ASK RF signal, and a second terminal for outputting the clipped signal. The method of claim 6, wherein the digital block, A signal generation block for generating the transmission control signal based on the N bit (N is a natural number) control signal; A control voltage generator configured to output the control voltage based on the N bit (N is a natural number) control signal; A gain control signal generation block for generating the gain control signal based on the N bit (N is a natural number) control signal; And And a decoding block converting the bits into bits of a predetermined unit corresponding to the digital modulated signal based on the second digital modulated signal and outputting the converted bits. The method of claim 9, wherein the control voltage generator, A BGR generating a second reference voltage; And An integrated circuit card having a voltage level regulator which receives the voltage output from the BGR and adjusts the voltage output from the BGR to a predetermined level based on the N bit (N is a natural number) control signal and outputs the control voltage; Reader. A controller for generating an N bit (N is a natural number) control signal; An integrated circuit card reader generating a first digital signal in response to the N bit (N is a natural number) control signal; An LC filter generating a first ASK RF signal based on the first digital signal; An antenna for outputting a first ASK RF signal output from the LC filter in an RF tag or for receiving a second ASK RF signal output from the RF tag; And Attenuator for receiving and attenuating the second ASK RF signal output from the antenna and outputting a third ASK RF signal to the integrated circuit card reader, The integrated circuit card reader, A digital block generating a transmission control signal, a control voltage, and a gain control signal in response to the N bit (N is a natural number) control signal; A transmitter for generating the first digital signal in response to the transmission control signal; And A receiver for demodulating the third ASK RF signal into a second digital signal, The receiver, A clipping circuit for clipping the third ASK RF signal based on the control voltage and generating a clipped signal; A DC remover receiving the clipped signal and removing a DC signal included in the received clipping signal to generate a signal from which the DC signal has been removed; A low pass filter block receiving the signal from which the DC signal has been removed and performing low pass filtering; A variable gain amplifier for amplifying an output signal of the low pass filter block and outputting the amplified signal based on a gain control signal; And And a comparator configured to receive and compare an output signal of the variable gain amplifier and a first reference voltage to generate a second digital modulated signal. The method of claim 11, wherein the digital block, A signal generation block for generating a transmission control signal based on the N bit (N is a natural number) control signal; A control voltage generator configured to output the control voltage based on the N-bit control signal; A variable gain control signal generation block outputting the gain control signal based on the N bit control signal; And And a decoding system converting the bits into bits of a predetermined unit corresponding to the second digital signal and outputting the converted bits based on the second digital signal. The method of claim 12, wherein the control voltage generator, A BGR generating a second reference voltage; And And a voltage level controller configured to receive the voltage output from the BGR and adjust the voltage output from the BGR to a predetermined level based on the N-bit (N is a natural number) control signal to output the control voltage. The reader system of claim 11, wherein the first reference voltage is the control voltage. The method of claim 11, wherein the clipping circuit, And a gate for receiving the control voltage, a first terminal for receiving the third ASK RF signal, and a second terminal for outputting the clipped signal. Generating an N bit (N is a natural number) control signal; Generating a transmission control signal in response to the N bit control signal; Generating a first digital signal in response to the transmission control signal; Outputting a first ASK RF signal as an RF tag based on the first digital signal; Attenuating a second ASK RF signal output from the RF tag and generating a third ASK RF signal; Generating a control voltage based on the N bit (N is a natural number) control signal; Clipping the third ASK RF signal based on the control voltage to generate a clipped signal; Receiving the clipped signal and removing a DC signal included in the received clipping signal to generate a signal from which the DC signal has been removed; Receiving the signal from which the DC signal has been removed and performing low pass filtering; Receiving the low-pass filtered signal and the variable gain control signal and amplifying the signal into a predetermined signal; Receiving and comparing an output signal and a control signal of the variable gain amplifier to generate a second digital signal; And And outputting bits converted into bits of a predetermined unit corresponding to the second digital signal based on the second digital signal.

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