KR100656469B1 - Apparatus for controlling power down of semiconductor memory - Google Patents

Abstract

A power down control apparatus of a semiconductor memory is provided to perform DLL(Delay Locked Loop) update by controlling a power down mode. A timing control unit(200) controls transition timing of a clock enable signal according to a reset signal. A driving unit(300) outputs a second clock enable signal by using the clock enable signal and an output of the timing control unit. A reset signal generation unit(400) generates the reset signal according to the clock enable signal. The timing control unit is a shift register delaying the clock enable signal in a clock unit.

Description

Apparatus for Controlling Power Down of Semiconductor Memory

1 is a timing diagram of a power down operation according to the prior art;

2 is a timing diagram of a self refresh emulation mode according to the related art;

3 is a block diagram showing the configuration of a power down control apparatus for a semiconductor memory according to the present invention;

4 is a circuit diagram illustrating an internal configuration of a timing controller of FIG. 3;

5A and 5B are circuit diagrams illustrating an internal configuration of the driver of FIG. 3;

6 is a circuit diagram illustrating an internal configuration of a reset signal generator of FIG. 3;

7 is an operation timing diagram of the driver of FIG. 3;

8 is an operation timing diagram of the reset signal generator of FIG. 3;

9 is a timing diagram of a power-down operation of the semiconductor memory according to the present invention.

<Description of Symbols for Main Parts of Drawings>

100: buffer 200: timing control unit

210 to 240: flip-flop 300: driver

400: reset signal generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memories, and more particularly, to a power down control apparatus for semiconductor memories.

In general, various methods for controlling current are used in semiconductor memories.

Among the modes affecting the operation of the DLL (Delay Locked Loop), a power down mode (PWDN) and a self refresh emulation mode (hereinafter referred to as SREM) are mentioned.

A conventional semiconductor memory enters a power down mode when the external clock enable signal CKE is low with a NOP (No Operation) or Desel (Device Deselect) command while the semiconductor memory is selected.

That is, as shown in FIG. 1, when the external clock enable signal CKE is low while NOP or Desel is in a state, the power clock enters a power-down mode in synchronization with a rising edge of a next clock.

When CKE goes high again, it will exit the power-down mode in synchronization with the rising edge of the next clock.

At this time, the power-down mode in Bank All Precharge is set to the precharge power-down mode. In this case, the DLL is turned off or in a standby state.

At this time, when the entry and exit of the power down mode is repeated in the minimum required time unit of the CKE, the active, off, or standby state of the DLL is repeated for a long time. In this case, the update of the DLL, that is, the clock synchronization timing correction operation cannot be performed and the normal output of the data cannot be guaranteed.

Meanwhile, the SREM combines a power down mode and an auto refresh operation to create a state similar to self refresh. After the self-refresh operation, it is standardized to access the chip after waiting a considerable time, but the SREM can access the chip in a much shorter time.

That is, when the power is down for a long time as shown in FIG. 2, a minimum command time of the external clock enable signal CKE is performed, for example, in units of three clocks. When used as (3 * tCK) and the auto refresh command is input from the outside of the chip in the high section of the CKE, it is executed like the self refresh command generated inside the chip.

However, the update of the DLL is performed in the high section of the CKE. As shown in FIG. 2, when the SREM is performed, the high section of the CKE is too short and the DLL update is not normally performed.

In order to solve this problem, a conventional method of guaranteeing internal timing by using a refresh or precharge signal, which is an asynchronous signal that does not operate based on a clock, has been used.

However, according to the related art, the internal timing guaranteed by using the asynchronous signal, the refresh or precharge signal, is too short for the time required for updating the DLL operating based on the clock (for example, 5tCK to 20tCK). too long. Therefore, there is a problem that a data output error occurs because the DLL is not updated correctly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to provide a power-down control apparatus for a semiconductor memory in which a DLL update is normally performed by controlling a power-down mode.

A power down control apparatus for a semiconductor memory according to the present invention includes timing control means for controlling and outputting a transition timing of a clock enable signal according to a reset signal; Driving means for outputting a second clock enable signal using the clock enable signal and the output of the timing control means; And reset signal generating means for generating the reset signal according to the clock enable signal.

Hereinafter, a preferred embodiment of a power down control apparatus for a semiconductor memory according to the present invention will be described with reference to the accompanying drawings.

3 is a block diagram showing a configuration of a power down control apparatus of a semiconductor memory according to the present invention, FIG. 4 is a circuit diagram showing an internal configuration of the timing controller of FIG. 3, and FIGS. 5A and 5B are diagrams showing an internal configuration of the driver of FIG. 6 is a circuit diagram showing an internal configuration of the reset signal generator of FIG. 3, FIG. 7 is an operation timing diagram of the driver of FIG. 3, FIG. 8 is an operation timing diagram of the reset signal generator of FIG. Is a timing diagram of power-down operation of a semiconductor memory.

As shown in FIG. 3, the apparatus for controlling power down of a semiconductor memory according to the present invention refers to an internal clock enable signal iCKE (hereinafter, referred to as a clock enable signal) buffered with an external clock enable signal CKE. The timing controller 200 for controlling and outputting the transition timing of the clock enable signal iCKE, that is, the transition timing from low to high, according to the output buffer 100 and the reset signal RST, and the clock enable signal ( The driver 300 outputs the second clock enable signal CKE1 by performing an OR operation on the output of the iCKE and the timing controller 200, and generates the reset signal RST according to the clock enable signal iCKE. The reset signal generator 400 is included.

As illustrated in FIG. 4, the timing controller 200 receives the clock enable signal iCKE as an initial input and transfers the clock enable signal in units of a clock CLK, thereby allowing a plurality of D flips to be delayed by a desired clock CLK. It consists of shift registers consisting of flops 210 to 240. Therefore, the timing controller 200 receives the clock enable signal iCKE and outputs a delayed clock enable signal iCKED.

The driver 300 is configured to output a second clock enable signal CKE1 high when at least one of the clock enable signal iCKE and the output of the timing controller 200 is at a high level, and FIG. 5A or FIG. It can be implemented in the logic as shown in Figure 5b.

As shown in FIG. 5A, the driver 300 receives a first inverter IV1 receiving the clock enable signal iCKE and a second inverter IV2 receiving the delayed clock enable signal iCKED. A first NAND gate ND1 receiving the outputs of the first inverter IV1 and the second inverter IV2, a third inverter IV3 receiving the output of the first NAND gate ND1, and And a fourth inverter IV4 that receives the output of the third inverter IV3 and outputs the second clock enable signal CKE1.

As shown in FIG. 5B, another configuration example of the driver 300 includes a NOR gate NOR1 receiving the clock enable signal iCKE and the delayed clock enable signal iCKED, and the NOR gate NOR1. And a fifth inverter IV5 for receiving the output of the second output signal and outputting the second clock enable signal CKE1.

The reset signal generator 400 may include an inverter chain 410 that receives the clock enable signal iCKE, a second NAND gate that receives an output of the inverter chain 410 and the clock enable signal iCKE. And a sixth inverter IV6 receiving the output of the second NAND gate ND2 and outputting a reset signal RST.

The operation of the power-down control device of the semiconductor memory according to the present invention configured as described above is as follows.

Prior to the detailed description, the present invention controls the time for updating the DLL, that is, the high period of the clock enable signal iCKE so that the normal update of the DLL is performed. Hereinafter, the operation of the present invention will be described with reference to FIGS. 3 to 9.

The buffer 100 of FIG. 3 buffers the clock enable signal CKE and outputs the buffered clock enable signal iCKE as shown in FIGS. 7 to 9.

The iCKE is commonly input to the timing controller 200, the driver 300, and the reset signal generator 400 of FIG. 3.

Next, the timing controller 200 of FIG. 4 outputs the delayed clock enable signal iCKED by delaying the iCKE by a clock unit (for example, 4tCK) as shown in FIG. 7.

At this time, the delayed clock enable signal iCKED is changed to low after delaying the high section of the iCKE by a predetermined clock unit, and changes to high again according to the reset signal RST output from the reset signal generator 400.

Subsequently, the driver 300 of FIG. 5A outputs the second clock enable signal CKE1 by ORing iCKE and iCKED as shown in FIG. 7.

In this case, as shown in FIG. 7, when the second clock enable signal CKE1 goes from low to high, the second clock enable signal CKE1 goes high on the rising edge of the clock CLK. When the iCKE goes high from low, the iCKED The signal goes low after a delay.

Meanwhile, as shown in FIG. 8, the reset signal generator 400 of FIG. 6 outputs a pulse type reset signal RST to the timing controller 200 at a timing when iCKE changes from low to high.

As illustrated in FIG. 9, the second clock enable signal CKE1 according to the present invention has a higher period than the clock enable signal according to the related art. That is, the timing at which the power down ends according to the clock enable signal is the same as in the related art, but the time for re-entering the power down is extended.

Therefore, while the second clock enable signal CKE1 is kept high, the power-down is terminated and the DLL becomes active. During this time, the DLL update can be normally performed.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

In the power down control apparatus of the semiconductor memory according to the present invention, since the DLL update is normally performed even when the clock enable signal operates in the unit of the minimum required time, the data output is normally performed, thereby improving the reliability of the semiconductor memory.

Claims (8)

Timing control means for controlling and outputting a transition timing of the clock enable signal according to the reset signal; Driving means for outputting a second clock enable signal using a clock enable signal and an output of the timing control means; And And a reset signal generating means for generating the reset signal in accordance with the clock enable signal. The method of claim 1, And the timing control means comprises a shift register for delaying and outputting the clock enable signal by a clock unit. The method of claim 1, And the driving means is configured to output a second clock enable signal high when at least one of the clock enable signal and the output of the timing control means is at a high level. The method of claim 1, The driving means A first inverter receiving the clock enable signal; A second inverter receiving an output of the timing control means; A NAND gate receiving the outputs of the first inverter and the second inverter, A third inverter receiving an output of the NAND gate, and And a fourth inverter receiving the output of the third inverter and outputting the second clock enable signal. The method of claim 1, The driving means Noah gate receiving the clock enable signal and the output of the timing control means, and And an inverter configured to receive the output of the NOR gate and output the second clock enable signal. The method of claim 1, The reset signal generating means An inverter chain receiving the clock enable signal; A NAND gate receiving the output of the inverter chain and the clock enable signal, and And an inverter configured to receive an output of the NAND gate and output a reset signal. The method of claim 1, And the clock enable signal is an internal clock enable signal buffered with an external clock enable signal. The method of claim 7, wherein And buffering means for buffering the external clock enable signal.

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