KR100644556B1 - High speed inverse discrete cosine transform device - Google Patents

Abstract

Disclosed are a fast inverse discrete cosine transform apparatus capable of performing inverse discrete cosine transform on an HD image and a prememory scanning method performed in the inverse discrete cosine transform apparatus. The inverse discrete cosine transform apparatus includes one one-dimensional inverse discrete cosine transform unit for inputting a sample output from an inverse quantizer to perform inverse discrete cosine transform and result data output from the one one-dimensional inverse discrete cosine transform unit. And a first one-dimensional inverse discrete cosine transform unit for performing one-dimensional inverse discrete cosine transformation by reading the result data from the prememory and storing the result data from the prememory, and sequentially performing inverse discrete cosine transformation in the vertical and horizontal directions. Simultaneous reading of a sample to be performed and writing of a result sample are performed at predetermined time intervals, and reading and writing processes are alternately performed for two memory banks. The inverse discrete cosine transform apparatus can perform inverse discrete cosine transform on an HD-class image that requires high speed processing, and requires less amount of transpose memory.

Description

High speed inverse discrete cosine transform device

1A is a diagram for describing a discrete cosine transform (DCT) process performed in an MPEG encoding process.

FIG. 1B is a diagram illustrating an inverse discrete cosine transform (IDCT) process performed in an MPEG decoding process.

2 is a block diagram showing the structure of a conventional two-dimensional inverse discrete cosine transform apparatus.

3A is a block diagram illustrating in detail the structure of a 16-bit one-dimensional inverse discrete cosine transform unit.

FIG. 3B is a detailed block diagram illustrating the structure of the shift register bank of FIG. 3A.

FIG. 3C is a detailed block diagram illustrating the structure of an inverse discrete cosine transform (IDCT) element of FIG. 3A.

4 is a block diagram showing the structure of a fast inverse discrete cosine transform apparatus according to an embodiment of the present invention.

5A illustrates a structure of a shift register bank for performing 12-bit inverse discrete cosine transform.

5B illustrates a structure of a shift register bank for performing 16-bit inverse discrete cosine transform.

6A and 6B are block diagrams illustrating in detail the structures of a 12-bit one-dimensional inverse discrete cosine transform performing unit and a 16-bit one-dimensional inverse discrete cosine transform performing unit, respectively.

FIG. 7 is a diagram for describing an order in which 12-bit one-dimensional discrete cosine transformed samples are input to a pre-memory.

8 is a diagram showing the write and read addresses of the transpose memory.

9A and 9B are flowcharts showing main steps of a pre-memory memory scanning method according to an embodiment of the present invention performed in a fast inverse discrete cosine transform apparatus according to the present invention.

FIG. 10A is a diagram for describing a procedure of writing and reading in the vertical direction on the transpose memory. FIG.

FIG. 10B is a diagram for describing a procedure of writing and reading in the horizontal direction on the transpose memory.

Fig. 11 shows the positions of write and read addresses and processing coefficients on the pre-memory.

The present invention relates to an Inverse Discrete Cosine Transform (IDCT) device, and more particularly, to an inverse Discrete Cosine Transform device.

The present invention also relates to a pre-memory scanning method performed in the inverse discrete cosine transform apparatus.

MPEG video decoders are applied in almost all technical fields related to the storage and transmission of digital video such as digital TVs, DVD players, and the Internet. Such MPEG image decoders are referred to as Inverse Discrete Cosine Transform (IDCT), together with Variable Length Decoder (VLD), Inverse Quantization (IQ), and Motion Compensation (MC). ) Is essential. The inverse discrete cosine transform speed is the most important variable for high speed image processing.

FIG. 1A illustrates a diagram for describing a general discrete cosine transform process performed in an MPEG encoding process. Referring to FIG. 1A, each block 100 serving as a unit of the discrete cosine transform process is composed of 8 × 8 pixels in the pixel domain. The first matrix 102 is constructed by performing one-dimensional discrete cosine transform on the block 100 in the horizontal direction. Next, one-dimensional discrete cosine transform is performed on the first matrix 102 in the vertical direction to form the second matrix 104. Here, the block 100 corresponds to the pixel domain, and the first and second matrices 102 and 104 correspond to the frequency domain.

In the MPEG decoding process, an inverse discrete cosine transform process as shown in FIG. 1B is performed. Referring to FIG. 1B, the inverse discrete cosine transform process is an inverse order of the discrete cosine transform process. That is, the fourth matrix 122 is constructed by performing one-dimensional inverse discrete cosine transform on the third matrix 120 in the frequency domain in the vertical direction. Next, block 144 is restored by performing one-dimensional inverse discrete cosine transform on the fourth matrix.

2 shows a block diagram of a conventional two-dimensional inverse discrete cosine transform apparatus. Referring to FIG. 2, the conventional two-dimensional inverse discrete cosine transform unit includes a 16-bit one-dimensional inverse discrete cosine transform unit 22 and a pre-memory 24. The 16-bit one-dimensional inverse discrete cosine transform unit 22 and the prememory memory 24 each consist of two inverse discrete cosine transform processing blocks and two 8x8 block size pre-memory.

If two inverse discrete cosine transform processing blocks are called first and second inverse discrete cosine transform processing blocks, respectively, and two 8x8 block size pre-memory are assumed to be first and second pre-memory, respectively, First, the first inverse discrete cosine transform processing block performs vertical inverse discrete cosine transform, for example, and writes the result to the first pre-memory. Next, the second inverse discrete cosine transform processing block reads the inverse discrete cosine transform result stored in the first pre-memory memory, performs the inverse discrete cosine transform in the horizontal direction, and stores the result in the second pre-memory memory. Therefore, it takes 8 clocks to perform both vertical and horizontal inverse discrete cosine transform for one block.

FIG. 3A shows a detailed structure of the 16-bit one-dimensional inverse discrete cosine transform unit 22 in a block diagram. Referring to FIG. 3A, the 16-bit one-dimensional inverse discrete cosine transform unit 22 includes a shift register bank 30 (SREG BANK) and an inverse discrete cosine transform element 20.

Referring to FIG. 3B, the structure of the shift register bank of FIG. 3A will be described. The shift register bank in the inverse discrete cosine transform element of the conventional inverse discrete cosine transform apparatus includes 16 bit shift register banks Bank0_0, Bank0_1, Bank0_2, and Bank0_3. And a first bank consisting of Bank0_4, Bank0_5, Bank0_6, and Bank0_7, and a second bank consisting of 16-bit shift register banks Bank1_0, Bank1_1, Bank1_2, Bank1_3, Bank1_4, Bank1_5, Bank1_6, and Bank1_7. Inverse discrete cosine transform is performed on the input bits by an inverse discrete cosine transform element having a structure as shown in FIG. 3C.

However, such a conventional inverse discrete cosine conversion device requires 8 clocks to perform both vertical and horizontal inverse discrete cosine transformation for one block as described above. However, there is a problem in that the inverse discrete cosine transform is not sufficient for an HD image that requires more than four times the processing speed of the SD image.

An object of the present invention is to provide a fast inverse discrete cosine transform apparatus capable of performing inverse discrete cosine transform on an HD image.

Another object of the present invention is to provide a pre-memory scanning method performed in the inverse discrete cosine transform apparatus as described above.

According to an aspect of the present invention, there is provided a fast inverse discrete cosine transform apparatus comprising: a one-dimensional inverse discrete cosine transform unit configured to perform inverse discrete cosine transform by inputting a sample output from an inverse quantizer; A pre-memory storing the result data output from the first one-dimensional inverse discrete cosine transform unit; And another one-dimensional inverse discrete cosine transform unit that reads the result data from the prememory memory and performs one-dimensional inverse discrete cosine transform. The sample includes: a sample for sequentially performing inverse discrete cosine transform in the vertical direction and the horizontal direction. The read and write of the resultant sample are simultaneously performed at predetermined time intervals, and the read and write processes are alternately performed for the two memory banks.

According to another aspect of the present invention, a high speed inverse discrete cosine conversion apparatus according to another aspect of the present invention inputs a first predetermined number of bits output from an inverse quantizer to perform inverse discrete cosine transformation on a clock by a second predetermined number of bits. A first inverse discrete cosine transform unit for performing; A pre-memory of a block having a first predetermined size for storing a result output from the first inverse discrete cosine transform unit; And a second inverse discrete cosine transform unit configured to perform inverse discrete cosine transform by a third predetermined number of bits in one clock, wherein the second inverse discrete cosine transform includes: reading a sample for sequentially performing inverse discrete cosine transform in the vertical direction and the horizontal direction; The writing of the resultant samples is performed simultaneously with a predetermined time difference, and the reading and writing processes are alternately performed for the two memory banks.

Wherein the first predetermined number is 12, the second predetermined number is 3, and the first inverse discrete cosine transform unit comprises: a shift register bank formed of six banks of four, five, six, and seven bits; And a three-bit block one-dimensional inverse discrete cosine transform unit in which eight samples are four-dimensionally one-dimensional inverse discrete cosine transformed at four clocks.

Also, it is preferable that the first predetermined size is eight.

The third predetermined number is 4, and the second inverse discrete cosine transform unit comprises: a shift register bank formed by providing eight banks of four, five, six, and seven bits; And a 4-bit block one-dimensional inverse discrete cosine transform unit in which eight samples are four-dimensionally one-dimensional inverse discrete cosine transformed at four clocks.

In addition, the first inverse discrete cosine transform performing unit and the second inverse discrete cosine transform performing unit may be configured in a group of 4 bits and 3 bits, respectively, so as to be performed at four clocks for eight one-dimensional inputs.

In order to achieve the above object, the pre-memory scanning method according to the present invention comprises two memory banks and a pre-memory scanning method performed in an inverse discrete cosine transform apparatus for performing inverse discrete cosine transform in a video compression decoder. wa) setting to perform reading in the horizontal or vertical direction; (wb) alternately reading from the two memory banks; (wc) checking whether a block of the pre-memory in which the read is performed corresponds to the last row; (wd) if the last row in step (wc), checks whether the row corresponds to the last column; (we) if the last row in step (wd), but is not the last column, altering the order of performing the steps; And (Wf) changing the writing direction to perform the steps (wa) to (wf); and initializing to perform reading in the horizontal direction. (rb) alternately reading from two banks; (rc) checking whether the block of the pre-memory that performed the read corresponds to the last row; (rd) if the last row in step (rc), checking whether the row corresponds to the last column; (re) if the last row in step (rd) but is not the last column, changing the order of alternation to perform the steps; And (rf) changing the read direction to perform the steps (ra) to (rf).

The method may further include: checking whether writing to the 51st sample has ended and branching to a reading process; And checking whether the reading of the 51st sample has ended.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram illustrating a structure of a fast inverse discrete cosine transform apparatus according to an exemplary embodiment of the present invention. 4, a fast inverse discrete cosine transform apparatus according to the present invention includes a 12-bit one-dimensional inverse discrete cosine transform unit 42, a pre-memory 44, and a 16-bit one-dimensional IDCT unit 46. As shown in FIG. Here, the structure of the shift register bank for performing 12-bit inverse discrete cosine transform is shown in FIG. 5A, and the structure of the shift register bank for performing 16-bit inverse discrete cosine transform is shown in FIG. 5B. .

Referring to FIG. 5A, the shift register bank for the 12-bit one-dimensional inverse discrete cosine transform unit 42 includes 7-bit banks BANK0_2, BANK0_1, BANK0_0, BANK1_2, BANK1_1 and BANK1_0, and 6-bit bank BANK2_2. BANK2_1, BANK2_0, BANK3_2, BANK3_1, BANK3_0), 5-bit banks (BANK4_2, BANK4_1, BANK4_0, BANK5_2, BANK5_1, BANK5_0), and 4-bit banks (BANK6_2, BANK6_1, BANK6_0, BANK7_2, BANK7_1) Equipped.

Referring to FIG. 5B, the shift register bank for the 16-bit one-dimensional inverse discrete cosine transform unit 46 is a 7-bit bank (BANK0_3, BANK0_2, BANK0_1, BANK0_0, BANK1_3, BANK1_2, BANK1_1, BANK1_0), and 6-bit size. Banks (BANK3_3, BANK2_2, BANK2_1, BANK2_0, BANK3_3, BANK3_2, BANK3_1, BANK3_0), 5-bit banks (BANK4_3, BANK4_2, BANK4_1, BANK4_0, BANK5_3, BANK5_2, BANK5_1, BANK5_3), and 4-bit banks , BANK6_2, BANK6_1, BANK6_0, BANK7_3, BANK7_2, BANK7_1, BANK7_0).

The 12-bit one-dimensional inverse discrete cosine transform unit 42 includes a shift register bank shown in FIG. 5A and a plurality of inverse discrete cosine transform element portions shown in FIG. 6A. The 12-bit one-dimensional inverse discrete cosine transform unit 42 includes a three-bit block one-dimensional inverse discrete cosine transform unit for one-dimensional inverse discrete cosine transforming eight samples at four clocks. For example, the transform unit may include an inverse discrete cosine transform element unit shown in FIG. 6A.

The 16-bit one-dimensional inverse discrete cosine transform unit 46 includes a shift register bank shown in FIG. 5B and a plurality of inverse discrete cosine transform element parts shown in FIG. 6B. The 16-bit one-dimensional inverse discrete cosine transform unit 46 includes a four-bit block one-dimensional inverse discrete cosine transform unit for one-dimensional inverse discrete cosine transform of eight samples at four clocks. For example, the transform unit may include an inverse discrete cosine transform element shown in FIG. 6B.

The operation of the apparatus as described above will be described below. FIG. 7 shows an order in which 12-bit one-dimensional discrete cosine transformed samples are input to the pre-memory. Referring to FIG. 7, each sample is composed of 16 bits and is sequentially input to the pre-memory by two samples out of 64 samples.

When two samples are input to the shift register bank shown in Fig. 5A, the samples are divided and stored in banks 7-bit size BANK0_2, BANK0_1, BANK0_0, BANK1_2, BANK1_1, and BANK1_0. The next two samples are stored in 6-bit banks (BANK2_2, BANK2_1, BANK2_0, BANK3_2, BANK3_1, BANK3_0). Two right-by-bit samples are input and one-dimensional inverse discrete cosine transform. The remaining banks operate in the same way. As a result, two 12-bit samples are input and one-dimensional inverse discrete cosine transform is performed.

The shift register bank shown in Fig. 5B is divided into seven-bit banks BANK0_3, BANK0_2, BANK0_1, BANK0_0, BANK1_3, BANK1_2, BANK1_1, and BANK1_0. The next two samples are stored in 6-bit banks (BANK2_3, BANK2_2, BANK2_1, BANK2_0, BANK3_3, BANK3_2, BANK3_1, BANK3_0), and the 7-bit banks (BANK0_3, BANK0_2, BANK0_1, BANK0_0, BANK1_3, BANK1_2, BANK1_1). , Samples stored in BANK1_0) are shifted right by one bit. The remaining banks operate in the same way. In this way, two 16-bit samples are input and one-dimensional inverse discrete cosine transform is performed.

6A and 6B show, in block diagrams, structures of a 12-bit one-dimensional inverse discrete cosine transform performing unit and a 16-bit one-dimensional inverse discrete cosine transform performing unit, respectively. 6A and 6B, a 12-bit one-dimensional inverse discrete cosine transform performing unit and a 16-bit one-dimensional inverse discrete cosine transform performing unit perform four-bit and three-bit groups to be performed at four clocks on eight one-dimensional inputs. Implement as type Here, ADD represents an adder, and ROME_0, ROME_1, ROME_2, and ROME_3, and ROMO_0, ROMO_1, ROMO_2, and ROMO_3, respectively, represent an even-numbered and odd-numbered ROM.

FIG. 7 is a diagram illustrating a sequence of inputting 12-bit one-dimensional discrete cosine transformed samples into the pre-memory. Referring to FIG. 7, 12-bit one-dimensional discrete cosine transformed samples are input to the pre-memory in the order of (0, 1), (2, 3), (4, 5), and (6, 7).

8 shows the write and read addresses of the transpose memory. In this embodiment, using a dual port SDRAM, one set of memories as shown in Fig. 8 constitutes one pre-memory in which 64 sample blocks are stored or read out. Hereinafter, operations of the write and read addresses of the pre-memory will be described based on allocation as shown in FIG. 8.

9A and 9B are flowcharts illustrating main steps of a pre-memory memory scanning method according to an embodiment of the present invention performed in a fast inverse discrete cosine transform apparatus according to the present invention. 9A illustrates the writing process, and FIG. 9B illustrates the reading process. This pre-memory scanning method is often referred to below.

First, referring to FIG. 9A, in the pre-memory scanning method according to the embodiment of the present invention, the writing process is controlled to perform writing in the vertical direction, for example, as an initial mode. In performing a write, for example, writing alternately to two banks (step 902). Next, it is checked whether the block of the pre-memory that has been written corresponds to the last row (step 904), and if it is the last row, it is checked whether it corresponds to the last column in the row (step 906). At this time, if it is the last row, but not the last column, the alternating order is changed (step 908) to perform steps 902 and 904. The change of the alternating order in this way is because the reads must be performed alternately for each bank at the same time while the writing is performed. In the case of the last row and the last column, the write mode is changed to the horizontal direction (step 910), and the above steps are repeatedly performed. If writing to one 8 × 8 block shown in FIG. 7 is completed, the writing process is terminated in the transpose memory scanning method of FIG. 9A.

According to the pre-memory scanning method according to the present invention, a read process is performed simultaneously with the write process. 9B is a flowchart illustrating main steps of a reading process in the transpose memory scanning method according to an embodiment of the present invention. 9B, in the pre-memory scanning method according to the present invention, the reading process is set to perform reading in the horizontal direction, for example, as an initial mode (step 922). In performing a read, for example, alternate readings are performed from two banks (step 924). Next, it is checked whether the block of the pre-memory where the read is performed corresponds to the last row (step 926), and if it is the last row, it is checked whether it corresponds to the last column in the row (step 928). At this time, if the last row, but not the last column, the alternating order is changed (step 930) to perform steps 924 and 926. This change in the alternating order is because the writes must be performed alternately bank by bank while reading is performed. Now, in the case of the last row and the last column, the read mode is changed to the horizontal direction (step 932) and the above steps are repeatedly performed. If the reading of one 8 × 8 block shown in FIG. 7 is completed, the reading process is terminated in the pre-memory scanning method of FIG. 9A.

The pre-memory scanning method according to the present invention performs writing and reading using one pre-memory bank. Therefore, read must be performed while writing is performed. For this reason, it is preferable to start the reading process by checking whether writing to the 51st sample has been performed in the vertical or horizontal direction.

10A and 10B illustrate the order of writing and reading in the vertical direction and the order of writing and reading in the horizontal direction on the transpose memory, respectively. That is, the same applies to the prememory scanning and writing.

Referring to FIG. 10A, a procedure of performing writing in the vertical direction on the transpose memory will be described. First, the (00,01) sample of FIG. 7 is respectively addressed to the address 0 of the bank 0 and the bank 1 Bank. Record at address (4) of 1). Next, the samples (02,03) in FIG. 7 are written to the address 8 of the bank 0 and the address 12 of the bank 1, respectively. In the same way, record for the (4,5) sample in Fig. 7, and record the (6,7) sample corresponding to the last row in the column, then shift the order to bank the (8,9) sample. It is written to address (0) of 1 (Bank 1) and address (4) of bank 0 (Bank 0). In the same way, the recording in the vertical direction for the samples (10, 11), ... (62, 63) is performed, followed by the recording in the horizontal direction.

Referring to FIG. 10B, a procedure of performing writing in the horizontal direction on the transpose memory will be described. First, (00,01) samples are respectively written at the address (0) and the bank 1 (Bank 1) of the bank 0. Write to address (0). Next, (02,03) samples are recorded in address 1 of bank 0 and address 1 of bank 1, respectively. In the same way, record for the (4,5) sample, record the (6,7) sample that corresponds to the last column in the row, and then reverse the order to transfer the (8,9) sample to Bank 1 (Bank 1). ) Is written in address 4 of the bank and address 4 of the bank 0. In the same way, the horizontal writing of the samples (10, 11), ... (62, 63) is performed, and then the vertical writing is performed again. When writing to the 51st sample is finished, the reading process starts. Since the reading process is the same as the above-described order, the description is omitted.

In order to explain a process of reading and writing on the pre-memory according to the pre-memory scanning method as described above, FIG. 11 shows the positions of the write and read addresses and the processing coefficients on the pre-memory.

The starting process of writing in the vertical direction is referred to as (W_V1). In this process, the (0,1) samples are simultaneously written in FIG. At this time, 0 and 1 are recorded at address 0 of bank 0 (BANK 0) and address 4 of bank 1 (BANK 1), respectively. The next clock is referred to as performing (W_V2). In this process, (2,3) samples are simultaneously written. At this time, 2 and 3 are recorded at address 8 of bank 0 (BANK 0) and address 12 of bank 1 (BANK 1), respectively. After performing the recording for the last column (6,7), change the order of the reading shift, and then change the (8,9) sample to address 0 of bank 1 (BANK 0) and address of bank 1 (BANK 1). Record each at number four.

Now, after writing to the (50, 51) samples is completed, the horizontal read is performed. The starting process of reading in the horizontal direction is referred to as (R_H1). In this process, (0,8) samples are read from address 0 of bank 0 (BANK 0) and address 0 of bank 1 (BANK 1), respectively. The next clock is referred to as performing (R_H2). This process simultaneously reads (16,24) samples. At this time, 16 and 24 are read from address 1 of bank 0 (BANK 0) and address 1 of bank 1 (BANK 1). After reading the (48,56) samples corresponding to the last row, change the order of the read alterations so that the (1,9) samples are replaced by address 4 of bank 1 (BANK 0) and bank 1 (BANK 1). Read from address 4.

When writing in the vertical direction is completed, write in the horizontal direction is performed. The starting process of writing in the vertical direction is referred to as (W_H1). In this process, (0,8) samples are written to address 0 of bank 0 (BANK 0) and address 0 of bank 1 (BANK 1), respectively. The next clock is referred to as performing (W_H2). In this process, (16,24) samples are written to address 1 of bank 0 (BANK 0) and address 1 of bank 1 (BANK 1), respectively. Thus, pipeline switching is repeated by alternately performing vertical and horizontal scanning with only 8x8 memory.

As a result, the fast inverse discrete cosine transform apparatus according to the present invention requires four clocks to perform both vertical and horizontal inverse discrete cosine transform in one block, and thus requires more than four times the processing speed of the SD image. It is suitable for inverse discrete cosine transform for HD-quality image.

As described above, the fast inverse discrete cosine transform apparatus and method thereof according to the present invention can process one block with four clocks, and thus it is possible to perform inverse discrete cosine transform on an HD-class image requiring high speed processing. The amount of transpose memory is small.

Claims (8)

An inverse discrete cosine transform apparatus for performing inverse discrete cosine transform in an image compression decoder, A one-dimensional inverse discrete cosine transform unit for inputting a sample output from the inverse quantizer to perform inverse discrete cosine transform; A pre-memory memory for storing result data output from the one-dimensional inverse discrete cosine transform unit; And And another one-dimensional inverse discrete cosine transform unit that reads the result data from the prememory memory and performs one-dimensional inverse discrete cosine transform. Sample reading and writing of the resultant sample are sequentially performed on the two memory banks in the pre-memory to sequentially perform the inverse discrete cosine transform in the vertical direction and the horizontal direction. A fast inverse discrete cosine transform device, characterized in that, after a time has passed, a sample read and a sample write are simultaneously performed in the prememory. An inverse discrete cosine transform apparatus for performing inverse discrete cosine transform in an image compression decoder, A first inverse discrete cosine transform unit configured to input a sample of a first predetermined number of bits output from the inverse quantizer to perform inverse discrete cosine transform by a second predetermined number of bits in one clock; A pre-memory of a block having a first predetermined size for storing a result output from the first inverse discrete cosine transform unit; And And a second inverse discrete cosine transform unit performing a third discrete cosine transform on a clock by a third predetermined number of bits. Sample reading and writing of the resultant sample are sequentially performed on the two memory banks in the pre-memory to sequentially perform the inverse discrete cosine transform in the vertical direction and the horizontal direction. A fast inverse discrete cosine transform device, characterized in that, after a time has passed, a sample read and a sample write are simultaneously performed in the prememory. The method of claim 2, The first predetermined number is 12, the second predetermined number is 3, The first inverse discrete cosine transform unit may include: a shift register bank including six banks of four, five, six, and seven bits; And a three-bit block one-dimensional inverse discrete cosine transform unit in which eight samples are four-dimensionally one-dimensional inverse discrete cosine transformed at four clocks. The method of claim 2, And said first predetermined size is eight. The method of claim 2, The third predetermined number is four, The second inverse discrete cosine transform unit comprises: a shift register bank comprising eight banks of four, five, six, and seven bits; And a 4-bit block one-dimensional inverse discrete cosine transform unit in which eight samples are four-dimensionally one-dimensional inverse discrete cosine transformed at four clocks. The method of claim 2, The first inverse discrete cosine transform performing unit and the second inverse discrete cosine transform performing unit are each configured in 4-bit and 3-bit group types so as to be performed at four clocks for eight one-dimensional inputs. Cosine converter. In a pre-memory scanning method performed in an inverse discrete cosine transform apparatus having two memory banks and performing inverse discrete cosine transform in an image compression decoder, (wa) setting to perform reading in the horizontal direction or the vertical direction; (wb) alternately reading from the two memory banks; (wc) checking whether a block of the pre-memory in which the read is performed corresponds to the last row; (wd) if the last row in step (wc), checks whether the row corresponds to the last column; (we) if the last row in step (wd), but is not the last column, altering the order of performing the steps; And (Wf) changing the writing direction to perform the steps (wa) to (wf); (ra) initializing to perform reading in the horizontal direction; (rb) alternately reading from two banks; (rc) checking whether the block of the pre-memory that performed the read corresponds to the last row; (rd) if the last row in step (rc), checking whether the row corresponds to the last column; (re) if the last row in step (rd) but is not the last column, changing the order of alternation to perform the steps; And and (rf) changing the read direction to perform the steps (ra) to (rf). The method of claim 7, wherein Checking whether the writing of the 51st sample has ended and branching to a reading process.

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