KR100644032B1 - CMOS Image Sensor for High Speed analog signal processing - Google Patents

Abstract

Even if you use a relatively low-speed system with a sufficient time margin to stabilize the data signal within the settling time, the analog signal is processed through multiple paths so that the overall signal processing speed of a device with millions of pixels is high. Disclosed are a method and a CMOS image sensor for eliminating the difference between offset values of the same color signal generated by processing a signal.

CMOS image sensor, analog signal processing, path, bus, offset

Description

CMOS Image Sensor for High Speed analog signal processing             

1 is a block diagram of a CMOS image sensor showing an analog signal processing path according to the prior art.

2 to 6 are schematic diagrams of a CMOS image sensor showing an analog signal processing path according to various embodiments of the present disclosure.

7 is a configuration diagram of a CMOS image sensor for explaining a decoding method according to the first embodiment in the analog signal processing path structure of FIG.

8a to 8c are views for explaining the operation of FIG.

9 is a configuration diagram of a CMOS image sensor for explaining the decoding method according to the second embodiment in the analog signal processing path structure of FIG.

Explanation of symbols on the main parts of the drawings

710: pixel array

720, 760: CDS section

730, 770: ASP section

740: 780: column driver

750, 790: selection

ADB1_L, ADB2_L: First and second lower analog data bus

ADB1_U, ADB2_U: First and Second Upper Analog Data Bus

The present invention relates to a complementary metal oxide semiconductor (CMOS) image sensor, and more particularly, to a method for processing an analog signal at high speed and a CMOS image sensor therefor.

As is well known, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Among these, a charge coupled device (CCD) includes individual MOS capacitors in close proximity to each other. A charge carrier is a device that is stored and transported in a capacitor, and a CMOS image sensor is a device that employs a switching method of constructing a pixel array using a CMOS integrated circuit fabrication technology and sequentially detecting an output thereof. CMOS image sensors have the great advantage of low power consumption, which is very useful for personal portable systems such as mobile phones.

1 is a configuration diagram of a CMOS image sensor according to the related art, and illustrates a process of processing image data (analog signals) obtained from pixels.

Referring to FIG. 1, in the image sensor according to the related art, R (Red), G (Green), and B (Blue) pixels are N in a row direction and M in a column direction. N, M are integers) and are arranged in a matrix to form the pixel array 11, and a CDS section 12 composed of one CDS (Correlated Double Sampling) circuit for each column is placed on the lower side of the pixel array section 11. Is placed. An ASP signal (Analog Signal Processor) 13 for processing an analog signal output from the CDS unit 12 is disposed on the right side of the pixel array unit 11.

The CDS circuit samples the reset signal and the data signal from each pixel and loads them on the analog data bus, and the ASP unit 13 obtains the difference between the reset signal and the data signal and amplifies them. Do it. As a result, pure pixel data of the actual subject image is obtained.

When reading the pixel data, the pixels of any row of the pixel array unit 11 are transferred to each CDS circuit of the CDS unit 12 at the same time (same clock), and the output of the CDS circuit is a column driver. Controlled by 14 is sequentially transmitted to the ASP unit 13 through the analog data bus 15 and processed.

As described above, in the conventional CMOS image sensor, when any row is selected, each pixel signal (reset signal and data signal) corresponding to the row is stored in a corresponding CDS circuit, and then a column The driver adopts a method in which signals from each CDS circuit are sequentially transferred to the ASP.

On the other hand, in the above-described conventional driving scheme and configuration, when millions of pixels are arrayed, the number of pixels in the row direction is increased, and the number of CDS circuits must be increased by that amount. The common connection also increases the load capacitance of the analog data bus.

Therefore, high speed operation is difficult with existing systems, and functional blocks (particularly ASPs) must be improved to have a desired signal processing function for high speed operation. In addition, designing a high-speed operation system has a low time margin for stabilizing signal values within the settling time, which adversely affects the reliability and mass productivity of the device.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems of the prior art, and it is possible to use the entire device of a device having millions of pixels even when using a relatively low-speed system (such as an ASP) having a sufficient time margin to stabilize the data signal within the settling time. It is an object of the present invention to provide a CMOS image sensor that enables analog signal processing to operate at high speed.

In addition, while the present invention processes signals through multiple paths to enable high-speed operation of the device even when using a relatively low speed system, each color-specific signal (i.e., the same R or G or B signal) is passed through the same path of ASP. The purpose is to provide a CMOS image sensor that solves the problem of offset by decoding to be processed in the path).

According to one aspect of the present invention, a CMOS image sensor includes: a pixel array unit in which a plurality of pixels of three colors are arranged in a matrix in a row direction and a column direction; A CDS unit configured to receive an output signal of the pixel and include one correlated double sampling (CDS) circuit for each column; A plurality of analog data buses which receive the outputs of all the CDS circuits of the CDS unit; And an analog signal processor (ASP) connected to the plurality of analog data buses.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

(First embodiment)

FIG. 2 is a configuration diagram of a CMOS image sensor according to an exemplary embodiment of the present invention, in which image data (analog signals) obtained from pixels are processed through two buses 25a and 25b extended from the prior art of FIG. 1. It is a schematic diagram showing that.

Referring to FIG. 2, in the image sensor according to the first embodiment of the present invention, N (R), G (Green), and B (Blue) pixels are arranged in a row direction in a row, and a column. The matrix is arranged in M (N, M is an integer) in the direction to form the pixel array 21, the CDS unit 22 composed of one CDS circuit for each column is placed on the lower side of the pixel array unit 21 Is placed. An ASP signal (Analog Signal Processor) 23 for processing an analog signal output from the CDS unit 22 is disposed in the right side of the pixel array unit 21. In addition, the column driver 24 receives the column address and outputs the column selection signals Cs0 and CS1... And the output signal of the CDS circuit under the control of the column selection signals CS0 and CS1... It includes a selection unit 26 for selectively transmitting to the corresponding analog data bus.

In the present embodiment, the pixel array unit 20 includes a plurality of even rows arranged by repeating G pixels and R pixels while G pixels are arranged in the first column, B pixels and B pixels being arranged in the first column. G pixels contain a plurality of odd rows arranged repeatedly.

In the present invention, the signal output from the CDS unit 22 is transmitted to the ASP unit 23 through the analog data bus, in which the analog data bus is expanded to two analog data buses, unlike the prior art of FIG. It consists of 25a and the 2nd analog data bus 25b.

The column drivers 24 and the selector 26 are output means for transmitting output signals of CDS circuits corresponding to pixels of the same color on the same row in the pixel array unit 20 to be transmitted to the same analog data bus. Is composed. That is, the output of each CDS circuit of the CDS unit 22 is controlled by the selection unit 26 controlled by the selection signal CS generated by the column driver 24. The first or second analog data buses 25a and 25b may be used. For example, when an even row is selected, the signals of B pixels (signal through the CDS circuit) are transmitted to the first analog data bus 25a, and the signals of G pixels (signal through the CDS circuit) are It is transmitted to the second analog data bus 25b. In addition, when odd rows are selected, the signals of the G pixels are transmitted to the first analog data bus 25a, and the signals of the R pixels are transmitted to the second analog data bus 25b.

As a result, when a row of the pixel array unit 20 is selected when reading the pixel data, the pixels on the row are simultaneously transferred to each CDS circuit of the corresponding CDS unit 22 (all at the same clock). Then, the output of each CDS circuit is controlled by the column driver 24 and sequentially transferred to the first or second analog data buses 25a and 25b and processed by the ASP unit 23.

As described above, the CMOS image sensor according to the first embodiment of the present invention can reduce the parasitic capacitance of the analog data bus because the analog data bus is divided even if the number of pixels increases and the number of corresponding CDS circuits increases.

That is, the load capacitance across the analog data bus is reduced by the number of bus lines. Therefore, the processing speed of the analog signal transmitted through the bus can be improved by reducing the load of the bus line, and the overall analog signal processing bandwidth can be increased.

Second Embodiment

Although the first embodiment of the present invention described above uses only one ASP pass, only the case where the analog data bus is extended to two is described. However, the analog data bus is extended to four or more while using the same ASP. As can be seen, Figure 3 shows the configuration of a CMOS image sensor according to a second embodiment of the present invention extended to four analog data buses.

Referring to FIG. 3, in the image sensor according to the second embodiment of the present invention, N (R), G (Green), and B (Blue) pixels are arranged in a row direction in a row direction, and a column. The matrix is arranged in a matrix of M pieces (N, M are integers) in the direction to form a pixel array 31, and a CDS section 32 composed of one CDS circuit for each column is placed on the lower side of the pixel array section 31. Is placed. In the right side of the pixel array unit 31, an ASP unit (Analog Signal Processor) 33 for processing an analog signal output from the CDS unit 32 is disposed.

In addition, the signal output from the CDS unit 32 is transmitted to the ASP unit 33 through the analog data bus. At this time, unlike the prior art of FIG. 1, the analog data buses are extended to four and the first analog data bus 35a. ), A second analog data bus 35b, a third analog data bus 35c, and a fourth analog data bus 35d.

The outputs of the CDS circuits of the CDS unit 32 are controlled by the selection unit 36 controlled by the selection signals CS0, CS1, CS2... Generated by the column driver 34. It is loaded on the analog data buses 35a, 35b, 35c, and 35d.

That is, when the CMOS image sensor according to the second embodiment of the present invention reads the pixel data, the pixels of any row of the pixel array unit 31 are simultaneously (same clock) the CDS unit 32 at the same time. After being transferred to each CDS circuit, the output of each CDS circuit is controlled by the column driver 34 to the ASP unit 33 sequentially through the first to fourth analog data buses 35a, 35b, 35c, and 35d. Delivered.

(Third Embodiment)

4 is a configuration diagram of a CMOS image sensor according to a third exemplary embodiment of the present invention, in which an analog signal processing path for processing analog signals output from pixels of a pixel array unit is divided into two processes. .

Referring to FIG. 4, in the image sensor according to the third embodiment of the present invention, N (R), G (Green), and B (Blue) pixels are arranged in a row direction in a row, and a column. The matrix array is arranged in M (N, M is an integer) in the direction to form a pixel array 41, the CDS section 42, 46 composed of one CDS circuit (Correlated Double Sampling) for each column is a pixel array section It is arrange | positioned at the lower end side and the upper end side of 41, respectively. In the right side of the pixel array unit 41, an ASP unit 43 for processing an analog signal output from the lower CDS unit 42 is disposed, and an analog signal output from the upper CDS unit 46 is processed. An ASP portion 47 for disposing is disposed.

The pixel array unit 710 includes a plurality of even rows arranged by repeating G pixels and R pixels while G pixels are arranged in the first column, and B pixels and G pixels are repeatedly arranged while B pixels are arranged in the first column. It includes a plurality of odd rows arranged.

The signal output from the CDS unit 42 is transmitted to the ASP unit 43 through the first analog data bus 45, and the signal output from the CDS unit 46 is ASP through the second analog data bus 49. It is passed to the unit 47.

The output of each CDS circuit of the lower CDS unit 42 is loaded on the first analog data bus 45 under the control of the selection signal CS_L generated by the first column driver 44, and the upper CDS unit ( The output of each CDS circuit of 46 is controlled by the selection signal CS_U generated by the second column driver 48 and loaded on the second analog data bus 49. Substantially, the outputs of the CDS circuits of the CDS units 42 and 46 are controlled by the column drivers 44 and 48 through the selection unit (see '26' and '36' in FIGS. 2 and 3) to control the analog data bus. As it is transmitted to (45, 49), Figure 4 shows a simplified view.

Looking at the overall operation for reading the data of the pixel, if any row of the pixel array unit 41 is selected, the output signals of all pixels corresponding to the row are the bottom and top CDS unit 42 of the corresponding column. , 46). That is, signals of the same pixel are transmitted to the lower and upper CDS units 42 and 46, respectively.

Next, the first column driver 44 sequentially drives only the CDS circuit of a column corresponding to G pixels among the lower CDS units 42 and loads it on the first analog data bus 45, and these signals are provided in the corresponding ASP unit. Is processed at 43. In addition, the second column driver 48 sequentially drives only the CDS circuits of columns corresponding to B pixels and R pixels among the upper CDS units 46 and loads them on the second analog data bus 49. Processing is performed in the ASP unit 47.

As described above, in the third embodiment of the present invention, since the signals of the R pixel / B pixel and the signals of the G pixel are processed through different analog signal processing paths, two signals can be processed simultaneously in one clock. This allows an analog system with twice the bandwidth.

In addition, since the ASP is split in two, so the role is reduced in half, each ASP can use a relatively low speed system with sufficient time margin for the data signal to stabilize within the settling time.

In addition, the present invention, while using a relatively low-speed system as described above, while processing the signal through the multi-path to enable the overall high-speed operation of the device, while the signals for each color (that is, the same R or G or B signal) is the same The problem of offset can be solved by decoding to be processed in the analog signal processing path.

That is, signals of the G pixels in the pixel array are decoded to be processed by the lower side ASP 43 through the lower side analog data bus 45, and the RB pixels are decoded by the upper side ASP 47 through the upper side analog data bus 49. By decoding to be processed in ()), it is possible to minimize the offset between the same pixels, thereby minimizing the offset noise of the image quality.

(Example 4)

The fifth embodiment of the present invention described above is a case in which a signal processing path is divided into two, and in this case, a plurality of analog data buses can be applied to each analog signal processing path. 6 shows an example of the configuration of such a CMOS image sensor.

5 shows a case where an analog signal processing path is divided into two at the upper and lower sides, and each path includes two analog data buses. This reduces the load capacitance of the analog data lines on each path, while simultaneously allowing two paths to signal at the same time.

6 shows a case in which analog signal processing paths are divided into two at the top and bottom sides, and each path includes four analog data buses. At this time, the load capacitance of the analog data line of each path is further reduced, and two paths can simultaneously process a signal at one clock.

5 and 6, the G pixel signal is processed through the lower analog signal path and the BR pixel signal is processed through the upper path, thereby minimizing offset between the same pixel signals. do.

Embodiments of the decoding method in the present invention

While the present invention processes signals through multiple paths to enable high-speed operation of the device even with a relatively low speed system, each color signal (i.e., the same R or G or B signal) is a path of the same ASP. The problem of offset is solved by decoding to be processed in. Hereinafter, a specific embodiment for decoding will be described.

7 and 9 illustrate decoding methods for a case in which an analog signal processing path is divided into two at the top and bottom sides, and each path has two analog data buses. Examples are. Ultimately, the embodiments of Figs. 7 and 9 decode the signals of the G pixels in the pixel array to be processed in the bottom side ASP via the bottom side analog data bus, and the R pixels and B pixels are top side through the top side analog data bus. Decode to be processed in ASP.

First, referring to FIG. 7, R (Red), G (Green), and B (Blue) pixels are N in a row direction and M in a column direction, where N and M are integers. Are arranged in a matrix to form a pixel array 710, and CDS units 720 and 760, each of which is composed of one CDS circuit (Correlated Double Sampling), are arranged on the lower and upper sides of the pixel array unit 710. Each is arranged. In addition, a lower ASP unit 730 for processing an analog signal output from the lower CDS unit 720, and an upper ASP unit for processing an analog signal output from the upper CDS unit 760 ( 770 is provided separately.

In the present embodiment, the pixel array unit 810 includes a plurality of even rows arranged by repeating G pixels and R pixels while G pixels are arranged in the first column, B pixels and B pixels being arranged in the first column. G pixels contain a plurality of odd rows arranged repeatedly.

In addition, the signal output from the lower side CDS unit 720 is transferred to the first and second lower analog data buses ADB1_L and ADB2_L through a transmission means composed of a lower side column driver 740 and a lower side selector 750. It is carried to the lower side ASP portion 730. The signal output from the upper side CDS unit 760 is loaded on the first and second upper analog data buses ADB1_U and ADB2_U through a transmission means consisting of the upper side column driver 780 and the upper side selection unit 790. It is transmitted to the side ASP unit 770.

The lower end selector 750 has one end connected to each CDS circuit of the lower CDS unit 720, and the other end connected to the first lower analog data bus ADB1_L or the second lower analog data bus ADB2_L. Implemented as connected switching elements, each switching element of the selector 750 is controlled by the lower column driver 740 and driven on / off.

The lower column driver 740 receives a column address ca and generates a column select signal CS1, CS2..., A column decoder 742, a driver select signal ds and a column select signal CS1. And an AND gate unit 744 for controlling each switching element of the selection unit 750 as its input and receiving its CS2...

In addition, the upper end selector 790 is connected to one CDS circuit of the upper CDS unit 760, and the other end is connected to the first upper analog data bus ADB1_U or the second upper analog data bus ADB2_U. Implemented as a connected switching element, each switching element of the selector 790 is controlled by the upper column driver 780 is driven on / off.

The upper column driver 780 receives a column address ca and generates a column selector signal CS1 and CS2..., A column decoder 782, a driver select signal ds and a column select signal CS1. And an AND gate portion 784 that controls each switching element of the selection portion 790 as its input.

The driver selection signal ds is a logic signal having opposite logic values when an even row is selected and an odd row is selected. In this embodiment, the driver selection signal ds is a logic '0'. Has a logic '1' if odd row is selected.

Let's look at the overall operation for reading the pixel's data.

When a row of the pixel array unit 710 is selected, output signals of all pixels corresponding to the row are simultaneously transmitted to the lower and upper CDS units 720 and 760 of the corresponding column, respectively. That is, signals of the same pixel are transmitted to the lower and upper CDS units 720 and 760, respectively.

Then, the column driver 740 sequentially drives only the switching elements of the column corresponding to the G pixel among the switching elements of the lower side selection unit 750, so that the first or second lower analog data buses ADB1_L and ADB2_L Alternately. These signals are processed by the corresponding ASP unit 730.

In addition, the column driver 780 sequentially drives only the switching elements of the column corresponding to the B pixel and the R pixel among the switching elements of the upper selector 790 to sequentially drive the first or second upper analog data buses ADB1_U and ADB2_U. Alternately). These signals are processed by the corresponding ASP unit 760.

8A to 8C illustrate a pixel arrangement and an operation timing diagram for describing the operation of FIG. 7. Referring to this, a detailed data processing operation of the embodiment shown in FIG. 7 will be described.

FIG. 8A shows a pixel array unit, FIG. 8B is an operation timing diagram when the driver selection signal ds is '0' (when even-numbered pixels are processed), and FIG. 8C is a driver selection signal ds. Is an operation timing diagram when '1' (when pixels of odd rows are processed).

In FIG. 8A, numbers are sequentially assigned to distinguish pixels of the same color.

First, referring to FIG. 8B, an operation of outputting data of even-numbered pixels (driver selection signal ds is '0') will be described. In the drawing, the data signal is output first and the reset signal is output, but the reset signal is output first and the data signal may be thrust.

When the column address ca is input to the column decoders 742 and 782 and the four column selection signals cs1 to cs4 are output, for example, the driver selection signal ds is '0', and thus the reverse signal 'dsb' Is '1'. As a result, the AND gates receiving the signal 'dsb' as one input output a switching signal according to the column selection signals cs1 to cs4 corresponding to the corresponding type forces. AND gates whose output switching signals may have values of '1' are A1a, A3a, A2b, and A4b.

As a result, when the column selection signal CS1 is activated, the data signal EB1_D and the reset signal EB1_R of the pixel B1 are successively loaded on the first upper analog data bus ADB1_U, and the ASP unit 770 displays these signals. By obtaining the difference value and then amplifying it, the data value of the pixel B1 is obtained. On the other hand, while the data of the pixel B1 is processed, the data signal EG2_D and the reset signal EG2_R of the pixel G2 are successively loaded on the first lower analog data bus ADB1_L, and the difference value of these signals in the ASP unit 730 is carried out. By obtaining and then amplifying, the data value of the pixel G2 is obtained. When the reset signal EB1_R of the pixel B1 is loaded on the first upper analog data bus ADB1_U, the data signal EB3_D of the pixel B3 starts to be loaded on the second upper analog data bus ADB2_U, and the reset of the pixel G2 is performed. When the signal EG2_R is loaded on the first lower analog data bus ADB1_L, the data signal EG4_D of the pixel G4 starts to be loaded on the second lower analog data bus ADB2_L.

FIG. 8C illustrates an operation of outputting data from pixels of odd rows, and performs an operation similar to that of even rows, and description thereof will be omitted.

As can be seen in the above operation, the signals of the G pixels in the pixel array are decoded to be processed in the lower side ASP via the first and second lower analog data buses, and the R or B pixels are first and second upper analog data buses. Decoded to be processed in the top side ASP via. Therefore, since the same color signal is processed in the same ASP path, it is possible to minimize the difference in offset values of the same color signal.

9 is a diagram for explaining a decoding scheme according to another embodiment of the present invention.

9, R (Red), G (Green), and B (Blue) pixels are N in a row direction and M (N, M are integers) in a column direction. The matrix array is arranged to form the pixel array 910, and CDS units 920 and 960 including one CDS circuit (Correlated Double Sampling) for each column are disposed on the lower and upper sides of the pixel array unit 710, respectively. do. Lower ASP unit 930 for processing analog signals output from the lower side CDS unit 920 and Upper ASP unit 970 for processing analog signals output from the upper side CDS unit 960. Is provided separately.

In the present exemplary embodiment, the pixel array unit 910 includes a plurality of even rows arranged by repeating G pixels and R pixels while G pixels are arranged in the first column, B pixels and G pixels contain a plurality of odd rows arranged repeatedly.

The signal output from the lower side CDS unit 920 is transferred to the lower side ASP unit 930 by being loaded on the first and second lower analog data buses ADB1_L and ADB2_L through the lower side selection unit 950. The signal output from the upper side CDS unit 960 is loaded on the first and second upper analog data buses ADB1_U and ADB2_U through the upper side selecting unit 990 and transferred to the upper side ASP unit 970.

The lower selector 950 is composed of a switching element unit 952 and a multiplexer unit 954. The switching element unit 952 has one end connected to each CDS circuit of the lower CDS unit 920 and multiplexer. The other end is connected to an input terminal of the multiplexer MUX of the unit 954 and is driven on / off by being controlled by the column select signal CS output from the column decoder 940.

Each multiplexer constituting the multiplexer 954 of the lower selector 950 is implemented as a 4-input 2-output multiplexer (MUX), and the 4-input stage is connected to the other end of the switching element of the corresponding column. One of the output terminals is connected to the first lower analog data bus ADB1_L and the other is connected to the second lower analog data bus ADB2_L. In addition, each multiplexer of the lower selector 950 is controlled by a control signal cont, and transmits two of the four inputs to the first and second lower analog data buses ADB1_L and ADB2_L. The control signal is a logic signal having opposite logic values when an even row is selected and an odd row is selected. In this embodiment, the control signal has a logic '0' when an even row is selected. Has an logic '1' if odd rows are selected.

The lower column decoder 940 receives the column address ca and generates column selection signals CS1 and CS2...

On the other hand, the upper selector 990 is composed of a switching element unit 992, a multiplexer unit 994 and an inverter 996, the switching element unit 992 is each CDS of the upper CDS unit 960 One end is connected to the circuit, the other end is connected to the input terminal of the multiplexer (MUX) of the multiplexer unit 994, it is driven on / off under the control of the column select signal (CS) output from the column decoder (980). .

Each multiplexer constituting the multiplexer section 994 of the upper selector 990 is implemented as a four input two output multiplexer (MUX), and the four input terminals are connected to the other end of the switching element of the corresponding column. One of the output terminals is connected to the first upper analog data bus ADB1_U and the other is connected to the second upper analog data bus ADB2_U. In addition, each multiplexer of the upper selector 990 is controlled by an output of the inverter 896 which receives a control signal cont and generates an inverted signal, and thus, two inputs of four inputs are input to the first and second upper analogues. Transfer to the data buses (ADB1_U, ADB2_U).

The upper column decoder 980 receives the column address ca and generates column selection signals CS1 and CS2...

Since the decoding method shown in FIG. 9 also performs the same operation as that of FIG. 7, detailed description of the operation will be omitted.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can improve the signal processing speed through a stable signal processing system by processing an analog signal through multiple paths, and in the pixel array even if the signal is processed through multiple paths. Signals for the same pixel are processed through the same path, thereby minimizing offset between the same pixels, thereby improving image quality.

Claims (28)

A pixel array unit in which a plurality of pixels of three colors are arranged in a matrix in a row direction and a column direction; A CDS unit configured to receive an output signal of the pixel and include one correlated double sampling (CDS) circuit for each column; A plurality of analog data buses which receive the outputs of all the CDS circuits of the CDS unit; And CMOS image sensor including an analog signal processor (ASP) connected to the plurality of analog data buses. The method of claim 1, A column driver that receives the column address and generates a column selection signal; And And switching means for transmitting an output signal of the CDS circuit to a corresponding analog data bus in response to the column selection signal. The method of claim 1, And transfer means for transferring an output signal of the CDS circuit corresponding to pixels of the same color on the same row in the pixel array unit to the same analog data bus. The method of claim 3, The delivery means, A column driver for receiving a column address and outputting a column selection signal; And And a selector which is controlled by the column select signal and selectively transmits the output signal of the CDS circuit to a corresponding analog data bus. The method of claim 4, wherein And the selector comprises a plurality of switching elements connected between the CDS circuit and the analog data bus. The method according to any one of claims 1 to 5, The pixel array unit, A plurality of even rows arranged with a G pixel and an R pixel repeated while G pixels are arranged in the first column; And And a plurality of odd rows in which B pixels and G pixels are arranged repeatedly while B pixels are arranged in a first column. A pixel array unit in which a plurality of R pixels, a plurality of G pixels, and a plurality of B pixels are matrix-arranged in a row and column direction; A first analog signal processing path disposed at one side of the pixel array unit for processing analog signals outputted from G pixels in the pixel array unit; And A second analog signal processing path disposed on the other side of the pixel array unit to process analog signals output from a B pixel or an R pixel in the pixel array unit; CMOS image sensor comprising a. The method of claim 7, wherein The first analog signal processing path is A lower CDS unit disposed below the pixel array unit to form one CDS circuit for each column, and receiving output signals of all pixels of the selected row to the corresponding CDS circuit at once; At least one lower analog data bus which receives only an output for a CDS circuit corresponding to a G pixel among all the CDS circuits of the lower CDS unit; And Lower ASP connected to the lower analog data bus CMOS image sensor comprising a. The method of claim 8, The second analog signal processing path is An upper CDS unit disposed on the pixel array unit to form one CDS circuit for each column, and receiving output signals of all pixels of the selected row into the corresponding CDS circuit at once; At least one upper analog data bus for receiving only outputs for CDS circuits corresponding to R pixels or B pixels among the entire CDS circuits of the upper CDS unit; And Upper ASP connected to the upper analog data bus CMOS image sensor comprising a. The method of claim 8, The first analog signal processing path is A first column driver for generating a first switching signal for transmitting only outputs of a CDS circuit corresponding to a G pixel among the entire CDS circuits of the lower CDS unit to the lower analog data bus; And A lower selector which is controlled by the first switching signal and selectively transmits an output signal of the CDS circuit to the lower analog data bus CMOS image sensor further comprises. The method of claim 9, The second analog signal processing path is A second column driver generating a second switching signal for transmitting only an output of a CDS circuit corresponding to an R pixel or a B pixel among the entire CDS circuits of the upper CDS unit to the upper analog data bus; And An upper selector configured to selectively transfer an output signal of the CDS circuit to the upper analog data bus under the control of the second switching signal; CMOS image sensor comprising a. The method of claim 10, And the lower selector comprises a plurality of switching elements connected between each CDS circuit and the lower analog data bus of the lower CDS unit. The method of claim 11, And the upper selector comprises a plurality of switching elements connected between each CDS circuit of the upper CDS unit and the upper analog data bus. The method of claim 10, The first column driver, A first column decoder configured to receive a column address and generate a first column selection signal; And And a first AND gate part receiving a control signal having information about odd or even rows and the first column selection signal and outputting a plurality of switching signals for each column as the first switching signal. . The method of claim 11, The second column driver, A second column decoder configured to receive a column address and generate a second column selection signal; And And a second AND gate part receiving a control signal having information about odd or even rows and the first column selection signal and outputting a plurality of switching signals for each column as the second switching signal. . The method of claim 8, The first analog signal processing path is A first column decoder configured to generate a first column selection signal for transmitting only an output of a CDS circuit corresponding to a G pixel among the entire CDS circuits of the lower CDS unit to the lower analog data bus; And A lower selector which is controlled by the first column select signal and selectively transmits an output signal of the CDS circuit to the lower analog data bus CMOS image sensor further comprises. The method of claim 9, The second analog signal processing path is A second column decoder configured to generate a second column selection signal for transmitting only an output of a CDS circuit corresponding to an R pixel or a B pixel among the entire CDS circuits of the upper CDS unit to the upper analog data bus; And An upper selector which is controlled by the second column select signal and selectively transmits an output signal of the CDS circuit to the upper analog data bus CMOS image sensor further comprises. The method of claim 16, The lower selection unit, A switching element driven under the control of the first column selection signal and selectively transferring each output signal of the lower CDS unit; And A multiplexer which is controlled by a control signal having information about an odd number or an even number and selectively transmits at least one signal of each output signal of the lower CDS unit to the lower analog data bus. CMOS image sensor comprising a. The method of claim 17, The upper selection unit, A plurality of switching elements which are driven under the control of the second column selection signal and selectively transmit each output signal of the upper CDS unit; And A plurality of multiplexers which are controlled by a control signal having information about odd or even rows and selectively transmits at least one signal of each output signal of the upper CDS unit to the upper analog data bus CMOS image sensor comprising a. A pixel array unit in which a plurality of pixels of three colors are arranged in a matrix in a row direction and a column direction; A lower CDS unit disposed below the pixel array unit to receive an output signal of the pixel and configured as one CDS circuit for each column; An upper CDS unit disposed on the pixel array unit to receive an output signal of the pixel and configured as one CDS circuit for each column; A plurality of lower analog data buses which receive the outputs of the entire CDS circuits of the first CDS unit; A plurality of upper analog data buses which receive the outputs of the entire CDS circuits of the second CDS unit; A lower ASP connected to the plurality of lower analog data buses; And An upper ASP connected to the plurality of upper analog data buses CMOS image sensor comprising a. The method of claim 20, First transfer means for dividing and transmitting the signals output from the respective CDS circuits of the lower CDS unit to the first and second lower analog data buses; And And second transmission means for dividing and transmitting the signals output from the respective CDS circuits of the upper CDS unit to the first and second upper analog data buses. The method of claim 21, The pixel array unit, A plurality of even rows arranged with a G pixel and an R pixel repeated while G pixels are arranged in the first column; And And a plurality of odd rows in which B pixels and G pixels are arranged repeatedly while B pixels are arranged in a first column. The method of claim 22, The plurality of lower analog data buses receive only the outputs of the CDS circuits corresponding to the G pixels among the entire CDS circuits of the lower CDS unit through the first transfer means, And the plurality of upper analog data buses receives only the outputs of CDS circuits corresponding to R pixels or B pixels from the entire CDS circuits of the upper CDS unit through the second transfer means. The method of claim 22, And the lower analog data bus comprises first and second lower analog data buses, and the plurality of upper analog data buses comprises first and second upper analog data buses. The method of claim 24, The first transfer means generates a first switching signal for transmitting only outputs of the CDS circuits corresponding to the G pixels among the entire CDS circuits of the lower CDS unit to the first and second lower analog data buses. And a lower selector for controlling a first switching signal and selectively transmitting an output signal of the CDS circuit to the first and second lower analog data buses. The second transfer means is configured to generate a second switching signal for transmitting only the output of the CDS circuit corresponding to the R pixel or the B pixel of the upper CDS unit to the first and second upper analog data buses. A lower selector for selectively transmitting a two-column driver and an output signal of the CDS circuit to the first and second upper analog data buses under the control of the second switching signal; CMOS image sensor comprising a. The method of claim 25, The lower selector includes a plurality of first switching elements connected between each CDS circuit of the lower CDS unit and the first and second lower analog data buses; And the upper selector comprises a plurality of second switching elements connected between each CDS circuit of the upper CDS unit and the upper analog data bus. The method of claim 25, The first column driver may include a first column decoder configured to receive a column address and generate a first column selection signal, a control signal having information about an odd row or an even row, and the first column selection signal for each column. A first AND gate part configured to output a plurality of switching signals as the first switching signal, The second column driver may include a second column decoder configured to receive a column address and generate a second column selection signal, a control signal having information about odd or even rows, and the first column selection signal for each column. And a second AND gate portion for outputting a plurality of switching signals as the second switching signal. The method of claim 24, The first transfer means generates a first column for generating a first column selection signal for transmitting only the output of the CDS circuit corresponding to the G pixel among the entire CDS circuits of the lower CDS unit to the first and second lower analog data buses. Controlled by a decoder, a plurality of first switching elements for selectively driving each output signal of the lower CDS unit, and controlled by a control signal having information about odd or even rows; A plurality of first multiplexers for selectively transmitting each output signal of the lower CDS unit to the first and second lower analog data buses, The second transfer means generates a second column selection signal for transferring only outputs of the CDS circuits corresponding to the R pixels or the B pixels among the entire CDS circuits of the upper CDS unit to the first and second upper analog data buses. A second column decoder, a plurality of second switching elements that are driven under the control of the second column selection signal, and selectively transmit each output signal of the lower CDS unit, and a control signal having information about odd or even rows. And a plurality of second multiplexers which are controlled to selectively transmit respective output signals of the upper CDS unit to the first and second upper analog data buses.

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