KR100631920B1 - Method for fabricating insalating film of semiconductor device - Google Patents

Method for fabricating insalating film of semiconductor device Download PDF

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KR100631920B1
KR100631920B1 KR1020000073192A KR20000073192A KR100631920B1 KR 100631920 B1 KR100631920 B1 KR 100631920B1 KR 1020000073192 A KR1020000073192 A KR 1020000073192A KR 20000073192 A KR20000073192 A KR 20000073192A KR 100631920 B1 KR100631920 B1 KR 100631920B1
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insulating film
barrier layer
film
plate electrode
forming
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정우찬
이승무
전진호
최병덕
임전식
이종승
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삼성전자주식회사
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment

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Abstract

커패시터와 메탈라인 사이에 BPSG 재질의 절연막 증착시, 다이버트 시간을 MFC가 안정될 때까지 충분히 늘리고, 플레이트 전극과 상기 절연막 사이에 B,P 소스의 아웃-디퓨전을 방지할 수 있는 장벽층을 더 추가하므로써, 플레이트 전극의 RS 증가를 막을 수 있도록 한 반도체 소자의 절연막 형성방법이 개시된다. When depositing a BPSG insulating film between the capacitor and the metal line, the divert time is sufficiently increased until the MFC is stabilized, and a barrier layer is further provided between the plate electrode and the insulating film to prevent out-diffusion of the B and P sources. In addition, a method of forming an insulating film of a semiconductor element is disclosed which prevents an increase in RS of a plate electrode.

이를 위하여 본 발명에서는, "스토리지 전극-유전막-플레이트 전극" 구조의 커패시터가 갖는 절연기판을 준비하는 단계; 상기 결과물 상에 유동성을 갖지 않는 절연 재질의 장벽층을 형성하는 단계; 및 B-소스 가스와 P-소스 가스를 10 ~ 15초 동안 다이버트하여 개스 플로우를 안정화시킨 후, SACVD 프로세스를 적용하여 상기 장벽층 상에 BPSG 재질의 절연막을 형성하는 단계를 포함하는 반도체 소자의 절연막 형성방법이 제공된다. To this end, the present invention comprises the steps of preparing an insulating substrate of the capacitor of the "storage electrode-dielectric film-plate electrode" structure; Forming a barrier layer of an insulating material having no fluidity on the resultant; And diverting the B-source gas and the P-source gas for 10 to 15 seconds to stabilize the gas flow, and then applying an SACVD process to form an insulating film made of BPSG material on the barrier layer. A method of forming an insulating film is provided.

Description

반도체 소자의 절연막 형성방법{Method for fabricating insalating film of semiconductor device} A method for forming an insulating film of a semiconductor device {Method for fabricating insalating film of semiconductor device}                              

도 1a 및 도 1b는 종래 기술로서, 커패시터가 구비된 절연기판 상에 절연막을 형성하는 방법을 보인 공정순서도, 1A and 1B are a prior art, process flowchart showing a method of forming an insulating film on an insulating substrate provided with a capacitor;

도 2a 및 도 2b는 본 발명으로서, 커패시터가 구비된 절연기판 상에 절연막을 형성하는 방법을 보인 공정순서도, 2A and 2B are process flowcharts showing a method of forming an insulating film on an insulating substrate provided with a capacitor according to the present invention;

도 3은 장벽층인 USG막 사용 전·후의 플레이트 전극의 시트 저항(sheet resistance:RS) 변화를 나타낸 그래프이다.
3 is a graph showing sheet resistance (RS) change of a plate electrode before and after using a USG film as a barrier layer.

본 발명은 반도체 소자의 절연막 형성방법에 관한 것으로, 특히 플레이트 전극의 시트 저항(이하, RS라 한다) 증가를 막을 수 있는 커패시터와 메탈라인 간의 절연막 형성방법에 관한 것이다. The present invention relates to a method for forming an insulating film of a semiconductor device, and more particularly, to a method for forming an insulating film between a capacitor and a metal line that can prevent an increase in sheet resistance (hereinafter, referred to as RS) of a plate electrode.                         

반도체 제품의 고집적화가 진행됨에 따라 커패시터, 메탈라인 등의 전기적 특성외에 이들간을 절연하는 막질의 절연 특성 또한 그 중요성이 점점 크게 부각되고 있다. 이는 하급 소자에서는 절연 막질이 커패시터 등에 미치는 영향이 소자 특성에 거의 영향을 미치치 않을 정도로 미미하였으나 디자인 룰이 미세해지면서 미미한 열역학적 반응에 의해서도 소자가 치명적인 손상을 받는 현상이 야기되기 때문이다. As semiconductor products have been highly integrated, the importance of the insulating properties of the film to insulate them apart from the electrical properties of capacitors, metal lines, and the like has become increasingly important. This is because, in lower devices, the influence of the insulating film quality on the capacitors and the like has little effect on the device characteristics. However, as the design rules become finer, the device may be fatally damaged by the slight thermodynamic reaction.

이를 도 1a 및 도 1b에 제시된 종래의 절연막 형성방법을 보인 공정순서도를 참조하여 살펴보면 다음과 같다. 상기 공정수순도는 커패시터가 구비된 절연기판 상에 절연막을 형성하는 방법을 보인 것으로, 여기서는 편의상 상기 공정을 제 2 단계로 구분하여 설명한다. This will be described with reference to the process flow chart showing the conventional insulating film forming method shown in Figures 1a and 1b as follows. The process purity shows a method of forming an insulating film on an insulating substrate provided with a capacitor. For convenience, the process will be described by dividing the process into a second step.

제 1 단계로서, 도 1a와 같이 폴리실리콘 재질의 스토리지 전극(20)이 구비된 절연기판(10) 상에, 상기 스토리지 전극(20)의 표면을 둘러싸는 유전막(30)을 형성한 후, 상기 유전막(30)을 포함한 절연기판(10) 상의 소정 부분에 폴리실리콘 재질의 플레이트 전극(40)을 형성한다. 그 결과, "스토리지 전극(20)-유전막(30)-플레이트 전극(40)" 구조의 커패시터가 완성된다. As a first step, after forming the dielectric film 30 surrounding the surface of the storage electrode 20 on the insulating substrate 10 with the polysilicon storage electrode 20, as shown in Figure 1a, A polysilicon plate electrode 40 is formed on a predetermined portion on the insulating substrate 10 including the dielectric film 30. As a result, a capacitor having a structure of "storage electrode 20-dielectric film 30-plate electrode 40" is completed.

제 2 단계로서, 도 1b와 같이 P-소스 가스와 B-소스 가스를 3초 동안 다이버트(divert)(혹은 bypass)시킨 후, 막질 증착용 챔버 내에서 SACVD(Semi-Atomospheric Chemical Vapor Deposition) 프로세스를 적용하여 상기 결과물 상에 BPSG(BoroPhospho Silicate Glass) 재질의 절연막(50)을 증착하고, 열처리 공정에 통해 상기 절연막(40)을 평탄화하므로써, 본 공정 진행을 완료한다. 이와같이 절연 막으로 유동성(flowable)을 갖는 BPSG가 이용되는 것은 디램 소자의 경우 구조적인 특성상 커패시터가 있는 셀(cell) 부위와 커패시터가 없는 페리(peri) 부분간의 단차 차이가 통상 15000~23000Å 정도 벌어지므로, 유동성을 갖는 막질이 그렇지 못한 막질에 비해 우수한 평탄화 특성을 확보할 수 있기 때문이다. 여기서, SACVD 프로세스란 대기압보다는 낮지만 저압 공정인 CVD 프로세스보다는 높은 압력하에서 막질 증착이 이루어지는 공정(일명, 고압 공정이라 한다)을 일컫는다. As a second step, as shown in FIG. 1B, the P-source gas and the B-source gas are diverted (or bypassed) for 3 seconds, followed by a semi-atomicpheric chemical vapor deposition (SACVD) process in a film deposition chamber. Is applied to deposit an insulating film 50 made of BPSG (BoroPhospho Silicate Glass) on the resultant, and planarizes the insulating film 40 by a heat treatment process, thereby completing the process. As such, the BPSG having flowable as an insulating film is used in the DRAM device because the difference in step between the cell part with the capacitor and the peri part without the capacitor is generally about 15000 to 23000 Å due to the structural characteristics. This is because the film quality having fluidity can secure excellent planarization characteristics compared to the film quality which is not. Here, the SACVD process refers to a process (hereinafter, referred to as a high pressure process) in which film deposition is performed under a higher pressure than a CVD process which is lower than atmospheric pressure but low pressure process.

하지만 상기 공정 기법에 의거하여 커패시터와 메탈라인 간의 절연막을 형성하면 소자 제조시 다음과 같은 몇가지의 문제가 발생된다. However, if the insulating film is formed between the capacitor and the metal line based on the above process technique, several problems occur in manufacturing the device.

BPSG 재질의 절연막(50) 내에 포함되어 있는 B와 P 도판트가 후속 공정(평탄화를 위한 열처리 공정)을 거치면서 아웃-디퓨전(out-diffusion)되는 성질이 있기 때문에, 커패시터 방향으로 아웃-디퓨전되는 B와 P 도판트가 플레이트 전극의 RS를 증가시켜 소자에 심한 손상(damage)를 입히는 문제가 발생된다. Since the B and P dopants included in the insulating film 50 made of BPSG are out-diffused during the subsequent process (heat treatment process for leveling), they are out-diffused toward the capacitor. The problem is that the B and P dopants increase the RS of the plate electrode, causing severe damage to the device.

뿐만 아니라 이 경우는 B-소스 가스와 P-소스 가스를 3초 동안 다이버트한 후에 메인(main) BPSG 막질 증착이 이루어지는 방식으로 공정이 진행되는데, 3초간의 다이버트 시간을 거쳐서는 가스 플로우를 안정화시킬 수 없어, MFC(Mass Flow Controller)가 안정화되지 않은 상태에서 챔버 내로 가스가 플로우되게 되고, 이로 인해 플레이트 전극(40) 바로 위에 증착되는 BPSG 막질이 열역학적으로 불안정한 상태가 되는 현상이 야기된다. In addition, in this case, the process proceeds in such a way that the main BPSG film deposition is performed after diverting the B-source gas and the P-source gas for 3 seconds. Inability to stabilize, gas flows into the chamber in a state where the Mass Flow Controller (MFC) is not stabilized, which causes a phenomenon in which the BPSG film deposited on the plate electrode 40 becomes thermodynamically unstable.

이러한 현상은 후속 열처리 공정에서 B,P 도판트의 아웃-디퓨전을 더욱 가속화시켜 RS를 증가시키는 촉진제 역할을 하게 되므로, 현재 이에 대한 개선책이 시 급하게 요구되고 있다.
This phenomenon is to accelerate the out-diffusion of the B, P dopant in the subsequent heat treatment process to act as an accelerator to increase the RS, the improvement is currently urgently required.

따라서 본 발명의 목적은 커패시터와 메탈라인 사이에 BPSG 재질의 절연막 증착시, 다이버트 시간을 MFC가 안정될 때까지 충분히 늘리고, 플레이트 전극과 상기 절연막 사이에 B,P 소스의 아웃-디퓨전을 방지할 수 있는 장벽층을 더 추가하므로써, 플레이트 전극의 RS 증가를 막을 수 있도록 한 반도체 소자의 절연막 형성방법을 제공함에 있다.
Accordingly, an object of the present invention is to sufficiently increase the divert time until the MFC is stabilized when depositing an insulating film of BPSG material between the capacitor and the metal line, and to prevent out-diffusion of the B and P sources between the plate electrode and the insulating film. The present invention provides a method of forming an insulating film of a semiconductor device by adding a barrier layer capable of preventing the increase of the RS of the plate electrode.

상기 목적을 달성하기 위하여 본 발명에서는 "스토리지 전극-유전막-플레이트 전극" 구조의 커패시터가 갖는 절연기판을 준비하는 단계; 상기 결과물 상에 유동성을 갖지 않는 절연 재질의 장벽층을 형성하는 단계; 및 B-소스 가스와 P-소스 가스를 10 ~ 15초 동안 다이버트하여 개스 플로우를 안정화시킨 후, SACVD 프로세스를 적용하여 상기 장벽층 상에 BPSG 재질의 절연막을 형성하는 단계를 포함하는 반도체 소자의 절연막 형성방법이 제공된다. In order to achieve the above object, the present invention includes the steps of preparing an insulating substrate of the capacitor of the "storage electrode-dielectric film-plate electrode" structure; Forming a barrier layer of an insulating material having no fluidity on the resultant; And diverting the B-source gas and the P-source gas for 10 to 15 seconds to stabilize the gas flow, and then applying an SACVD process to form an insulating film made of BPSG material on the barrier layer. A method of forming an insulating film is provided.

이때, 상기 장벽층은 20 ~ 150Å 두께의 USG 재질로 형성하는 것이 바람직하다. In this case, the barrier layer is preferably formed of a USG material of 20 ~ 150Å thickness.

상기와 같이 커패시터와 메탈라인 간의 절연막을 형성할 경우, 플레이트 전극과 BPSG 막질 사이에 USG 재질의 장벽층이 추가되고, 아울러 B-소스 가스와 P-소 스 가스의 다이버트 시간을 MFC가 안정될 때까지 충분히 늘린 상태에서 메인 BPSG 막질 증착이 이루어지도록 공정이 진행되므로, 후속 열처리시 B,P 도판트가 커패시터 방향(특히, 플레이트 전극)으로 아웃-디퓨전되는 것을 막을 수 있게 된다. In the case of forming the insulating film between the capacitor and the metal line as described above, a barrier layer made of USG material is added between the plate electrode and the BPSG film quality, and the divergence time of the B-source gas and the P-source gas is stabilized. Since the process proceeds to the main BPSG film deposition in a fully stretched state until, it is possible to prevent the B, P dopant out-diffusion in the direction of the capacitor (especially plate electrode) during the subsequent heat treatment.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명한다. Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 2a 및 도 2b는 본 발명에서 제안된 반도체 소자의 절연막 형성방법을 보인 공정순서도로서, 이를 참조하여 그 제조방법을 제 2 단계로 구분하여 설명하면 다음과 같다. 이 경우 역시, 커패시터가 구비된 절연기판 상에 절연막을 형성하는 방법에 대하여 살펴본다.2A and 2B are flowcharts illustrating a method of forming an insulating layer of a semiconductor device according to the present invention. Referring to this, the manufacturing method is divided into second steps and described as follows. In this case, a method of forming an insulating film on an insulating substrate provided with a capacitor will be described.

제 1 단계로서, 도 2a와 같이 폴리실리콘 재질의 스토리지 전극(20)이 구비된 절연기판(10) 상에, 상기 스토리지 전극(20)의 표면을 둘러싸는 유전막(30)을 형성한 후, 상기 유전막(30)을 포함한 절연기판(10) 상의 소정 부분에 폴리실리콘 재질의 플레이트 전극(40)을 형성한다. 그 결과, "스토리지 전극(20)-유전막(30)-플레이트 전극(40)" 구조의 커패시터가 완성된다. As a first step, after forming the dielectric film 30 surrounding the surface of the storage electrode 20 on the insulating substrate 10 provided with a polysilicon storage electrode 20, as shown in Figure 2a, A polysilicon plate electrode 40 is formed on a predetermined portion on the insulating substrate 10 including the dielectric film 30. As a result, a capacitor having a structure of "storage electrode 20-dielectric film 30-plate electrode 40" is completed.

제 2 단계로서, 도 2b와 같이 상기 커패시터를 포함한 절연기판(10) 상에 유동성이 없는 절연 재질(예컨대, USG) 재질의 장벽층(45)을 2.5 ~ 4.5초간 20 ~ 150Å의 두께로 형성한다. 이와같이 커패시터와 이후 형성될 BPSG 막질 간에 장벽층(45)을 별도 더 형성한 것은 후속 열처리시 상기 절연 막질 내에 포함된 B,P 도판트가 커패시터의 플레이트 전극(40)쪽으로 아웃-디퓨전되는 것을 막기 위함이다. 이어, P-소스 가스와 B-소스 가스를 10 ~ 15 동안 다이버트(혹은 bypass)시켜 가스 플로우를 안정화한 후, 막질 증착용 챔버 내에서 SACVD 프로세스를 적용하여 상기 장벽층(45) 상에 BPSG 재질의 절연막(50)을 증착하고, 열처리 공정에 통해 상기 절연막(40)을 평탄화하므로써, 본 공정 진행을 완료한다. P-소스 가스와 B-소스 가스의 다이버트 시간을 상기와 같이 늘려준 것은 MFC가 안정된 상태에서 메인 BPSG 막질 증착이 이루어지도록 하여, 장벽층(45) 바로 위에 증착되는 BPSG 막질이 열역학적으로 불안정한 상태에 놓여지는 것을 막기 위함이다. As a second step, as shown in FIG. 2B, a barrier layer 45 made of a non-flowable insulating material (eg, USG) material is formed on the insulating substrate 10 including the capacitor to a thickness of 20 to 150 μs for 2.5 to 4.5 seconds. . The additional formation of the barrier layer 45 between the capacitor and the BPSG film to be formed later is to prevent the B and P dopants contained in the insulating film from being out-diffused toward the plate electrode 40 of the capacitor during the subsequent heat treatment. to be. Subsequently, the gas flow is stabilized by diverting (or bypassing) the P-source gas and the B-source gas for 10 to 15, and then applying a SACVD process in the film deposition chamber to apply the BPSG on the barrier layer 45. The process of this process is completed by depositing the insulating film 50 of a material and planarizing the said insulating film 40 by a heat processing process. Increasing the divert time of the P-source gas and the B-source gas as described above causes the main BPSG film deposition to be performed while the MFC is stable, so that the BPSG film deposited on the barrier layer 45 is thermodynamically unstable. This is to prevent it from being put on.

이와같이 공정을 진행할 경우, B-소스 가스와 P-소스 가스의 다이버트 시간이 기존의 3초에서 10 ~ 15초로 늘어나므로, BPSG 재질의 절연막 증착시 MFC를 안정화시킬 수 있게 되고, 이로 인해 플레이트 전극(40)과의 계면에 열역학적으로 안정된 BPSG 막질을 증착할 수 있게 된다. 뿐만 아니라 USG 재질의 장벽층(45)을 이용하여 절연막(50) 내의 P, B 도판트가 후속 열처리 과정에서 플레이트 전극(40)쪽으로 아웃-디퓨전되는 것을 방지할 수 있게 된다. 그 결과, 상기 도판트들의 아웃-디퓨전에 의해 야기되던 플레이트 전극의 RS 증가를 막을 수 있게 되는 것이다. In this case, the divergence time of the B-source gas and the P-source gas is increased to 10 to 15 seconds from the existing 3 seconds, thereby stabilizing the MFC during the deposition of the insulating film of the BPSG material, and thus the plate electrode. It is possible to deposit a thermodynamically stable BPSG film at the interface with (40). In addition, the barrier layer 45 made of USG may be used to prevent P and B dopants in the insulating layer 50 from being out-diffused toward the plate electrode 40 in a subsequent heat treatment process. As a result, it is possible to prevent the RS increase of the plate electrode caused by the out-diffusion of the dopants.

도 3에는 이를 확인하기 위한 일 실험 예로서, USG 재질의 장벽층(45) 사용 전·후의 플레이트 전극의 RS 변화를 보인 그래프가 제시되어 있다. 상기 그래프에서 가로축은 날짜(date)를 나타내고, 세로축은 플레이트 전극의 RS를 나타낸다. 3 shows a graph showing the RS change of the plate electrode before and after using the barrier layer 45 made of USG as an experimental example to confirm this. In the graph, the horizontal axis represents the date and the vertical axis represents the RS of the plate electrode.

상기 그래프에 의하면, 장벽층(45) 사용전보다 사용후에 플레이트 전극(40)의 RS 산포가 전체적으로 낮아지는 경향을 보임을 확인할 수 있다.
According to the graph, it can be seen that the RS distribution of the plate electrode 40 tends to be lowered overall after use than before the barrier layer 45 is used.

이상에서 살펴본 바와 같이 본 발명에 의하면, 1) B-소스 가스와 P-소스 가스의 다이버트 시간을 MFC가 안정될 때까지 충분히 늘려주므로써, 플레이트 전극과의 계면에 안정된 BPSG 막질을 증착할 수 있게 되고, 2) 플레이트 전극과 BPSG 막질 사이에 USG 재질의 장벽층을 더 추가하므로써, 후속 열처리 과정에서 BPSG 막질 내의 B,P 도판트가 커패시터의 플레이트 전극쪽으로 아웃-디퓨전되는 것을 막을 수 있게 되므로, 기존대비 플레이트 전극의 RS를 낮출 수 있게 된다.






As described above, according to the present invention, 1) by sufficiently increasing the diver time of the B-source gas and the P-source gas until the MFC is stabilized, it is possible to deposit a stable BPSG film at the interface with the plate electrode 2) By further adding a USG barrier layer between the plate electrode and the BPSG film, it is possible to prevent the B, P dopant in the BPSG film to be out-diffused to the plate electrode of the capacitor during the subsequent heat treatment. It is possible to lower the RS of the contrast plate electrode.






Claims (4)

"스토리지 전극-유전막-플레이트 전극" 구조의 커패시터가 갖는 절연기판을 준비하는 단계; Preparing an insulating substrate of a capacitor having a "storage electrode-dielectric film-plate electrode" structure; 상기 결과물 상에 유동성을 갖지 않는 절연 재질의 장벽층을 형성하는 단계; 및 Forming a barrier layer of an insulating material having no fluidity on the resultant; And B-소스 가스와 P-소스 가스를 10 ~ 15초 동안 다이버트하여 가스 플로우를 안정화시킨 후, SACVD 프로세스를 적용하여 상기 장벽층 상에 BPSG 재질의 절연막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 절연막 형성방법.Diverting the B-source gas and the P-source gas for 10-15 seconds to stabilize the gas flow, and then applying an SACVD process to form an insulating film of BPSG material on the barrier layer. A method of forming an insulating film of a semiconductor device. 제 1항에 있어서, 상기 장벽층은 20 ~ 150Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 절연막 형성방법. The method of claim 1, wherein the barrier layer is formed to a thickness of 20 to 150 kPa. 제 1항에 있어서, 상기 장벽층은 USG 재질로 형성하는 것을 특징으로 하는 반도체 소자의 절연막 형성방법. The method of claim 1, wherein the barrier layer is formed of a USG material. 제 1항에 있어서, 상기 장벽층은 2.5 ~ 4.5초의 시간 범위 내에서 형성하는 것을 특징으로 하는 반도체 소자의 절연막 형성방법. The method of claim 1, wherein the barrier layer is formed within a time range of 2.5 to 4.5 seconds.
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