KR100617129B1 - Digital Multimedia Broadcasting Receiver with Forward Error Correction - Google Patents

Abstract

The present invention is to reduce the chip area by sharing the RS decoder of the forward error correction encoder in the digital multimedia broadcasting receiver, time-deinterleaving for all channels to be decoded among the received channels, Viterbi decoding and byte de-interleaving A serialization block for sequentially transmitting the bytes deinterleaved and transmitted in parallel as one channel for each packet; An RS decoder for correcting errors in channels that have passed through the serialization block; Provided is a digital multimedia broadcasting receiver including a forward error correction encoder configured to include a byte-to-bit converter for converting an error-corrected channel from a byte unit to a bit unit through the RS decoder.

Therefore, according to the present invention, an RS decoder can be shared regardless of the number of channels to efficiently use resources and reduce chip area.

Forward Error Correction Coder, Serialization Block, RS Decoder, Byte / Bit Converter

Description

Digital multimedia broadcasting receiver with forward error correction encoder {Digital Multimedia Broadcasting Receiver with Forward Error Correction}

1 is a diagram illustrating a structure of a forward error correction coding unit and an interface with A / V according to the related art.

2 is a diagram illustrating a structure of a forward error correction coding unit and an interface with A / V according to the present invention.

3 is a view showing the shape of the signal for the interface with the A / V according to the present invention

4 is a block diagram showing a conceptual configuration of a digital multimedia broadcasting receiver including the present invention.

* Explanation of symbols for the main parts of the drawings

100: forward error correction encoder 110: time inverse interleaver

120: Viterbi decoder 130: byte reverse interleaver

135: serialization block 140: RS decoder

145: Byte / Bit Converter

The present invention relates to a forward error correction encoder in a digital multimedia broadcasting receiver, and more particularly, to a shared structure of an RS decoder of a forward error correction encoder.

Digital multimedia broadcasting can be classified into terrestrial digital multimedia broadcasting and satellite digital multimedia broadcasting.

Terrestrial digital multimedia broadcasting is based on Orthogonal Frequency Division Multiplexing (OFDM), which provides audio and video services while moving, and satellite digital multimedia broadcasting is a CDM (Code Division). Multiplexing: Based on Code Division Multiplexing (CDM)), a satellite and ground gap filler, which is used as a repeater, is used to solve the shadow area that does not receive radio waves directly from the satellite. will be.

At present, the technology of satellite digital multimedia broadcasting basically adopts CDM transmission method, and is a new concept service of communication and broadcasting convergence, which broadcasts weather, traffic, video information using CD (Compact Disk) level sound quality and various channels.

Of these digital multimedia broadcastings, the satellite digital multimedia broadcasting has a broad coverage as a national broadcasting, but the transmission channel is a wireless mobile receiving channel, and the size of the received signal is not only time-varying, but also due to the influence of mobile receiving. Doppler shift of the received signal spectrum occurs.

In consideration of the transmission and reception in such a channel environment, the satellite digital multimedia broadcasting transmission method adopts the CDM method, and interleaves the time domain signals to correct errors occurring in the transmission channel.

1 illustrates a structure of a conventional forward error correction encoder and an interface with A / V. The forward error correction encoder 10 includes a time inverse interleaver 20, a Viterbi decoder 30, and a byte inverse interleaver 40. ), An RS decoder 50, and a formatter 60.

The time reverse interleaver 20 performs reverse interleaving on the received channel in the time domain.

The Viterbi decoder 30 Viterbi decodes the time deinterleaved signal for each channel.

The byte deinterleaver 40 deinterleaves each of the Viterbi-decoded channels in byte units.

The RS decoder 50 corrects a clustering error of each channel decoded in the byte unit.

The formatter 60 maintains a constant channel order of several parallel channels for interfacing with the A / V data decoder, and serially connects them in packet units and signals processed in bytes. Converts to.

However, the structure of the conventional forward error correction coding unit described above is composed of one chip, which requires an RS decoder by the number of channels, and when the number of channels is increased later, the number of RS decoders is increased so that resources are inefficiently used. There is a problem in that the chip area increases even when used, and implemented as a chip.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an object of efficiently using resources and reducing chip area by sharing an RS decoder regardless of the number of channels.

In order to achieve the above object, the present invention performs time deinterleaving for all channels to be decoded among the various channels received, performs Viterbi decoding and byte deinterleaving, and then transmits the packets deinterleaved and transmitted in parallel. A serialization block for sequentially transmitting one channel for each channel; An RS decoder for correcting errors in channels that have passed through the serialization block; Provided is a digital multimedia broadcasting receiver including a forward error correction encoder configured to include a byte-to-bit converter for converting an error-corrected channel from a byte unit to a bit unit through the RS decoder.

The serialization block performs processing so that each channel can be sequentially transmitted in consideration of the interface with the A / V data decoder, rather than performing the data in the order in which the data comes.

The order of the transmitted channels is characterized in that each channel can be sequentially transmitted without two channels being transmitted in succession.

The clock is used as many times as many times as the number of channels than the Viterbi decoder and the byte deinterleaver so that each channel can be sequentially transmitted.

The RS decoder has a structure in which the serialization block is located in front of the RS decoder and the byte / bit converter is located in the rear end of the RS decoder to share the RS decoder.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described.

The same components as in the prior art are given the same names and the same reference numerals for convenience of description, and detailed description thereof will be omitted.

Referring to the accompanying drawings, FIG. 2 is a diagram illustrating a structure of a forward error correction coding unit and an interface with A / V. The time deinterleaver 110 and the Viterbi decoder Viterbi. decoder 120, byte deinterleaver 130, serialization block 135, RS decoder (Reed-Solomon decoder) 140, byte / bit converter ( 145).

The time reverse interleaver 110 performs reverse interleaving on a bit basis at the receiving end to interleave bit by bit at the transmitting end so as to correct an error that may occur in the transmission process.

The Viterbi decoder 120 performs the Viterbi decoding of the time deinterleaved signal. The Viterbi decoder 120 generates a new bit pattern by forming a relational expression using a plurality of bits in front of the current bit to generate a new bit pattern. Even if an error occurs, a method of detecting and correcting a bit having an error by examining the preceding bit is called convolutional coding. The Viterbi decoder decodes the convolutional coded signal.

The byte deinterleaver 130 may deinterleave it in byte units after the Viterbi decoding. In this way, the signal interleaved and transmitted by the transmitting end is deinterleaved by bit unit and byte unit through the above-described process.

The serialization block 135 transmits a channel transmitted in parallel through the byte deinterleaver 130 as a single channel for each packet, which is arranged in front of the RS decoder 140 and the RS decoder 140. It is characterized by the role of the interface to share.

When the RS decoder 140 transmits data and a parity bit in a manner of adding a redundant parity by cutting a channel that is input through the serialization block 135 into a predetermined length, the receiving side transmits the data and the parity bit. The error is corrected by checking the presence of an error by checking the parity, thereby correcting a clustering error of the byte deinterleaved channel.

The byte / bit converter 145 finally transmits the coarse channel to the RS decoder 140 to the A / V data decoder 520 to receive only the channel in bits for display. ) Is a converter that converts channels in bytes into channels in bits for the interface with).

In the above-described signal processing of the CDM type forward error correction encoder 100, an independent Viterbi decoder 120 and an RS decoder 140 are required for each channel to process channels transmitted in parallel.

Four channels are used on the digital multimedia broadcasting device under development. However, according to the present invention, by arranging a serialization block that sequentially delivers channels in front of the RS decoder 140 required per channel, the RS decoder is shared as if there is only one channel, so that four conventional RS decoders are required. Because only a few dogs are used, resources can be saved and chip area can be reduced.

In addition, according to the present invention, the RS decoder 140 may share and use the RS decoder 140 regardless of the change even if the number of channels on the digital multimedia broadcasting device is currently being developed.

However, in the Viterbi decoder 120, there is a memory for backtracking data in the Viterbi decoder 120, which is present for each channel to structurally place the serialization block 135 in front of the Viterbi decoder 120. This is not good for chip area or efficiency.

Also, in the case of the byte deinterleaver 130, if the serialization block 135 is placed in front of the byte deinterleaver 130, the data is delayed for each channel during deinterleaving in the byte deinterleaver 130. To do this, the structure for this becomes too complex, which, in turn, is not good for chip area or efficiency.

FIG. 3 is a diagram illustrating a form of a signal for interfacing with an A / V according to the present invention, wherein a clock, data, and a signal indicating validity of the data are transmitted to the A / V data decoder, wherein the data is in packet units. To be passed in bits, not bytes.

Since the RS decoder 140 of the above-described digital multimedia broadcasting uses (204, 188) bytes on the digital multimedia broadcasting apparatus under development, one channel is 204 x 8 to be 1632 bits, among which the A / V data decoder 520 The valid data transmitted to 188 x 8 1504 bits is transmitted as a unit, and the remaining 128 bits are used to distinguish each channel.

Channels transmitted in parallel to the serialization block 135 have a sequence of packets in the same order as they are sent by the transmitter after passing through each byte deinterleaver 130, and then through the serialization block 135 This function combines each channel into one as if data is transmitted from the channel of.

In this case, the serialization is not performed in the order of the data coming in, but each channel can be delivered sequentially (Ch1, Ch2, Ch3, Ch4, Ch1, Ch2 ...) considering the interface with the A / V data decoder. do.

In addition, the order of the channels to be transmitted is that in principle, each channel is sequentially transmitted without transmitting two channels in succession.

As described above, the serialization block 135 uses the Viterbi decoder 120 to make a channel coming out of the byte deinterleaver 130 as one channel to perform an interface for the shared structure of the RS decoder 120. ) And a clock that is as fast as the number of channels of the byte reverse interleaver 130.

For example, on the digital multimedia broadcasting device currently under development, the serialization block 135 may use the previous Viterbi decoder 120 to transmit channels transmitted in parallel as one channel per packet because the maximum number of four channels is decoded. Or 4 times faster than the byte reverse interleaver (130).

However, the number of such channels may vary, and according to the present invention, even if there is a change in the number of such channels, the RS decoder 140 may be shared and used regardless of the number of channels. The clock of 135 may be adjusted, and according to the present invention, even if the number of channels is changed, it can be effectively used.

4 is a block diagram illustrating a digital multimedia broadcasting receiver including a forward error correction encoding unit according to the present invention.

Looking at the receiving process of the receiving apparatus, the received signal input to the antenna is converted to the baseband (Baseband) in the tuner 400, the converted signal is a constant size of the signal input to the A / D (420) The A / D 420 is converted into a digital signal through an automatic gain adjusting unit 410 which measures the power of the received signal and multiplies the calculated gain value.

In order to demodulate the signal in the CDM transmission method, the converted signal must capture a pseudo-noise sequence (PN) used for signal spreading. The searcher enters a searcher 430 functioning to secure within two chips, and the signal found in the searcher 430 enters a tracker 441 ˜ 44n which functions to finely synchronize a signal. The process performed by the tracker is called signal tracking.

In the above description, the chip refers to a division unit of the pseudonoise sequence PN.

In this way, the signal that is captured and tracked and synchronized is despread by multiplying the pseudonoise sequence (PN) generated by the receiver, and the symbol of the desired CDM channel is extracted by multiplying the WALSH code used to distinguish the CDM channels. 451 to 45n). This process is performed in all the multiple paths found by the searcher 430, each of which is called a finger.

Here, the frequency offset estimator 530 estimates the frequency offset for each finger, synthesizes the frequency offset, and feeds back the tuner 211 to correct the frequency offset.

The RAKE synthesizer 460 synthesizes the extracted symbols by multiplying the WALSH codes. Rake synthesis is performed for all CDM channels for demodulation. The synthesized symbols extract the timing of the frame and superframe using the pilot channel in the timing extraction circuit 470 of the frame and superframe.

In this way, the signal sent from the rake synthesizer 460 enters the forward error correction encoding unit 100 in which one pilot channel and four channels correspond to the present invention, and the pilot channel includes a code for releasing the channel. The four channels are detected by the data mode detector 510 and the time deinterleaver 110, the Viterbi decoder 120, the byte deinterleaver 130, the serialization block 135, the RS decoder 140, and the byte. It enters the / bit converter 150 and decodes it using a pilot channel to be displayed through the A / V data decoder 520.

The present invention is not limited to the above-described embodiments, and as can be seen in the appended claims, modifications can be made by those skilled in the art to which the invention pertains, and such modifications are within the scope of the present invention.

The effects of the digital multimedia broadcasting receiver including the forward error correction coding unit according to the present invention described above are as follows.

By sharing the RS decoders in the forward error correction encoder, by using only one RS decoder regardless of the number of channels, there is an effect of efficiently using resources and reducing the chip area in chip implementation.

Claims (5)

After time deinterleaving, Viterbi decoding and byte deinterleaving for all the channels that you want to decode, A serialization block for sequentially transmitting the bytes deinterleaved and transmitted in parallel as one channel for each packet; An RS decoder for correcting errors in channels that have passed through the serialization block; And a byte / bit converter configured to convert an error-corrected channel from a byte unit to a bit unit via the RS decoder. The method of claim 1, wherein the serialization block, A digital multimedia broadcasting receiver including a forward error correction encoder, characterized in that each channel is sequentially transmitted in consideration of an interface with an A / V data decoder rather than being performed in order of data. The method of claim 2, A digital multimedia broadcasting receiver including a forward error correction encoder, characterized in that each channel is sequentially transmitted without two channels being sequentially transmitted. The method of claim 3, wherein A digital multimedia broadcasting receiver including a forward error correction encoder, characterized in that the clock is used by the number of times faster than the Viterbi decoder and the byte deinterleaver so that each channel can be sequentially transmitted. The method of claim 1, wherein the RS decoder, And a serial error block encoding unit, wherein the serialization block is located in front of the RS decoder and the byte / bit converter is located in the rear of the RS decoder to share the RS decoder.

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