KR100612152B1 - Method for synchronizing secondary-synchronization channel in wide code division multiple access and recording media stored program embodying the same - Google Patents

Abstract

The present invention relates to an S-SCH synchronization method and apparatus therefor in a WCDMA system. In this method, after receiving a received signal at a time when an S-SCH slot is present, each received signal during a specific period and an S-SCH are received. Among the array values of the specific signal pattern table in which the signal patterns are stored in advance, the values are accumulated by multiplying the array values of the specific signal pattern table corresponding to the positions in the specific sections of each received signal, and then synchronizing the values accumulated during the specific sections. Output as a result. Thereafter, the process is repeatedly performed until the time when there is no S-SCH slot. According to the present invention, it is possible to implement an S-SCH synchronization device of a software reconfigurable SDR concept, and also to obtain an economical effect of enabling real-time processing using a relatively low / low speed DSP chip. have.

WCDMA, Sync, S-SCH, Sync Channel, DSP, SDR

Description

METHOD FOR SYNCHRONIZING SECONDARY-SYNCHRONIZATION CHANNEL IN WIDE CODE DIVISION MULTIPLE ACCESS AND RECORDING MEDIA STORED PROGRAM EMBODYING THE SAME

1 is a block diagram of an S-SCH synchronization apparatus in a conventional WCDMA system.

2 is a conceptual diagram in which an S-SCH synchronization apparatus in a WCDMA system of SDR concept reconfigurable in software using a DSP chip according to an embodiment of the present invention is used.

3 is a flowchart of an S-SCH synchronization method in a WCDMA system according to an embodiment of the present invention.

The present invention relates to a method of synchronizing a secondary-synchronization channel (S-SCH) in a wide code division multiple access (WCDMA) system, and in a WCDMA system performing S-SCH synchronization with software on a DSP. A S-SCH synchronization method and a recording medium storing a program for implementing the method.

Conventional wireless communication devices are designed to support only predefined communication systems. Therefore, these wireless communication devices have no flexibility for other communication methods, and thus global roaming or selective use of a wireless communication system is impossible.

To address these shortcomings, multi-mode and multi-band wireless communication devices are on the market, but they offer different flexibility depending on the user's needs, providing limited flexibility, but the supported modes and functions are predefined. Therefore, in order to access a new communication system or a system of another communication method in another region, there is a problem in that the hardware of the wireless communication device needs to be replaced.

In order to overcome this inflexibility, SDR (Software Defined Radio) technology has emerged in the 1990s, which converts and processes a signal digitally at a radio frequency (RF) or intermediate frequency (IF) stage. This SDR technology, in principle, implements a communication system by processing all parts of the stage after the software by software, and operates without changing or adding new hardware, such as operation frequency, modulation type, and modulation type. ), The bandwidth (bandwidth), network protocols (network protocols) can be changed by changing only the software program.

In terms of current hardware technology, processing to high frequency (RF) is not practical, so most of the studies have been implemented by software since intermediate frequency (IF). Therefore, the core algorithm of the wireless modem of the wireless communication device using the SDR technology is generally composed of the DSP chip and its software.

When the wireless communication device is manufactured using the SDR technology, the functions and modes can be freely reconfigured in software unlike the hardware-oriented devices. For example, using a communication device using the SDR technology, it is possible to support a variety of existing mobile communication standards (CDMA, GSM, WCDMA, etc.) by replacing only the software with the same platform.

However, despite the above advantages, SDR technology has many difficulties to apply in reality. One of the biggest obstacles is that the DSP chip's processing speed is not sufficient to support the complex physical layer specification for wireless communication. ASICs or FPGAs are widely used in most existing wireless communication devices because they can be parallelized in time by arranging a large number of circuit blocks spatially and are not limited in processing time. On the other hand, since the DSP chip is a device that the internal CPU executes the programs sequentially, it is difficult to implement the physical layer standard for wireless communication due to the theoretically impossible parallel processing. Of course, there are a plurality of arithmetic operators inside the DSP chip, which can compensate for some of these shortcomings through software pipeline techniques, but they are also a supplementary means and cannot be a fundamental solution. In particular, in the case of a WCDMA base station receiver, in order to process chip rate processing, which requires fast computation, to a DSP chip, the amount of computation can be realized through various techniques.

On the other hand, the S-SCH (Secondary Synchronization Channel) synchronization device of the WCDMA system defined in 3GPP is generally implemented as an IC circuit, such as ASIC, as shown in FIG. As described above, the wireless communication modem implemented using the IC circuit can be parallelly processed in time by rearranging a large number of internal circuit blocks spatially, and thus is not greatly affected by the calculation amount and the processing speed. In addition, the S-SCH synchronization device shown in FIG. 1 is widely used in a WCDMA system because the structure occupies a small amount of circuit.

However, when the S-SCH synchronization device is implemented to be reconfigurable in software using a DSP chip, a slight increase in the amount of computation is expected in the chip rate due to the characteristics of the DSP chip performing sequential calculation. In the context of the inability to process in real time, there is a problem that is not suitable for real time processing due to the large amount of required calculations.

According to the circuit configuration shown in FIG. 1, five addition and subtraction operations and three multiplication operations are performed every chip time, and one subtraction operation is required every 16 chip times. In addition, since the operation of the delay device must be processed in every chip by software, there is a problem in that real-time processing is difficult due to an increase in the amount of computation and an inefficiency of pipelining due to the increase of the computation.

Meanwhile, the prior art discloses Korean Patent Application No. 2001-7011316, "Efficient Synchronization Method and Apparatus in Spread Spectrum Communication," which discloses wireless transmission and reception using one or more complementary sequences, for example, Golay sequence pairs. It is characterized by providing accurate and efficient synchronization of periods. However, this technique is a hardware device that achieves synchronization by generating a timing estimate by implementing a Golay correlator in the form of a matched filter, and is not a device that achieves synchronization in terms of software.

Therefore, the technical problem of the present invention is to solve the above problems, S-SCH synchronization method in a WCDMA system that can be implemented in software on the DSP chip by processing the S-SCH signal with a much smaller amount of operation than the required operation amount and A program for implementing the method is provided to provide a storage medium.

S-SCH synchronization method in a WCDMA system according to an aspect of the present invention for achieving the above object,

a) receiving a received signal at the time when the S-SCH slot exists; b) of the specific signal pattern table corresponding to the position in the specific section of each of the received signals among the arrangement values of each of the received signals during the specific section and the specific signal pattern table in which the S-SCH signal pattern is stored in advance; Accumulating by multiplying array values; c) outputting a value accumulated during the specific period as a synchronization result value; And d) repeating steps b), c) and d) until the time when the S-SCH slot does not exist.

Here, the step a) may include: i) initializing a count value and a cumulative value indicating a position of a received signal in the specific section; ii) waiting for a reception signal input; iii) when the received signal is input in step ii), determining whether the time point at which the received signal is input is a time point at which a slot of the S-SCH exists; And iv) if the time point at which the received signal is input in step iii) is not the time point at which the S-SCH slot exists, the time i is input until the time point at which the received signal is input is the time point at which the S-SCH slot exists. ), ii) and iii).

Further, in step b), when the signal waiting in step ii) is received, the accumulated value is multiplied by the received signal and an array value corresponding to the count value among the array values of the specific signal pattern table. Adding; vi) determining whether the count value is a count value representing the specific section; And vii) if it is determined in step vi) that the count value is a count value representing the particular section, determining that the cumulative value added in step v) is a synchronization result value during the particular section. do.

In addition, the step b), in the step vii), if it is determined that the count value is not a count value indicating the specific interval, increasing the count value to perform synchronization for the next received signal; And updating the cumulative value for another received signal until the count value becomes a count value representing the specific section.

In addition, the step c), the step of outputting a cumulative value that is the synchronization result value determined in step vii); And initializing the accumulated value; And increasing the count value to perform synchronization on a next received signal.

S-SCH synchronization apparatus in the WCDMA system according to another aspect of the present invention,

An analog / digital converter for converting a received signal into a digital signal and outputting the digital signal;

A FIFO buffer for storing the digital signal output from the analog / digital converter; And performing S-SCH synchronization from the digital signal stored in the FIFO buffer based on a specific signal pattern table in which an S-SCH signal pattern is stored in advance, and performing the S-SCH synchronization according to the S-SCH synchronization program code. It includes a DSP chip (Digital Signal Processor Chip) unit.

Here, the DSP chip unit, the internal memory for taking a predetermined amount from the data stored in the FIFO buffer; And a DSP chip having a central processing unit (CPU) configured to perform synchronization of the S-SCH by using the data stored in the internal memory in one package.

The DSP chip unit may further include a memory configured to store software including a program code for implementing the S-SCH synchronization.

The DSP chip unit may further include a memory configured to store the specific signal pattern table storing S-SCH signal patterns of 256 chips.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

Hereinafter, an S-SCH synchronization method and apparatus thereof in a WCDMA system according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a conceptual diagram in which an S-SCH synchronization apparatus in a WCDMA system of SDR concept reconfigurable in software using a DSP chip according to an embodiment of the present invention is used.

As shown in FIG. 2, the S-SCH synchronization device in the WCDMA system according to the embodiment of the present invention includes an analog-to-digital converter (ADC) 30 and a first input first out (FIFO) buffer (FIG). 40, and the DSP module 50.

The ADC 30 converts the radio signal received through the reception antenna 10 into a baseband signal by the IF / RF processing module 20 and converts the analog signal into a digital signal and outputs the converted analog signal.

The FIFO buffer 40 stores data output from the ADC 30 and provides a predetermined amount of the stored data in accordance with a request of the DSP module 50.

The DSP module 50 uses the data stored in the FIFO buffer 40 by a predetermined amount to process S-SCH synchronization in software.

The DSP module 50 includes a DSP chip 51 including the internal memory 52 and the CPU 54 in one package.

The internal memory 54 takes a certain amount from the data stored in the FIFO buffer 40 and stores it for use by the CPU 54.

The CPU 54 uses the data stored in the internal memory 52 to perform synchronization of the S-SCH in a manner according to an embodiment of the present invention.

The DSP module 50 further includes a memory for storing a software algorithm including program code for the CPU 54 of the DSP chip 51 to process data stored in the internal memory 52 to perform synchronization of the S-SCH. Included.

In addition, a memory in which signal patterns of S-SCH as many as 256 chips are stored in a table form in the synchronizing device, not in the DSP chip 50 or the DSP chip 50 (hereinafter, referred to as a "signal pattern table"). Is further included. Therefore, the CPU 54 uses as many S-SCH signal patterns as 256 chips stored in the signal pattern table when performing S-SCH synchronization using data stored in the internal memory 52.

Hereinafter, an S-SCH synchronization method in a WCDMA system according to an embodiment of the present invention will be described in detail with reference to FIG. 3.

First, when the WCDMA system or the synchronization device is initialized, the CPU 54 of the DSP chip 51 initializes the count value cnt and the cumulative value (accum), which are internal variables, to 0 (S300), and then the FIFO buffer ( Waiting for input of the received signal sample from 40 (S310).

When the signal transmitted from the transmitting device of the WCDMA system is received through the receiving antenna 10 and input to the FIFO buffer 40 through the IF / RF processing module 20 and the ADC 30 and stored, the CPU 54 When the signal samples stored in the FIFO buffer 40 are brought into the internal memory 52, input processing of the received signal samples is performed. Hereinafter, as described above, when the CPU 54 takes the input signal sample into the internal memory 52 and stores the input signal sample, the CPU 54 processes the input signal sample as an input of the received signal sample and the detailed description thereof is omitted.

When the received signal sample is input as described above in step S310, the CPU 54 determines whether the present time point is a time point at which a slot of the S-SCH exists. This determination is performed according to the well-known WCDMA synchronization algorithm, and thus will be readily understood by those skilled in the art even if the detailed description is omitted here.

In step S320, if it is determined that the current time point is a time point at which the slot of the S-SCH exists, the signal pattern table for storing the S-SCH as many as 256 chips is stored in a table form in the cnt array. After multiplying the corresponding value S-SCH_table [cnt] by the value of the received signal input, this value is accumulated in accum (S330). This process can be expressed as Equation 1 below.

accum = (S-SCH_table [cnt] × input) + accum

By this equation, since accum is initially 0, only the multiplication value of the S-SCH signal pattern and the input signal when cnt = 0 is accumulated in accum.

Next, in order to output a cumulative value for every 16 chips, it is determined whether the remaining value (% operation) obtained by dividing the cnt value by 16 is 15 (S340).

As a result of the determination in step S340, if the remaining value obtained by dividing the cnt value by 16 is 15, the accumulated accum value until then is output as a synchronization value (S350), and again after accum is initialized to 0 (S360), In order to perform synchronization for the next chip, cnt is increased by 1 (S370), and then the process returns to the step S310 of waiting for a received signal sample input.

On the other hand, if it is determined that the present time point is not the time point at which the slot of the S-SCH is present, the process returns to the initializing step S300 again and the time point at which the received signal is input is the S-SCH slot. Steps S300, S310, and S320 are repeated until the present time.

In addition, as a result of the determination in step S340, if the remaining value obtained by dividing the cnt value by 16 is not 15, in order to repeat the next chips until the 16-chip interval is obtained when the accumulation is not performed for the 16-chip interval. The process moves to step S370.

On the other hand, the S-SCH synchronization method in the WCDMA system according to the embodiment of the present invention as described above is implemented as a program in a computer-readable form of a recording medium (CD-ROM, RAM, ROM, floppy disk, hard disk, optical Magnetic disks, etc.).

Although the preferred embodiment of the present invention has been described in detail above, the present invention is not limited thereto, and various other changes and modifications are possible.

According to the present invention, since only two addition operations, one multiplication operation, and one division operation are required for each chip, the amount of computation required by the conventional algorithm described in FIG. Multiplication and delay element operations can be handled in software, and S-SCH signals can be processed with much less computation compared to one subtraction every 16 chips.

Due to these advantages, when the S-SCH synchronization device of the software-reconfigurable SDR concept is implemented by applying this algorithm to a DSP chip, it is possible to enable real-time processing using a relatively low / low speed DSP chip. Economic effect can be obtained.

Claims (12)

In a secondary-synchronization channel (S-SCH) synchronization method in a wide code division multiple access (WCDMA) system, a) receiving a received signal at the time when the S-SCH slot exists; b) of the specific signal pattern table corresponding to the position in the specific section of each of the received signals among the arrangement values of each of the received signals during the specific section and the specific signal pattern table in which the S-SCH signal pattern is stored in advance; Accumulating by multiplying array values; c) outputting a value accumulated during the specific period as a synchronization result value; And d) repeating steps b), c) and d) until the time when the S-SCH slot does not exist S-SCH synchronization method in a WCDMA system comprising a. The method of claim 1, Step a) is i) initializing a count value and a cumulative value indicating a position of a received signal in the specific section; ii) waiting for a reception signal input; iii) when the received signal is input in step ii), determining whether the time point at which the received signal is input is a time point at which a slot of an S-SCH exists; And iv) if the time point at which the received signal is input in step iii) is not the time point at which the S-SCH slot exists, the time i) until the time point at which the received signal is input is the time point at which the S-SCH slot exists; repeating steps ii) and iii) S-SCH synchronization method in a WCDMA system comprising a. The method of claim 2, B), v) when the signal waiting in step ii) is received, multiplying the received signal with an array value corresponding to the count value among the array values of the specific signal pattern table and adding the multiplied value to the accumulated value; vi) determining whether the count value is a count value representing the specific section; And vii) if it is determined in step vi) that the count value is a count value representing the specific section, determining that the cumulative value added in step v) is a synchronization result value during the specific section. S-SCH synchronization method in the WCDMA system further comprising. The method of claim 3, Step b). In step vii), if it is determined that the count value is not a count value indicating the specific section, increasing the count value to perform synchronization on a next received signal; And Updating a cumulative value for another received signal until the count value becomes a count value representing the specific section; S-SCH synchronization method in the WCDMA system further comprising. The method of claim 3, C), Outputting a cumulative value that is a synchronization result value determined in step vii); And Initializing the cumulative value; And Increasing the count value to perform synchronization on a next received signal S-SCH synchronization method in a WCDMA system comprising a. The method according to any one of claims 1 to 5, The specific section is a S-SCH synchronization method in the WCDMA system, characterized in that the section corresponding to 16 chips. The method according to any one of claims 1 to 5, The specific signal pattern table stores S-SCH signal patterns of 256 chips. delete delete delete delete A recording medium storing a program for implementing a method of synchronizing a secondary-synchronization channel (S-SCH) in a wide code division multiple access (WCDMA) system, a) a function of receiving a received signal at the time when the S-SCH slot exists; b) of the specific signal pattern table corresponding to the position in the specific section of each of the received signals among the arrangement values of each of the received signals during the specific section and the specific signal pattern table in which the S-SCH signal pattern is stored in advance; Accumulating by multiplying array values; c) a function of outputting a value accumulated during the specific period as a synchronization result value; And d) repeating steps b), c) and d) until the time when the S-SCH slot does not exist Record medium that stores the program to implement.

Images