KR100606531B1 - Driving method of flash memory device - Google Patents

Abstract

The present invention relates to a method for driving a flash memory device proposed by the present applicant,

In a method of driving a flash memory device according to the present invention, a first block oxide film is provided in each of a source and a drain region on a semiconductor substrate having a source / drain region connected to a plurality of bit lines, and each of the first block oxide films is provided. A method of driving a flash memory device having a floating gate formed thereon and having a control gate connected to a plurality of word lines on a semiconductor substrate between the source / drain regions, the negative gate of the plurality of word lines. And applying a voltage of 0 V or a positive voltage to the substrate, and floating the plurality of bit lines to erase electrons of the floating gate toward a channel region of the semiconductor substrate. Apply a positive voltage to the corresponding wordline where the specific cell is needed, apply 0V to the other wordline, and program A program step of injecting electrons present in the channel of the substrate into the control gate of the specific cell by applying a positive voltage to the corresponding bit line where the specific cell is needed and applying 0 V to the other bit line and the substrate And a reference voltage is applied to the word line of the specific cell, a positive voltage is applied to the bit line of the specific cell, and 0V is applied to other word lines, the bit line, and the substrate. And a read step of identifying a program or erase state.

Flash memory, program, erase

Description

Driving method of flash memory device {Driving method of flash memory device}             

1 is a cross-sectional view of a memory device having an ETOX structure among floating gate series nonvolatile memory devices according to the related art.

2 is a graph illustrating the distribution of the number of memory cells to a threshold voltage during a program and erase process using a non-volatile memory device of a conventional floating gate series.

3 is a structural cross-sectional view of a flash memory device for implementing an embodiment of the present invention.

4 is a circuit diagram of a flash memory device according to the present invention.

5 is a reference diagram illustrating a voltage applied to a driving process of a flash memory device according to an exemplary embodiment.

Description of the main parts of the drawing

301 semiconductor substrate 302 first block oxide film

303: floating gate 304: gate insulating film

305: second block oxide film 306: control gate

307: oxide film 308: spacer

The present invention relates to a method of driving a flash memory device, and more particularly, to a method of driving a flash memory device proposed by the present applicant.

The most functionally ideal among the semiconductor memory devices is a non-volatile memory that can be easily programmed by a user by arbitrarily switching the memory state by an electric method and maintaining the memory state even when the power supply is removed. Element. At present, in terms of process technology, nonvolatile memory devices are classified into a floating gate series and a metal-insulator-semiconductor (MIS) series in which two or more kinds of dielectric layers are stacked in double or triple layers.

The floating gate series nonvolatile memory device implements memory characteristics by using potential wells, and is currently the most widely used flash EEPROM (EPROM Tunnel Oxide) structure. Is representative. In contrast, the MIS-based nonvolatile memory device performs a memory function by using traps present at the dielectric layer, the bulk layer, the dielectric layer-dielectric layer interface, and the dielectric layer-semiconductor interface.

A representative structure of the floating gate-based nonvolatile memory device, a program method and an erase method using the same are described below with reference to the accompanying drawings. 1 is a cross-sectional view illustrating a memory device having an ETOX structure among floating gate series nonvolatile memory devices according to the related art.

As shown in FIG. 1, the tunnel oxide film 102, the floating gate 103, the dielectric film 104, and the control gate 105 are sequentially stacked on the p-type semiconductor substrate 101. Source S regions and drain D regions are formed in the semiconductor substrate surfaces on both sides of the structure. Here, the dielectric film typically uses an oxide-nitride-oxide (ONO) layer in order to increase the coupling ratio.

A program and erase method of a floating gate-based nonvolatile memory device having such a structure is performed as follows. First, a program method uses a method of increasing a threshold voltage by injecting electrons into a potential well formed in the floating gate through hot electron injection or Fowler-Nordheim (FN) tunneling. The method uses a method of injecting holes by hot hole injection to recombine electrons and holes, or by flowing electrons to the substrate using FN tunneling to lower the threshold voltage.

In the erasing process using a conventional floating gate series nonvolatile memory device, an over erase problem arises. The over erasure refers to a phenomenon in which electrons stored in the floating gate are leaked out more than necessary and the threshold voltage is negative, and the cell is overerased on the bit line in the nonvolatile memory circuit. If any one of these is present, an overcurrent flows in the bit line, which causes a problem in that even the data of the non-erased cell cannot be read.

FIG. 2 is a graph illustrating the distribution of the number of memory cells to a threshold voltage when a program and an erase process are performed using a non-volatile memory device of a conventional floating gate series, and illustrates a program state and an erase state having a predetermined voltage distribution. The voltage between and the erase state represents a threshold voltage window (V _T window) (W). As shown in FIG. 2, there is a cell (a) in which an over erase occurs during the erase process and the threshold voltage falls below 0 V. Accordingly, the threshold voltage distribution during erasing becomes wider than the threshold voltage distribution during programming. When the threshold voltage distribution is widened during the erase, the threshold voltage window between the program state and the erase state is reduced, thereby deteriorating the characteristics of the flash memory device.

On the other hand, there are a variety of causes of the over-erasing, in detail, the line width of the active region, the thickness of the tunnel oxide film, the junction overlap, the line width of the floating gate, the roughness of the floating gate surface, the tunnel oxide film Over-destruction can be caused by various process factors, such as damage, localized thinning of the tunnel oxide, and pinholes. Since there are many causes of over-erasing in the related art, in the related art, a method of increasing the threshold voltage of the corresponding cell by detecting and reprogramming the over-erased cell rather than solving the fundamental problem of over-erasing is taken. Doing. This not only lengthens the test time, but also requires additional circuitry to recover over-erased cells.

On the other hand, the present applicant has proposed a flash memory device having the following structure to solve the above problems. 3 is a structural cross-sectional view of the flash memory device proposed by the present applicant.

In the flash memory device proposed by the present applicant, as shown in FIG. 3, a gate insulating film 304 and a first block oxide film 302 are formed on predetermined regions on a semiconductor substrate 301, respectively. ) And the first block oxide film 302 are formed with a control gate 306 and a floating gate 303, respectively. A second block oxide film 305 is formed on a surface where the control gate 306 and the floating gate 303 are in contact with each other. In addition, an oxide film 307 is formed on a surface of the control gate 306, and a spacer 308 is formed on a sidewall of the control gate 306. Meanwhile, a source / drain region S / D having an LDD structure is formed in the substrate 301.

In the structure of the flash memory device of FIG. 3, the floating gate 303 is formed in each of the source / drain regions S / D in one transistor, so that the area thereof is reduced to 1/2 size compared with the conventional flash memory device. Even if the floating gate 303 is over-erased, when 0 V is applied to the control gate 306, the channel is turned off so that a read error due to over-erasing does not occur. Thus, there is no need to reprogram the memory cells that have been erased in the conventional flash memory device and no additional circuitry is required.

However, the present applicant does not present a detailed process of the driving method in the proposal of the flash memory device as described above, and the present invention is intended to present the method.

An object of the present invention is to provide a method for driving a flash memory device proposed by the present applicant as described above.

In accordance with another aspect of the present invention, there is provided a method of driving a flash memory device, wherein a first block oxide layer is provided in each of a source and a drain region on a semiconductor substrate having source and drain regions connected to a plurality of bit lines. A floating gate is formed on each of the first block oxide layers, and a method of driving a flash memory device having a control gate 306 connected to a plurality of word lines on a semiconductor substrate between the source / drain regions, A negative voltage is applied to the plurality of word lines, a 0V or a positive voltage is applied to the substrate, and the plurality of bit lines are floated to transfer electrons of the floating gate to channels of the semiconductor substrate. Erasing toward the region; and applying a positive voltage to a corresponding word line where a specific cell requiring a program exists, and Electrons present in the channel of the substrate 301 by applying 0V to the line, applying a positive voltage to the corresponding bit line where the particular cell requiring the program is present, and applying 0V to other bit lines and the substrate Injecting a control gate into the control gate of the specific cell; and applying a reference voltage to the word line of the specific cell, applying a positive voltage to the bit line of the specific cell, and other word lines and bits. And a read step of determining a program or erase state of the specific cell by applying 0V to the line and the substrate.

Preferably, the erasing may include applying a negative voltage to the plurality of word lines, applying a voltage of 0 V or a positive voltage to the plurality of bit lines, and floating the substrate. Electrons of the floating gate may be erased toward the source / drain region S / D of the semiconductor substrate.

Preferably, the reference voltage may be a value approximately midway between the highest voltage among the threshold voltages of the erase state and the lowest voltage among the threshold voltages of the program state.

According to a feature of the present invention, by using a flash memory device capable of implementing two bits of operation with one transistor, it is possible to solve problems such as over-erasing, which was an operation problem of a conventional flash memory device.

Hereinafter, a driving method of a flash memory device according to the present invention will be described with reference to the accompanying drawings. 4 is a circuit diagram of a flash memory device according to the present invention, Figure 5 is a reference diagram showing a voltage applied to the driving process of the flash memory device according to the invention.

As shown in FIG. 4, a plurality of flash memory cells and logic circuits for selectively driving the flash memory cells, such as a word line driving circuit, a bit line driving circuit, and a common source driving circuit (not shown), may be used. A combined configuration is taken.

3, a gate insulating film 304 and a first block oxide film 302 are formed on a predetermined region on a semiconductor substrate 301, as shown in FIG. 3. The control gate 306 and the floating gate 303 are formed on the first block oxide film 302, and the second block oxide film 305 is formed on the surface where the control gate 306 and the floating gate 303 are in contact with each other. In addition, an oxide film is formed on a surface of the control gate 306, a spacer 308 is formed on a sidewall of the control gate 306, and a source having an LDD structure inside the substrate 301. The / drain region S / D is formed.

In this case, the control gate 306 has a structure connected to the plurality of word lines WL1, WL2, WL3, and WL4, respectively, and the first impurity diffusion layers, for example, source regions are formed at one side of the structures. And a plurality of bit lines BL1, BL1 ′, BL2, and BL2 in a state in which second impurity diffusion layers, for example, drain regions, are formed on the other side of the structures. `, BL3, BL3`) respectively have a structure.

In this situation, a series of erase procedures are performed to erase electrons injected into the floating gates 303 of the memory cells toward the semiconductor substrate 301. At this time, the erasing includes a first erasing method for drawing electrons toward the channel and a second erasing method for drawing electrons toward the source / drain region S / D.

In the case of the first erase method, as shown in FIG. 5, a negative voltage is applied to the word lines WL1, WL2, WL3, and WL4, and 0 V or positive is applied to the substrate 301. Is applied, and the bit lines BL1, BL1 ', BL2, BL2', BL3, and BL3 'are floated. Accordingly, a strong electric field is applied from the semiconductor substrate 301 to the control gate 306, and electrons trapped in the potential well of each floating gate 303 by the electric field are The first block oxide layer 302 is tunneled to a channel of the semiconductor substrate 301 by Fowler-Nordheim (FN) tunneling to lower the threshold voltage of the floating gate 303. At this time, since a strong electric field is applied from the channel of the semiconductor substrate 301 to the word line region, it is necessary to set a condition that no breakdown occurs in the word line when the channel FN tunneling method is used. .

In the second erasing method, as shown in FIG. 5, in order to draw electrons from the floating gate 303 to the source / drain region S / D of the substrate 301, first, the word line WL1, A negative voltage is applied to WL2, WL3, and WL4, and a 0V or positive voltage Vs is applied to the bit lines BL1, BL1 ', BL2, BL2', BL3, and BL3 '. The substrate 301 is floated. Accordingly, a strong electric field is applied from the source / drain region S / D of the semiconductor substrate 301 toward the control gate 306, and the potential of each floating gate 303 is caused by the electric field. The electrons trapped in the well exit the source / drain region S / D of the semiconductor substrate 301 by FN tunneling the first block oxide layer 302, so that the threshold voltage of the floating gate 303 is low. You lose. As described above, the FN tunneling and erasing of the floating gate 303 toward the source / drain region S / D is performed because the electric field is not strongly formed from the channel of the semiconductor substrate 301 toward the control gate 306. (breakdown) No problem.

In the first and second erase methods, a series of program procedures for filling electrons into a memory cell having a desired characteristic are performed among the respective memory cells while erasing of the flash memory device is completed. For the program, first, a positive voltage Vwlp is applied to the corresponding word line WL2 as shown in FIG. 5, and 0 V is applied to the other word lines WL1, WL3, and WL4 that do not require a program. In the case of a bit line, a positive voltage Vblp is applied to a corresponding bit line BL2, and 0 V is applied to other unprogrammed bit lines BL1, BL1 ', BL2', BL3, and BL3 '. Apply. On the other hand, 0V is applied to the substrate 301.

According to the voltage condition, the cells to which the bit line voltage is applied to the drain region of the floating gate 303 pattern among the cells are all cells connected to the corresponding bit line BL2 or the corresponding word line WL2 to which the voltage is applied. Voltage is applied to the drain region and the control gate 306 of the specific cell MC connected to the current to flow in the control gate 306 of the specific cell MC. Accordingly, the electric field becomes the maximum value in the region where the specific cell MC is formed, and electrons present in the channel of the semiconductor substrate 301 become hot electrons. The threshold voltage is increased by being injected into the potential well formed in the floating gate 303.

In such a program operation, a positive voltage Vwlp Vblp applied to a corresponding word line BL2, a corresponding bit line BL2, or the like may be applied to a hot electron injection efficiency, a breakdown of a drain region, Consider program current, gate and drain resistance. In addition, in the case of a positive voltage Vwlp applied to the corresponding word line WL2, a program is performed on the floating gate 303 of the source region, and the source region is applied when the Vwlp voltage is applied even if a potential barrier occurs in the source region. In this case, the potential barrier of the source region must be set to a condition sufficient to lower electrons to be injected into the channel of the semiconductor substrate 301.

Meanwhile, a series of reading procedures for checking the program state of the programmed specific cell MC is performed while the program is in progress. First, as shown in FIG. 5, a reference voltage Vref is applied to the corresponding word line WL2, a positive voltage Vblr is applied to the corresponding bit line BL2 ′, and other word lines ( 0 V is applied to all of the WL1, WL3, and WL4, the bit lines BL1, BL1 ′, BL2, BL3, BL3 ′, and the substrate 301. In this case, the reference voltage is selected as a value that is halfway between the highest voltage among the threshold voltages of the erase state and the lowest voltage among the threshold voltages of the program state. In addition, if the voltage applied to the bit line during the read operation is too high, unnecessary program operation may be performed on the cell on the left side of the specific cell MC, that is, the cell connected to the bit line BL2 ′. A reference voltage should be applied.

If the specific cell MC is erased due to the voltage condition, a current flows from the drain region of the bit line BL2 'toward the source region of the bit line BL2. If the specific cell MC is programmed, BL2 No current flows from the drain region to the source region of the bit line BL2, so that the specific cell MC can determine whether it is a program state or an erase state. Through the above process, the driving method of the flash memory device according to the present invention, that is, the erase process, the program process and the reading process are completed.

The driving method of the flash memory device according to the present invention has the following effects.

By using a flash memory device capable of implementing two bits of operation with one transistor, it is possible to solve problems such as over-erasing, which was an operation problem of a conventional flash memory device.

Claims (3)

A first block oxide layer is formed on each of the source and drain regions on a semiconductor substrate having a source / drain region connected to a plurality of bit lines, and a floating gate is formed on each of the first block oxide layers. A method of driving a flash memory device having a control gate connected to a plurality of word lines on a semiconductor substrate between drain regions, A negative voltage is applied to the plurality of word lines, a 0V or a positive voltage is applied to the substrate, and the plurality of bit lines are floated to transfer electrons of the floating gate to channels of the semiconductor substrate. Erasing towards the area; A positive voltage is applied to the corresponding word line where the specific cell to be programmed is present, 0 V is applied to the other word line, and a positive voltage is applied to the corresponding bit line where the specific cell requiring the program is present. A program step of injecting electrons present in a channel of the substrate into a control gate of the specific cell by applying 0V to other bit lines and the substrate; Apply a reference voltage that is about the middle of the highest voltage among the threshold voltages of the erase state and the lowest voltage among the threshold voltages of the program state to the word line of the specific cell and apply a positive voltage to the bit line of the specific cell. And reading a program or erase state of the specific cell by applying 0 V to other word lines, bit lines, and substrates. A first block oxide layer is formed on each of the source and drain regions on a semiconductor substrate having a source / drain region connected to a plurality of bit lines, and a floating gate is formed on each of the first block oxide layers. A method of driving a flash memory device having a control gate connected to a plurality of word lines on a semiconductor substrate between drain regions, A negative voltage is applied to the plurality of word lines, 0 V or a positive voltage is applied to the plurality of bit lines, and the substrate is floated to transfer electrons of the floating gate to a source of the semiconductor substrate. Erasing towards / drain regions; A positive voltage is applied to the corresponding word line where the specific cell to be programmed is present, 0 V is applied to the other word line, and a positive voltage is applied to the corresponding bit line where the specific cell requiring the program is present. A program step of injecting electrons present in a channel of the substrate into a control gate of the specific cell by applying 0V to other bit lines and the substrate; Apply a reference voltage that is about the middle of the highest voltage among the threshold voltages of the erase state and the lowest voltage among the threshold voltages of the program state to the word line of the specific cell and apply a positive voltage to the bit line of the specific cell. And reading a program or erase state of the specific cell by applying 0 V to other word lines, bit lines, and substrates. delete

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