KR100599201B1 - clock control apparatus in digital signal processor and its method - Google Patents

Abstract

The present invention relates to an apparatus and method for controlling a clock of a digital signal processing processor.

In order to reduce the power consumption of the digital signal processing processor, the frequency mapping of the clock frequency required for each application software is mapped differently so that the software of the digital signal processing processor operates as many clocks as required to operate in real time. Configure the table. This is based on the fact that in the case of finite state machine (FSM) -based application software, the amount of computation of the digital signal processing processor required for each state is different. When the transition schedule is monitored by monitoring the state transition of each application software, the clock generation unit is driven according to the clock frequency corresponding to the transition state.

According to the present invention, the power consumption can be remarkably reduced by operating each application software in the digital signal processing processor with a minimum reference clock that allows real-time processing for each state.

SDR, DSP, Low Power, Clock Control

Description

Clock control apparatus in digital signal processor and its method

1 is a structural diagram of a clock control apparatus according to an embodiment of the present invention.

2 is a diagram illustrating a configuration example of a mapping table according to the present invention.

3 is a structural diagram illustrating an example in which a clock control device according to an embodiment of the present invention is implemented in a digital signal processing processor.

4 is a flowchart illustrating a clock control method according to an exemplary embodiment of the present invention.

The present invention relates to a clock control method, and more particularly, to an apparatus and a method for controlling a clock for the operation of a digital signal processor (DSP).

In general, wireless communication devices are designed to support only predefined communication systems. These wireless communication devices have no flexibility for other communication methods, and thus global roaming or selective use of a wireless communication system is impossible. To address these shortcomings, multi-mode and multi-band wireless communication devices are on the market, but they offer a variety of modes depending on the user's needs, providing limited flexibility, but the supported modes and functions are preliminary. Since it is defined, in order to access a new communication system or a system of another communication method in another region, there is a problem that the hardware of the wireless communication device needs to be replaced.

 In order to overcome this inflexibility, software defined radio (SDR) technology, which converts and processes a signal into a digital signal at the RF or IF stage, has emerged in the 1990s. SDR technology is a technology that implements a communication system by processing all parts of the stage after the antenna by software in principle, and operates without changing or adding new hardware, for example, operation frequency and modulation type. It is a technology that can change the bandwidth, the network protocols (network protocols), etc. only by changing the software program. In terms of current hardware technology, processing to high frequency (RF) is not practical, so most of the studies have been implemented by software since intermediate frequency (IF). Therefore, the core algorithm of the wireless modem of the wireless communication device applying the SDR technology is generally composed of a digital signal processing processor (hereinafter referred to as DSP) and its software.

When the wireless communication device is manufactured using the SDR technology, the functions and modes can be freely reconfigured in software unlike the hardware-oriented devices. For example, using a communication device using the SDR technology, it is possible to support a variety of existing mobile communication standards (CDMA, GSM, WCDMA, etc.) by replacing only the software in the same platform state.

However, despite these advantages, SDR technology has many difficulties to apply in reality. One of the biggest obstacles is the power consumption of the DSP. Modems used in mobile communication terminals in the form of application specific integrated circuits (ASICs) consume significantly less power than DSPs. Therefore, when the DSP-based modem is applied to the mobile communication terminal, the power consumption is relatively higher than that of the ASIC, thereby reducing the battery usage time, which is directly related to the decrease in the market competitiveness of the product.

Due to the physical nature of the DSP, lowering the frequency of the operating clock reduces power consumption. This can be used to reduce battery power consumption, but the processing speed of the DSP is also reduced, so that certain operations are not performed smoothly. In this case, the amount of computation can be greatly reduced by optimizing the software of the DSP, but this is also a supplementary measure and cannot be a fundamental solution for preventing the DSP battery power consumption.

Therefore, the technical problem to be achieved by the present invention is to reduce the power consumption by allowing the DSP software used in various electronic devices to operate in the clock required to operate in real time.

In order to achieve the above technical problem, the clock control method according to an aspect of the present invention, in the clock control method for controlling the clock signal generation for the operation of the digital signal processing processor, a) application software driven in the digital signal processing processor Monitoring the state transition of the; b) if the state transition of the application software is monitored, finding a clock frequency according to the state to be transitioned from the mapping table to which the clock frequencies required for each application software state are mapped and setting the driving frequency; And c) driving a clock generator for generating a clock signal according to the driving frequency to generate a clock signal corresponding to the frequency.

According to another aspect of the present invention, a clock control device includes a clock control device for controlling an operation of a clock generator that generates a clock signal for an operation of a digital signal processing processor including a plurality of application software. An application software processor including a monitoring state transition module and a status transition notification module for outputting a notification signal corresponding to the monitoring state transition module; And a storage module storing a frequency mapping table in which clock frequencies required for respective states are mapped for each application software, and searching for a frequency mapping table corresponding to the application software from the storage module according to the notification signal. And a clock control unit including a frequency mapping module for setting a clock frequency corresponding to the state to be transitioned from a table as a driving frequency, and a driving module for operating the clock generator according to the driving frequency.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention.

1 is a structural diagram of a clock control apparatus according to an embodiment of the present invention.

As shown in FIG. 1, a clock control apparatus according to an embodiment of the present invention includes an application software processing unit 10 and a clock control unit 20 for monitoring a driving state of a plurality of application software for driving a corresponding electronic device. It may include, the clock generating unit 30 may further include.

The application software processor 10 monitors the software driving module 11 for driving the predetermined application software 40, the monitoring module 12 for monitoring the state transition of the driven application software according to the clock signal being applied, and the state transition is monitored. The transition state notification module 13 for notifying the clock control unit 20 and the state transition for instructing the state transition of software from the clock control unit 20 to the driving module 11 in response to the response signal for the state transition notification. Instruction module 14 is included.

The application software 40 according to the embodiment of the present invention is embedded in a DSP, and is configured in the form of a finite state machine (FSM) to divide the operation of the software into states. The amount of DSP calculation required for each state of such software may be different. At low calculations, the DSP will be lightly loaded, so even at low clocks, the DSP will have no problem processing the application software in a timely manner. In addition, a higher computational load will require a higher DSP load, requiring a relatively high clock. Therefore, in the embodiment of the present invention, the clock control unit 20 described below has an appropriate clock frequency value corresponding to the DSP load required according to each state of the application software in the form of a mapping table.

Meanwhile, the clock generator 30 outputs a clock signal of a corresponding frequency according to the applied frequency control signal, and in particular, generates and outputs a clock signal having a clock frequency within a frequency range in which the DSP can operate.

The clock control unit 20 selects a predetermined frequency according to the transition of the driving state of the application software 40 and outputs the frequency control signal. To this end, the clock control unit 20 may transition from the frequency mapping table when a software state transition is notified from the mapping table storage module 21 and the application software processing unit 10 in which operating frequencies are mapped for each application software state. And a clock driving module 22 for providing a frequency control signal corresponding to the found requested clock frequency to the clock generator 30.

The frequency mapping table stored in the storage module 21 may be implemented with a structure as shown in FIG. 2. 2 shows an example of a mapping table configuration. Among the required clock frequencies may be the highest clock frequency and the lowest clock frequency at which the DSP can operate, and the configuration of this mapping table may vary depending on the nature of the application software. Therefore, the mapping table is stored for each application software, and each mapping table is stored with the clock frequency required for each state.

In the embodiment of the present invention having such a structure, the clock control unit 20 and the clock generation unit 30 may be implemented separately from the DSP, for example, the DSP is the application software processing unit 10, the clock control unit 20 It may be configured to include only) or may be configured to include only the application software processing unit 10. 3 is a diagram illustrating an implementation of a DSP according to an embodiment of the present invention. As shown in FIG. 3, in the exemplary embodiment of the present invention, the application software processing unit 10 and the clock control unit 20 exist in the DSP 100 in the form of software.

Next, a clock control method according to an exemplary embodiment of the present invention will be described based on the structure.

4 is a flowchart illustrating a clock control method according to an exemplary embodiment of the present invention.

First, the monitoring module 12 of the application software processing unit 10 monitors whether a state transition is required in the FSM-based application software (S100). When the current state is monitored to be transitioned while the predetermined application software is being driven, the state transition notification module 13 notifies the clock control unit 20 that a state transition is to be generated in the software (S110 to S120). In this case, the state transition notification module 13 provides the clock control unit 20 with a signal including the first identification number of the corresponding application software and the second identification number of the state to be transitioned. The state transition indicating module 14 drives the timer (S130). In this case, the timer is driven so as not to fall into a dead lock state waiting for an indefinite response when the response is not received from the clock control unit 20 after notifying the state transition schedule.

On the other hand, when the state transition of the predetermined application software is notified from the application software processing unit 10, the frequency mapping module 22 of the clock control unit 20 extracts the first and second identification numbers included in the notification signal, respectively. After that, the storage module 21 finds the frequency mapping table corresponding to the application software, and determines whether there is a state corresponding to the second identification number in the found frequency mapping table (S140 to S150).

The frequency mapping module 22 finds the clock frequency required in the transition state in the mapping table and provides the clock driving module 23 to the clock driving module 23 when the transition requested state exists in the mapping table, and the clock driving module 23 generates a clock. The drive of the unit 30 is set to the corresponding frequency (S160 to S170). That is, the frequency control signal corresponding to the clock frequency is transmitted to the clock generator 30, and the clock generator 30 generates a clock signal corresponding to the clock frequency according to the frequency control signal (S180).

Thereafter, the clock driving module 23 notifies the application software processing unit 10 that the clock frequency change is completed according to the state to be transitioned, and thereafter returns from the application software processing unit 10 to the state waiting for the scheduled notification (S190). ).

On the other hand, if there is no state corresponding to the second identification number in the frequency mapping table found in step S150, the frequency mapping module 22 of the clock control unit 20 is determined to be a kind of error state is required The clock frequency is set to the maximum clock frequency (S200). This is because it is not possible to determine what is the optimal clock frequency for the current state transition. This is to set the maximum clock frequency to ensure stability in the operation of the DSP.

The clock driving module 23 operates the clock generator 30 at the maximum clock frequency, notifies the application software processing unit 10 that the clock change is completed, and then returns to the state waiting for the scheduled notification.

According to the clock control, the state transition indicating module 14 of the application software processing unit 10 instructs the state transition when the clock control unit 20 is notified that the change of the clock frequency according to the predetermined transition state is completed (S210 to S220). Accordingly, the driving module 11 shifts the operation state of the application software to the corresponding state and causes the application software to operate in the transitioned state according to the clock signal generated from the clock generator 30.

On the other hand, if the state transition indicating module 14 of the application software processing unit 10 is not notified of the completion of the clock frequency change from the clock control unit 20 so that the timer expires (S230), the state transition instruction without changing the clock frequency is started. Directed to the drive module 11. Thereafter, the application software processing unit 10 returns to the initial stage of monitoring whether or not the state of the software transitions.

The method described above may be implemented in the form of a program stored in a computer-readable recording medium. The recording medium may include any kind of recording device that stores data that can be read by a computer. For example, a CD-ROM, a magnetic tape, a floppy disk, and the like may be used. Included is implemented in the form of).

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

According to the exemplary embodiments of the present invention described above, power consumption can be reduced by allowing the application software to operate at a lower clock as required for real time operation of the application software.

In particular, it is possible to reduce power consumption more effectively than in the prior art, which uses a fixed clock frequency irrespective of the clock frequency required for the application software to operate in real time. Therefore, there is an effect that a low power consumption device can implement a communication device of the software reconfigurable SDR concept using a digital signal processing processor chip.

Claims (9)

In the clock control method for controlling the clock signal generation for the operation of the digital signal processing processor, a) monitoring a state transition of application software running on said digital signal processing processor; b) if the state transition of the application software is monitored, finding a clock frequency according to the state to be transitioned from the mapping table to which the clock frequencies required for each application software state are mapped and setting the driving frequency; And c) driving a clock generator for generating a clock signal according to the driving frequency to generate a clock signal corresponding to the frequency; Clock control method comprising a. The method of claim 1 Step b) Determining whether a mapping table corresponding to a state transition of the monitored application software exists; If the mapping table exists, finding a clock frequency according to the transition state from the mapping table and setting the clock frequency to a driving frequency of the clock generator; And Setting the maximum clock frequency to a driving frequency of the clock generator when the mapping table does not exist Clock control method comprising a. In the clock control device for controlling the operation of the clock generator for generating a clock signal for the operation of the digital signal processing processor including a plurality of application software, A state transition module for monitoring a state transition of the application software, and An application software processor including a state transition notification module for outputting a notification signal corresponding to the state transition being monitored; And A storage module that stores a frequency mapping table in which clock frequencies required for each state are mapped to each application software. A frequency mapping module for finding a frequency mapping table corresponding to the application software from the storage module according to the notification signal, and setting a clock frequency corresponding to the transition state from the frequency mapping table as a driving frequency; and A clock control unit including a driving module to operate the clock generation unit according to the driving frequency; Clock control device comprising a. The method of claim 3, And the frequency mapping module sets the driving frequency to a maximum clock frequency when there is no frequency mapping table for the application software or there is no state to be transitioned to the frequency mapping table. The method according to claim 3 or 4 And the notification signal comprises an identification number of an application software and an identification number corresponding to a state to be transitioned. The method according to claim 3 or 4 The frequency mapping module notifies the application software processor of the change of the clock frequency of the clock generator according to the transition state. And the application software processing unit further comprises a state transition indicating module for instructing a state transition to the application software when the clock frequency change is completed. The method of claim 6 The state transition instructing module drives a timer when the notification signal is transmitted to the clock control unit, and when the timer driving is completed, the clock control instructing the state transition to the application software regardless of whether the clock frequency change is completed or not from the clock control unit. Device. The method according to claim 3 or 4 The application software is a clock control device based application software based on FSM (finite state machine). The method according to claim 3 or 4 And the clock control device is included in a digital signal processing processor.

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