KR100593567B1 - Vertical Interconnect Process for Silicon Segments with Dielectric Insulation - Google Patents

Abstract

The present invention provides an apparatus for vertical interconnection of silicon segments. Each segment has a plurality of adjacent dies located on a semiconductor wafer. Multiple dies on the segment are interconnected on the segment using one or more metal interconnect layers extending to all four sides of the segment to provide edge bonding pads for external context points. After the dies are interconnected, each segment is cut from the wafer backside using an oblique cut to provide an inwardly inclined edge wall on each segment. After the segments are cut from the wafer, the segments are placed on top of each other to form a stack. Vertically adjacent segments of the stack are electrically interconnected by providing an electrically conductive epoxy on one or more sides of the stack. Inwardly inclined edge walls of each segment of the stack provide a recess for the electrically conductive epoxy to access the lateral circuits and edge bonding pads on each segment. An insulating coating is attached to the die to provide a conformal coating that protects and insulates the die and may be removed from the area on the bonding pads so that the laser removes the insulating coating to provide electrical connection to the bonding pads.

Description

VERTICAL INTERCONNECT PROCESS FOR SILICON SEGMENTS WITH DIELECTRIC ISOLATION}

FIELD OF THE INVENTION The present invention relates to an apparatus for stacking and interconnecting silicon segments, and more particularly to stacking segments having a plurality of dies and sloped edge walls and segmenting on the edges of the stack using an electrically conductive epoxy. And an apparatus for interconnecting them.

The present invention is a partial priority application of co-pending application No. 08 / 265,081, filed June 23, 1994, entitled "Vertical Interconnect Process for Silicon Segment", the applicant of this application Is the same as the applicant of the above, and the application is incorporated herein by reference.

For many years, electrical devices such as transistors and integrated circuits have been fabricated using wafers of semiconductor materials including silicon and germanium. Integrated circuits are provided on a wafer using a variety of techniques known for etching, doping, and wiring. The individual integrated circuits provided on the wafer are called dies, which include contact points called bonding pads for electrical connection with the outside. Typically, the dies on the wafer are separated from each other by cutting the wafer along the boundary that forms the die. Once the dies are cut from the wafer, they are called chips and packed for use. In recent years, the proliferation of one or more powerful electronic systems has increased the need for high density integrated circuit packages.

Methods for fabricating high density packages are attempting to fabricate the entire computer system on a single wafer using wafer scale integration (WSI) technology. WSI technology attempts to interconnect dies by wiring all dies on the wafer laterally using wires. However, many wires must be made extremely fine to make the necessary interconnects between dies, which is difficult to manufacture.

A second method for manufacturing a high density package is to physically stack the chips vertically to reduce the area needed to place the chips on the circuit board. Single chip stacking techniques mount individual dies on ceramic carriers, encapsulate the dies and carriers, and stack the carriers to form a stack on a printed circuit board. In this technique, all dies in the stack are interconnected by connecting the leads of the die to the printed circuit board through the metal pins. This approach results in a significant number of pins on the circuit board, reducing the reliability of the circuit, because the number of pins increases the likelihood that one of the plurality of pins may be disconnected from the board.

Another chip stacking method using a more complex process for stacking dies is disclosed in US Pat. No. 5,104,820, filed April 14, 1992. As shown in FIG. 1, the method deforms the individual chips 10 such that the individual chips 10 are stacked by adding a metallization pattern called rerouting leads to the wafer surface. The rerouting leads 12 extend from the bonding pads 14 on the chip 10 to the newly formed bonding pads 11 and all rerouting leads 12 are arranged to terminate on one side of the modified chip 10. . As indicated by the dotted lines, each modified chip 10 is cut from the wafer and assembled into a stack (not shown). The stack is assembled such that all leads 12 of the modified chip 10 are aligned along the same side of the stack. The stack side with the leads 12 is etched and polished so that the cross section of the leads 12 on each chip 10 that are altered can be accessed. After the lid 12 is exposed, a metallization layer is attached to the lid 12 along the stack side to electrically connect each modified chip 10 in the stack. The laminate part is mounted and connected to a substrate to which a normal circuit is connected.

The method of rerouting leads provides an improvement in circuit density over the prior art, but is complex and expensive. In addition, as shown in FIG. 1, the rerouting leads 12 extend on five adjacent dies 15 to 19, which are broken when the modified chip 10 is cut from the wafer. In this method, five die are sacrificed every changed chip 10.

Another method of fabricating a high density circuit manufactures stacks from the entire wafer, not individual chips, to form a wafer array. In some devices, wafers of the stack are electrically interconnected using a solid vertical column of conductive feed-through of a metal such as copper. The use of solid feedthroughs to interconnect the wafers can cause damage to the wafer array by the difference in coefficient of thermal expansion during the thermal cycle. This also makes the process expensive and difficult to separate wafers for repair.

For example, U.S. Patent 4,897,708, registered June 30, 1990, and U.S. Patent 4,954,875, registered September 4, 1990, disclose other methods for interconnecting wafer stacks. In these methods conical through holes are provided in each wafer in the stack to expose the bonding pads on the wafer. Wafer bonding pads in the stack are electrically connected by filling the through holes with an electrically conductive liquid or inserting electrically conductive flowable materials into the through holes, providing continuous vertical electrical connection between the wafers. While avoiding the disadvantages of using solid vertical columns of metal to interconnect wafers, the use of electrically conductive liquids and conductive materials requires specific tools for filling through holes. In addition, in some applications, it may not be desirable to use the entire wafer stack due to the size limitations of the electrical device.

It is therefore an object of the present invention to provide an improved apparatus for stacking and interconnecting silicon segments.

In one embodiment of the present invention, the present invention provides an apparatus for vertically interconnecting a silicon segment stack. Each segment includes a plurality of adjacent dies on a semiconductor wafer. Multiple die on the segment are interconnected on the segment using one or more metal interconnect layers extending to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the dies are interconnected, each segment is cut from the wafer backside using oblique cutting to provide four inwardly inclined edge walls on each segment.

After the segments have been cut from the wafer, the segments are placed on top of each other to form a stack that is distinguished between the stack of individual chips and the entire wafer stack. Segments vertically adjacent within the stack are electrically interconnected by attaching lines to one or more sides of the electrically conductive epoxy filament or stack. Once the segments are stacked, the edge walls beveled into each segment of the stack provide a recess that allows the electrically conductive epoxy to access the peripheral circuitry and edge bonding pads on each segment. The electrically interconnected segment stack is then mounted on or above the surface of the circuit board and electrically connected to the circuit on the board by adding a trace of electrically conductive epoxy between the bonding pad and the circuit board on the upper segment of the stack. .

According to another aspect of the invention, an insulating dielectric process is used to electrically insulate the entire die edge. An insulating dielectric process provides a conformal insulating coating around the edge of the die to protect and insulate the die.

Other objects, features and advantages of the present invention will become apparent from the following detailed description with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS The drawings, which are attached and combined in the specification, illustrate embodiments of the invention in order to illustrate the main principles of the invention in conjunction with the description.

1 shows a prior art for providing a rerouting lead along one side of a chip.

2 shows a typical silicon wafer including a plurality of dies.

3 shows two segments, each segment comprising a 2 × 2 array die in accordance with the present invention.

4 shows a number of segments placed on a wafer.

5A-5H illustrate multiple cross-sectional views of a wafer, showing multiple layers of material attached to a wafer for interconnecting dies of a segment.

6A and 6B show edge wall profiles of polyimide layers.

7A and 7B illustrate a metal lift-off process for providing metal interconnects on a wafer.

8A shows the segment backside with four sloped sidewalls after the segment has been cut from the wafer.

8B shows the inclined sidewalls and front side of the three segments after being cut from the wafer.

9 illustrates a segment stacking and bonding process in which segments are laminated and epoxy bonded to each other.

10A and 10B illustrate a method for providing a vertical electrical path between stack segments in accordance with the present invention.

11 shows the mechanism by which epoxy traces are distributed along the edge of the stack.

Figure 12 illustrates a signal transfer substrate having a plurality of laminates that are subsurfaces mounted in accordance with the present invention.

13 illustrates a method for electrically connecting a subsurface mount stack to a circuit board.

14 is a partial cross-sectional view of a die in accordance with the present invention having a conformal dielectric coating.

FIG. 15 is a cross-sectional view of FIG. 14 illustrating the use of a laser to remove a portion of a dielectric coating. FIG.

Hereinafter, with reference to the drawings will be described in detail an embodiment of the present invention. The invention will be described in detail with reference to the examples, but these examples should not be understood as limiting the invention. On the contrary, it is to be understood that the invention includes other modifications, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the claims.

VIP process

As described above, the present invention is a partial priority application of US patent application 08 / 265,081, filed June 23, 1994 and co-pending under the name “vertical interconnect process for silicon segments”. An overview of this VIP process will first be described in detail.

With reference to FIG. 2, the vertical interconnect process will be described in detail, starting from the standard wafer 30 provided by the manufacturer. The rectangles on the wafer 30 represent individual die 32 locations on the wafer 30. Wafer 30 is typically reached from the manufacturer with ink dots 34 representing non-functional or defective dies. In an embodiment of the invention, the wafer 30 is made of silicon. However, wafer 30 can be made using other materials, such as gallium arsenide. Typically, die 32 is cut from wafer 30 to provide individual chips such as, for example, memory chips. In accordance with a conventional VIP process, die 32 is not individually cut from wafer 30. Instead, a number of adjacent dies 32 on the wafer 30 are grouped to form a so-called segment 32 as shown in FIG. However, the dies can be cut individually according to the present invention and conventional VIP processes.

3 is a plan view showing two segments 36A and 36B (hereinafter referred to as segment 36) on the wafer 30, where each square represents one die 32. As shown in FIG. Each segment 36 is defined by a vertical boundary 38 and a horizontal boundary 40 where each segment 36 comprises a group of adjacent dies 32 on the wafer 30, thereby providing a specific size and shape. A segment 36 having is obtained. In an embodiment of the invention, segment 36 includes four adjacent dies 32 arranged in a 2x2 matrix as shown. This segment 36 is called a 2x2 segment. However, segment 36 may be arranged in any pattern or arrangement of adjacent dies 32, such as, for example, 1 × 1 segment, 2 × 1 segment, 2 × 4 segment, or 4 × 4 segment die 32. It may include. Each segment 36 is provided with edge bonding pads 42 on one or more sides of the segment 36, which serve as electrical connection points for external connection. Similarly, each die 32 includes internal bonding pads 44 for connecting internal circuitry of the die 32. Individual segments 36 are separated from the wafer 30 by cutting the wafer 30 along a vertical boundary 38 and a horizontal boundary 40, typically referred to as a street. The process of cutting the segment 36 from the wafer 30 will be described in more detail below.

One feature of the VIP process is that the individual dies 32 on the segment 36 are interconnected using multiple layers of die interconnect circuitry. The die interconnect circuit includes a plurality of metal traces oriented in the x and y directions on the surface of the segment 32. The metal traces, referred to as x-interconnect 46 and y-interconnect 48, transfer power and signals from the edge bonding pads 42 of the segment 36 to the selected internal bonding pads 44 of the individual dies 32. It is responsible for communicating.

4 shows a layout of a number of segments 36 across the wafer 30. At the periphery of the wafer 30, the bonding pads of the individual dies 32 (see FIGS. 2 and 3) are routed appropriately to create a 1 × 1 segment 50.

Referring to Fig. 3, ink dots 34 (denoting defective dies) are attached to the metal x- and y-interconnect portions 46 and 48 on the surface of the wafer 30 to interconnect the individual die 32. 2) should be removed first so that the ink dots 34 do not affect the metal interconnects 46 and 48. Ink spot 34 is removed from wafer 30 using a conventional positive resist stripper. Positive resist strippers are well known in the art for dissolving and removing unwanted materials from certain surfaces without damaging the original surface. After the ink spots 34 are removed, metal interconnects 46 and 48 are attached to the wafer 30 during the wafer interconnect process.

5A-5H, partial cross-sectional views of the wafer 30 are shown. As described above, the surface of the wafer 30 has a plurality of internal bonding pads 44 (see FIGS. 2 and 3) belonging to the individual die 32 and a plurality of external bonding pads 42 belonging to the segment 36. Included. In order to insulate the die 32 from the metal interconnect to be attached to the wafer 30 surface, a polyimide layer 60 is first deposited on the wafer 30 as shown in FIG. 5B. Although the wafer manufacturer provides a protective film on the surface of the wafer 30 from which the circuit must be insulated, the polyimide layer 60 ensures that there are no holes in the protective film. The polyimide layer 60 also helps to fill the streets 38, 40 (see FIG. 3) between the dies 32 of the wafer 30. In an embodiment of the present invention, the polyimide layer 60 has a thin polyimide layer on the wafer 30 with a polyimide centered on the wafer 30 and the wafer 30 being about 2 microns thick on a spin motor. 60) are attached by a standard spin coating process that rotates horizontally to provide 60).

5C, after the surface of the wafer 30 is coated with a polyimide layer 60 or other insulating material, the polyimide layer 60 is removed from the surface of the wafer 30 on the bonding pads 44, 42. Removed. In a preferred embodiment, polyimide layer 60 is removed over bonding pads 44 and 42 using standard photolithography processes.

During the photolithography process, a layer of photosensitive material called positive photoresist is deposited on the surface of the polyimide layer 60 and baked. Next, a mask having an opening that forms the position of the bonding pads 44 and 42 on the wafer 30 is superimposed on the photoresist using a conventional alignment device. Ultraviolet irradiation light is applied to the mask and uncoated portions of the photoresist on the bonding pads 44 and 42 are exposed to the light. The exposed photoresist is then peeled off from the bonding pads 44 and 42 and developed in the diluted developer. After the bonding pads 44 and 42 are exposed, the remaining photoresist is removed from the wafer 30 using acetone or other positive photoresist stripper material. Acetone cleans the photoresist but does not damage the polyimide layer 60.

After the photoresist is removed, the wafer 30 is baked to cure the polyimide layer 60. Typically, the polyimide is cured at 400 ° C. for half an hour. In a preferred embodiment of the present invention, the polyimide layer 60 is cured at 350 ° C. for 6 hours to reduce the likelihood of damage to the circuit on the wafer 30.

Referring to FIGS. 6A and 6B, in a preferred embodiment, as shown in FIG. 6A, the polyimide in the insulating layer 60 creates a rounded edge wall 70 in the region where the polyimide layer 60 has been removed. Is used. The rounded edge wall 70 of the polyimide layer 60 is desirable to facilitate deposition of the metal layer 48 to be attached to the polyimide layer 60. In contrast, the photoimageable polyimide 61 provides an edge wall with angled edges 72 causing discontinuities in the metal layer 49 as shown in FIG. 6B.

Referring to FIG. 5D, after the polyimide layer 60 is opened on the bonding pads 44 and 42, the next step in the vertical interconnect process is that the first metal layer 48 is attached to the wafer 30 so that the segment 36 is attached. Is a metal lift-off process that electrically interconnects each die 32 located on the top of the die. The first metal layer 48 deposited on the wafer 30 connects the bonding pads 44 and 42, which corresponds to the metal y-interconnect 48 of FIG. 3. The path of the metal y-interconnect 48 of the wafer 30 is determined using a standard photolithography process.

7A and 7B, the first step of the metal lift-off process is to attach the lift-off photoresist layer 74 onto the polyimide layer 60. In a preferred embodiment, a commercially available image reversal photoresist is deposited on the wafer 30 in a known manner. Photoresist 74 is then removed in the selected area to form a metal y-interconnect 48 path. An overhang edge, in which the image reversal photoresist 74 is referred to as a backing or reentrant edge wall 76, is made along the metal y-interconnect 48 path as shown in FIG. 7A.

After the selected region of the photoresist 74 has been removed to form a metal y-interconnect 48 path, a standard sputtering apparatus (shown) that the wafer 30 uses to deposit the metal layer 48 over the entire wafer 30 (not shown). Not located). In a preferred embodiment, metal layer 48 comprises a sandwich of chromium, titanium-tungsten, and gold. Chrome and titanium-tungsten are first combined with gold for adhesion, but other metal sandwiches are also possible. In a conventional VIP process, about 2000 kW of chromium, 500 kW of titanium-tungsten, and about 1200 kW of gold are deposited on the wafer 30. In an embodiment of the present invention, about 6000 GPa of gold is deposited on the wafer 30.

Once metal deposition is performed, the remaining photoresist 74 is removed from the wafer 30 surface. The photoresist is typically removed by dipping the wafer 30 in another positive photoresist stripper that dissolves acetone or photoresist 74. Referring to FIG. 7B, as the photoresist 74 is dissolved, the metal layer 48 is removed from the surface of the first polyimide layer 60, leaving the metal interconnect 48 (see FIG. 3). The purpose of the reentrant edge wall 76 is to allow acetone to flow around the edge of the metal y-interconnect 48 to effectively dissolve the photoresist 74.

After acetone is removed from the photoresist 74, the wafer 30 is baked to evaporate the acetone absorbed in the polyimide layer 60. After this step, a layer of gold remains on the surface of the polyimide layer 60 forming the y-interconnect 48 in contact with the bonding pads 44 and 42 as shown in FIG. 5D.

After the metal y-interconnect 48 is provided on the wafer 30 surface, a second metal layer 46 is formed on the wafer by essentially repeating the process described above. The second metal layer 46 corresponds to the x-interconnect 46 shown in FIG.

Referring to FIG. 5E, second polyimide deposition is performed to form the polyimide layer 80 on the wafer 30. The second polyimide layer 80 is attached in the same manner as in the first polyimide layer 60 but need not be thick. After the second polyimide layer 80 is attached, the second layer at the point on the metal y-interconnect 48 that electrically connects the metal x-interconnect 46 as shown in FIG. 5F ( 80). Once the segments 36 are stacked, edge bonding on each segment 36 such that the second polyimide layer 80 and the second metal interconnect 46 layer electrically connect the edge bonding pads 42. It is removed from the pad 42.

In another embodiment, the first metal layer 48 is used to connect the edge bonding pads 42 instead of the second metal layer 46. After the second polyimide layer 80 is removed at a selected point on the wafer 30, the second polyimide layer 80 is undesirable between the gold interconnect 48 and the aluminum bonding pads 44, 42. The insulating material cures at low temperatures to prevent possible interactions.

After the second polyimide deposition, a second metal lift-off process is performed to form the interconnect 46 of the second layer as shown in FIG. 5G. Again, the image reversal photoresist is deposited on the wafer 30 and removed at the position forming the gold interconnect 48 path of the second layer on the wafer 30. As described above, this process creates a photoresist layer that forms a path with reentrant edge walls. In a preferred embodiment, a metal layer comprising chromium, titanium-tungsten, and gold sandwich is sputter deposited on the photoresist. Chromium is unnecessary in the second layer 48 but can be used for standardization of the manufacturing process. After the second gold deposition has been performed, a lift-off step is performed to remove unwanted photoresist and metal, leaving the x-interconnect 46 of FIG.

After the second metal layer 46 is deposited, a third polyimide layer 90 is deposited on the wafer 30, as shown in FIG. 5H, to protect the metal x-interconnect 46 from scratches and to external Act as a mechanical shield for the world. The third polyimide layer 90 is removed around the edge of each segment 36 to expose the edge bonding pads 42 that are later electrically connected with the edge bonding pads of the other segments. Conventional photoimageable polyimide 90 or non-photoimageable material may be used to protect the metal x-interconnect 46.

As shown in FIG. 5H, the first polyimide layer 60 protects the circuit on the wafer 30 with the first metal interconnect 48 layer in contact with the bonding pads 44, 42. The second polyimide layer 80 insulates the metal interconnect 48 of the second layer from the metal interconnect 36 of the first layer except where the two layers are in contact. Finally, the third polyimide layer 90 insulates and protects the metal interconnects 48 of the second layer.

Two layers of metal interconnects 46 and 48 provided by the wafer interconnect process (VIP) add flexibility in routing lines along the wafer 30 to interconnect die 32 on each segment 36. Connect. Interconnecting the dies 32 on the segments 36 and then stacking the segments 36 is a conventional method of cutting individual chips from the wafer 30, stacking the chips, and interconnecting the chips on a circuit board. It is much cheaper and more reliable than the technique.

After the wafer 30 interconnection process, a segment formation process is performed on the wafer 30. Referring again to FIG. 3, the wafer 30 is cut into individual segments 36 by cutting along the vertical and horizontal streets 38, 40 between the segments 36. After segment 36 is cut from wafer 30, the segments will be placed in a stacked structure. In order to reduce the overall size of this structure, the material is polished from the back side of the segment 36 and first thinned. To assist in this thinning process, the entire wafer 30 is thinned before the segment 36 is cut from the wafer 30. The thinning process reduces the wafer 30 and segment 36 heights from 25 millimeters to about 8-10 millimeters.

Typically, the wafer 30 is cut from the front on which the circuit is placed so that the circuit is easily visible and not damaged in the sawing process. However, in the present invention, the wafer 30 is cut along the streets 38 and 40 on the backside of the wafer 30 using oblique cutting. 8A shows segment 36 back surface 100 after segment 36 has been cut from the wafer using a bevel cut. As shown, the oblique cut provides the segment 36 with an edge wall 102 that is inclined inwardly on all four sides of the segment 36.

In a conventional VIP process, to cut the wafer at the backside 100, a pattern of streets 38, 40 forming segment boundaries is provided on the backside 100 of the wafer 30 to induce a saw. do. A pattern of segment boundaries is provided on the backside 100 that places the wafer 30 in a device including a video camera and a felt-tipped writing device. The wafer is mounted so that the front surface of the wafer 30 faces the camera while the writing device is in contact with the back surface 100 of the wafer 30. An image of the front side of the wafer 30 is displayed on the monitor and the operator draws the pattern on the backside 100 of the wafer 30 by moving the wafer 30 below the writing device along the pattern of segment boundaries.

Optionally, in a conventional VIP process, a pattern of segment boundaries may also be provided on the backside 100 of the wafer 30 using conventional techniques. In this process, the backside 100 of the wafer 30 is coated with photoresist, the front side of the wafer 30 is irradiated with infrared light so that a circuit appears on the backside 100 of the wafer 30, and the pattern of segment boundaries It is developed on the surface of the backside 100 of the wafer 30 so that the saw can be aligned and guided.

After the pattern of segment boundaries is provided on the wafer 30 backside 100 and before the wafer is sawed, a tape layer is attached to the front side of the wafer 30 to support the segment 36 during sawing. After the front side of the wafer 30 is tapered, oblique cutting is performed along the segment boundary on the back side 100 of the wafer 30. In a preferred embodiment of the present invention, the segment edge wall 102 is made with a 45 degree angle by oblique cutting. After the segment 36 is cut, the tape is carefully removed from the front side of the wafer 30 and the segment 36 is cleaned to remove residues from sawing processes and taping.

FIG. 8B shows three segments 36 positioned vertically on top of each other after the segments are cut from the wafer 30 and just before the segments are permanently assembled and stacked. As shown, each segment 36 front face 104 includes metal interconnects 48, 46 and edge bonding pads 42. Once the segments 36 are assembled into a stack, the edge bonding pads 42 of the segments 36 will be electrically connected with the edge bonding pads 42 of the segments 36 perpendicular to the stack. The purpose of the inclined edge wall 102 is for the vertical electrical connection between the edge bonding pad 42 of one segment 36 and the edge bonding pad 42 of the segment 36 directly under the first stack. To provide adequate clearance.

As with the conventional VIP process described above, after clarifying the electrical connections, the backside 100 of the segment 36 and the beveled edge 102 are insulated using a sputtered nitride process. The sputtered nitride process is similar to metal film sputtering, except that silicon nitride is sputtered on the backside 100 of the segment 36 instead of metal. Silicon nitride isolation is necessary to prevent noise and interference signals from being absorbed into the silicon substrate base of the die 32 on the segment 36.

After the segment 36 is cut from the wafer 30 and insulated, the function of the circuit on the segment 36 is checked. Since a portion of the die 32 in the state of the wafer 30 in the prior art does not operate and the defective die is discarded without being cut from the wafer 30, the defective die must be disconnected in the die 32 functional check. . The defective die may be disconnected by using a laser to vaporize the top layer of metal interconnect 46 connected between the edge bonding pad 42 of the segment 36 and the circuit of the defective die. The defective die may be disconnected by mechanical polishing or electrical melting of the top layer of the metal interconnect 46. Once the top layer of metal interconnect 46 has opened between the edge bonding pad 42 of the segment 36 and the circuit of the defective die, the defective die is no longer electrically connected to the segment 36. .

Apart from disconnection of the defective die, each segment 36 is specifically made such that a decoding circuit that can be connected with the completed stack can access each segment 36. In a conventional VIP process, each segment 36 is made specifically during a process called level programming in which multiple control signals are burned on each segment using a laser. Referring again to FIG. 3, a number of control signals are provided on each segment by burning a specific pattern on the control bonding pads 106 on each segment 36, although the specific pattern is also an electrical blowing fuse. It can be formed by.

After each segment 36 is made specific to each other, the segment 36 is programmed. For purposes of initiation, programming refers to the process of routing circuitry such that for programming, the redundant function die 32 is replaced with a faulty die that is disconnected. This is accomplished by providing a replacement die 32 that properly controls the original intended signal for the disconnected die. Programming is required to allow a computer, such as a computer, to access the disconnected die in the stack once the segments 36 are stacked and operated. Thus, the segment 36 with the defective die must be programmed so that the functional die 32 is accessed instead when an attempt is made to access the defective die in the stack. Actual programming of segment 36 takes place during fabrication of the stack, as described below.

Referring to FIG. 9, there is shown a segment adhesive fixture 110 in which the stack 112 is assembled during the stacking process in which the segments 36 are stacked and bonded to each other. In a conventional VIP process, during the lamination process, the stack 112 is assembled using six adjacent segments 36 to provide six logic levels. The stack 112 is assembled by providing an epoxy 114 film between each pair of adjacent segments 36 and placing the next segment 36 front face 104 on the alignment fixture 116. The alignment fixture 116 squeezes the stack against the horizontal plane against the fixed wall of the fixture and uses three closed-cell urethane rubber stamps 118, 119, 120 in a vertical plane with respect to the base of the fixture. The laminated part 112 is crimped | bonded. Next, the lamination part 112 is cured at 120 ° and remaining in the fixed part solidifies the lamination part 112. The cure cycle consists of a 15 minute stabilization period, 60 minutes of cure, and 10 minutes of cooling. In the VIP process, the segments 36 forming the stack 112 of the present invention have advantages over the prior art in which the individual dies 32 are stacked because the segments 36 can have various thicknesses and can be stacked in any order. .

After the stack 112 is solidified, the edge bonding pads 42 (see FIG. 8B) on each segment 36 are electrically vertically connected to the stack 112 to provide the electrically functional stack 112. . Conventional methods of vertically connecting elements for stacking connect an element with a metal rod, provide a plurality of vias in the element and insert an electrically conductive material into the via or fill the via with a conductive liquid to provide an electrical path between the stack elements. How to do this.

10A and 10B, a method according to the present invention for providing a vertical electrical path between segments 36 of stack 112 is shown. 10A shows the stack 112 from the back side 100 of the segment 36 with the stack located on the side. 10B shows the appearance of the stack 112 from the front face 104 of the segment 36 in which the stack is vertically located. In order to provide a vertical electrical path between the segments 36 of the stack 112, a silver filled conductive epoxy trace 130 is provided by the dispensing mechanism 132 along the sloped edge wall 102 of the segment 36. Is distributed. The dispensing mechanism 132 moves in the x and y directions and is aligned with the outer bonding pads 42 of the segment 36 to position the epoxy traces on the stack 112. Epoxy traces 130 are attached at preprogrammed positions on all four edges of the stack 112 and the epoxy traces 130 flow to connect the exposed metal of the bonding pads 42 vertically. The inclined edge wall 102 of the segment 36 facilitates access to the outer bonding pads 42 by the epoxy traces 130. The use of sloped edge walls 102 and epoxy traces 130 of the VIP process is an advantage over the use of metallization layers to provide vertical electrical connections to laminates in the prior art.

As shown in FIGS. 10A and 10B, the epoxy traces 130 are selectively distributed to different layers of the stack 112 according to preliminary programming. Various epoxy traces 130 form circuit paths for specific devices and route circuits around disconnected defective dies. In the case where the segments 36 are stacked on top of each other to form an assembled stack 112, each die 32 position on the segment 36 forms a vertical row of the stacks 112. . For example, if each segment 36 in the stack 112 includes six dies 32, the stack 112 includes six vertical rows of dies 32. In order to include functional circuits such as, for example, memory circuits, a predetermined number of functional dies 32 are required for each vertical column of segments 36. In a conventional VIP process as described above, the circuit of stack 112 comprising six segments is routed during programming to provide four functional dies 32 in each column of the stack. However, another configuration is possible according to the present invention. For example, eight to twelve adjacent segment stacks may be configured to form eight logic levels of die in each column of the stack.

Referring to FIG. 11, the mechanism by which the epoxy traces 130 are distributed is shown. Dispensing mechanism 140 includes a rotating indexing vacuum chuck 134, a dispensing mechanism 132, a sealed rotating vacuum joint 138, a motor 142, and a 90 ° indexing mechanism 144. The sealed rotating vacuum joint 138 is coupled to a vacuum pump (not shown) to operate to create a vacuum at the end of the vacuum chuck 134 located below the dispensing mechanism 132. The stack 112 is positioned horizontally on the vacuum chuck 134, and the chuck 134 supports the stack 112 on the stack front 104 by vacuum. After the stack 112 is positioned above relative to the chuck 134, the dispensing mechanism 132 moves over one edge of the stack 112 and down one side of the stack 112 as described above. Distribute the pre-programmed channel of epoxy traces 130. The dispensing mechanism 132 is moved and the vacuum chuck 134 is rotated 90 ° by the 90 ° indexing mechanism 144 so that the epoxy can be dispensed along the other edge of the stack 112. This process is repeated until all the edges of the stack 112 are epoxy applied. In an embodiment, the epoxy dispensing mechanism 132 is a 30 gage, Luer-tip 5cc hypodermic syringe with 1/1000 inch resolution and mounted on a programmable robot (not shown).

After the epoxy traces 130 have been dispensed, because the epoxy 130 is wet, the stack 112 is removed from the chuck 134 and placed in a support area with specific handling. An epoxy bonded segment stack 112 is then placed in a convection oven for curing, which consists of 15 minutes preheating, 60 minutes curing and 10 minutes cooling. Once the electrical function of the stack 112 is tested, the stack 112 process is complete and the stack 112 is ready for mounting on a circuit receiving substrate such as, for example, a printed circuit board.

In a conventional VIP process, the stack 112 can be connected to the circuit board by a sub surface that mounts the stack 112 to the circuit board. 12, a cross-sectional view of a circuit board 150 having a plurality of stacks 112 mounted to a subsurface in accordance with a VIP process is shown. In order to subsurface the stacked portion 112 on the circuit board 150, a plurality of holes 154 slightly larger than the circumference of the stacked portion 112 are opened in the circuit board 150. After the hole 154 is opened in the circuit board 150, the circuit board 150 is located in the clamping fixture 152. Next, the stack 112 is placed in the hole 154 of the circuit board 150 such that the front surface 104 of the upper segment 36 of the stack 112 is coplanar with the printed circuit board 150. Will be located. The stack 112 is fixed in place by the following operation of applying a small amount of rapid cure position epoxy (not shown) at various locations around the stack 112.

The stack 112 may be mounted on top of the circuit board by epoxy, but by subsurface mounting the epoxy is attached to the circuit board around the stack 112 and the epoxy is applied to the vertical side of the stack 112. Problems that may occur when attaching are resolved. Subsurface mounting of the stack 112 in the circuit board 150 allows the coefficient of thermal expansion and reduces the overall height of the stack 112 on the circuit board 150 so that the stack 112 is heightened at an increased density. Is increased, providing many advantages, including the ability to simplify the electrical connection between the stack 112 and the circuit board 150 as described below.

Referring to FIG. 13, a method for electrically connecting the stack 112 to the circuit board 150 is shown for a conventional VIP process. After attaching the positioning epoxy 158 so that the stack 112 is secured to the circuit board 150, the stack 112 allows computer circuitry to access the die 32 on each level of the stack 112. And is electrically connected to the metal traces 160 on the circuit board 150. Each stack 112 is positioned such that the edge bonding pads 42 around the upper segment 36 match the position of the metal traces 160 on the circuit board 150. To bridge the gap between the bonding pads 42 and the metal traces 160 on the circuit board 150, a silver filled conductive epoxy whisker 162 utilizes a dispensing mechanism 132 to each bonding pad ( From 42 to the opposite metal trace 160 on the circuit board 150. As shown in FIG. 13, the positioning epoxy 158 used to secure the stack 112 to the circuit board 150 is attached so as not to interfere with the conductive epoxy whisker 162. One feature of the VIP process is made by the conductive epoxy whisker 162 in which the electrical connection between the stack 112 and the metal traces 160 on the circuit board 150 is substantially flush with the circuit board 150. Will be.

The horizontal epoxy whisker 162 of the conventional VIP process is between the circuit board 150 and the edge bonding pads 42 of the upper segment 36 of the stack 112, and the edge bonding pads 42 of the upper segment 36. ) And an electrical connection between the vertical epoxy traces 130 attached under the edge of the stack 112 to interconnect the segments 36. The horizontal and vertical conductive epoxy traces 160, 132 attached to the stack 112 allow the circuitry of the circuit board 150 to be accessed by any segment 36 of the stack 112.

In a conventional VIP process, after segments are vertically interconnected using epoxy traces 130 (see FIGS. 10A and 10B), different program levels may be used to correct errors on any die on segment 36. May be employed at board level 150. The die error is corrected by deselecting the control signal for the defective die at the circuit board level and replacing the signal with the control signal of the functional die 32 in the stack 112. This is accomplished by interconnecting a suitable metal trace 160 on the circuit board 150 with the conductive epoxy whisker 162.

After the epoxy whisker 162 is attached to the circuit board 150, the board 150 assembly is placed in a convection oven for final curing. This curing consists of 15 minutes of preheating, 60 minutes of curing and 15 minutes of cooling. After curing, the board 150 assembly is tested and encapsulated with a polyimide layer. In a conventional VIP process, the completed circuit board 150 assembly of the present invention can be used for a variety of purposes, such as a Personal Computer Memory Card International Association (PCMCIA) card. PCMCIA cards are small credit-card size devices that can be inserted into notebooks and portable computers to provide additional input / output capabilities and increased storage capacity. Stacking in the VIP process can be mounted on a PCMCIA card and used, for example, as an external memory circuit in a notebook computer.

Dielectric insulation process

Having described the detailed aspects of the vertical interconnection process (VIP) described so far in the related patent applications, the dielectric insulation of the present invention will be described in detail below.

One of its features is the use of a dielectric isolation process. The enhanced VIP process uses a dielectric to electrically isolate the entire edge of the die. In the conventional VIP process described above, silicon nitride is used as the insulating dielectric.

Better dielectrics made of polymers can be used. One suitable insulator that can be used for this purpose is Parylene ^TM . The dielectric insulation etch process according to the present invention provides a conformal coating located around the die edge to protect and insulate the die. In an embodiment, the polymer coating is vacuum deposited.

14 shows a cross-sectional view of the die 200 and bonding pads 208 coated with an insulating polymer coating 204 such as Parylene ^™ . Next, in an improved process, a laser is used to remove the polymer. 15 shows a removal area 212 for removing the coating 204 on the bonding pads 208 where electrical connections are made. Conventional VIP processes use silicon nitride which is fragile and can have other problems.

The dielectric insulation process according to the present invention provides a conformal coating 204 around the edge of the die 200 completely. Silicon nitride is deposited in a more directional manner and the edges of the die are not coated in a conformal manner. One problem is that silicon nitride is fragile at the corners because silicon nitride is the same as the hard part of the glass and can break when bent around the edge of the die. The conformal coating according to the invention can be bent at the edge portion of the die.

Another feature associated with the improved VIP process is that once the die 200 of FIG. 14 is conformally coated to have a coating 204, the conformal coating in a location or opening where electrical connection to the bonding pad 208 is desired. Means to selectively remove parts. As shown in FIG. 15, in one preferred embodiment of the present invention, for removing conformal coating 204 in areas where laser 210 is required to make an electrical connection opening with bonding pads 208. It can be used for the purpose. 15 shows a removal area 212 for removing the coating 204 on the bonding pads 208 where electrical connections are made. As described above, a preferred feature of the dielectric insulating etch process is to provide a conformal coating located around the edge to insulate and protect the die.

The foregoing description of specific embodiments of the present invention has been disclosed for purposes of illustration and description. It is to be understood that these descriptions are not intended to be exhaustive or to limit the invention to the precise form disclosed, and that many modifications and variations are possible in the present invention. The embodiments have been selected and described as best illustrating the principles and practical application of the invention, whereby various modifications may be made to suit a particular use intended by one of ordinary skill in the art to which the invention pertains. It is possible to use the embodiment. The scope of the invention is defined by the claims and their equivalents.

Claims (49)

A silicon segment having a plurality of edges forming a segment, wherein A plurality of dies on said segment each comprising a plurality of first bonding pads; A plurality of edge bonding pads located on one or more edges of the segment for external electrical connections; And A layer of one or more metal traces connected between the plurality of first bonding pads to interconnect the die, The metal trace is further connected between the plurality of edge bonding pads and the plurality of first bonding pads to connect the die to the external electrical connections, wherein a conformal dielectric coating is formed on the die. And the conformal coating has openings for forming electrical connections to the bonding pads. The silicon segment of claim 1 wherein the metal traces comprise a sandwich of chromium, titanium-tungsten, and gold. 3. The method of claim 2, wherein the segment further comprises a front side and a back side, wherein the plurality of first bonding pads, the plurality of edge bonding pads, and the layer of metal traces are located on a front side of the segment. Characterized by silicone segment. 4. The silicon segment of claim 3 wherein the edges forming the segment further comprise edge walls, wherein the edge walls and the back surface of the segment are insulated by the conformal dielectric. 5. The silicon segment of claim 4 wherein the edge walls are inclined. A stack comprising a plurality of edges, a plurality of die having circuitry therein, and electrically conductive contact points, each segment disposed vertically on top of each other; First interconnecting means for interconnecting a plurality of dies on the respective segments and connecting the one or more plurality of dies to electrically conductive contact points of each of the segments; Access means for providing access to the electrically conductive contact points on the respective segments; And Electrically interconnecting the electrically conductive contact points on each of the segments in the stack and providing lateral electrical connections to the plurality of die located in the respective segments in the stack. A second interconnection means applied to said access means for A conformal dielectric coating formed on the die, the conformal dielectric coating having openings for forming electrical connections at the contact points. 7. The electrical circuit stack of claim 6, wherein the electrically conductive contact points are located along one or more of the edges of each of the segments. 8. The electrical circuit stack of claim 7, wherein said first interconnecting means comprises a layer of one or more metal traces. 9. The electrical circuit stack of claim 8, wherein said layer of metal traces comprises a sandwich of chromium, titanium-tungsten, and gold. 10. The electrical circuit stack according to claim 9, wherein said access means includes edge walls inclined inward along each of said edges of said segments. 11. The electrical circuit stack of claim 10, wherein said interconnect means comprises an electrically conductive epoxy. 12. The electrical device of claim 11, wherein each of the segments comprises control bonding pads, the segments being made specific to each other by having a specific pattern formed on the control bonding pads of the respective segments. Circuit stacks. 12. The device of claim 11, wherein the segments comprise interconnected functional dies and non-functional dies, the non-functional dies disconnected from the functional dies, and wherein the metal traces on each of the segments indicate that a particular one of the functional dies is selected. And routed to be replaced with a non-functional die. 13. The method of claim 12, wherein the stack includes at least two segments, each of the two segments including at least one die, and wherein the stack comprises at least one vertical row of the dies of the two dies. It is a height, The electric circuit laminated part characterized by the above-mentioned. 15. The device of claim 14, wherein the stack has at least six said segments, each of said six segments comprising at least four said dies, said stack having four vertical rows of said die, and said vertical rows. Each is the height of the six dies, and the electrically conductive epoxy is attached to the six segments such that four functional dies are connected to each of the four vertical rows of the die within the stack. An electric circuit laminated part made into. 16. The electrical circuit of claim 15 wherein the stack comprises 8 to 12 segments, each of which forms four stacks of eight functional dies, including four vertical rows of dies. Laminations. At least one silicon segment having at least three edges forming segments, A plurality of dies on said segment each having a plurality of first bonding pads; A plurality of edge bonding pads located on one or more edges of the segment for external electrical connections; And A layer of one or more metal traces connected between the first bonding pads to interconnect the die, The metal traces are further connected between the plurality of edge bonding pads and the plurality of first bonding pads to connect the die to the external electrical connections, wherein a conformal dielectric coating is formed on the die. Wherein the conformal dielectric coating has openings for forming electrical connections to the bonding pads. At least one silicon segment having at least three edges forming a segment, A plurality of dies on said segment each having a plurality of first bonding pads; A plurality of edge bonding pads located on one or more edges of the segment for external electrical connections; And A layer of one or more metal traces connected between the first bonding pads to interconnect the die, The metal traces are further connected between the plurality of edge bonding pads and the plurality of first bonding pads to connect the die to the external electrical connections, The segment includes an interconnected functional die and a non-functional die, wherein the non-functional die is disconnected from the functional die, and the metal traces on each segment are such that a particular one of the functional die is replaced with the non-functional die. Routed, A conformal dielectric coating is formed on the die and the conformal dielectric coating has openings for forming electrical connections to the edge bonding pads. Electrical circuit stack, A stack of segments located on top of each other, each segment comprising: a segment stack having at least three edges forming an edge of each one of the segments; A plurality of die on the respective segments and each comprising a plurality of first bonding pads; A plurality of edge bonding pads located at one or more of the edges of the respective segments for external electrical connections; And A layer of one or more metal traces connected between the plurality of first bonding pads to interconnect the die, The metal traces are further connected between the plurality of edge bonding pads and the plurality of first bonding pads to connect the die to the external electrical connections, A conformal dielectric coating formed on the die, the conformal dielectric coating having openings for forming electrical connections to the edge bonding pads. Electrical circuit stack, A stack of segments located on top of each other, each segment comprising: a stack of segments having at least three edges, a plurality of die having circuitry therein, and electrically conductive contact points; First interconnecting means for interconnecting the plurality of dies on the respective segments, and connecting one or more of the plurality of dies with one or more of the electrically conductive contact points on the respective segments; Access means for providing access to electrically conductive contact points on the respective segments; And The electrical interconnections on the electrically conductive contact points on each of the segments in the stack and for providing peripheral electrical connections to the plurality of die located at the respective segments in the stack. A second interconnect means applied to the access means, The segment includes an interconnected functional die and a non-functional die, wherein the non-functional die is disconnected from the functional die, and the metal traces on each of the segments allow a particular one of the functional die to be replaced with the non-functional die. Routed, A conformal dielectric coating is formed on the die, the conformal dielectric coating having openings for forming electrical connections to the edge bonding pads. At least one silicon segment having multiple edges forming a segment, At least one die on the segment; And At least one bonding pad located at one or more of the edges of the segment for vertical external electrical connections, A conformal dielectric coating is formed on the die, the conformal dielectric coating having openings for forming electrical connections to the edge bonding pad. At least one silicon segment having multiple edges forming a segment, At least one die on said segment having at least one first bonding pad; Edge bonding pads positioned at one or more of the edges of the segment for external electrical connections; And A layer of metal traces connected between the first bonding pads to interconnect the die, The metal traces are further connected between the edge bonding pad and the first bonding pad to connect the die to the external electrical connections, The segment includes an interconnected functional die and a non-functional die, the non-functional die is disconnected from the functional die, and the metal traces on the segment are routed such that a particular one of the functional die is replaced by the non-functional die. , A conformal dielectric coating is formed on the die and the conformal dielectric coating has openings for forming electrical connections to the edge bonding pad. Electrical circuit stack, A stack of segments located on top of each other, the segments comprising: a stack of segments having a plurality of edges, at least one die having a circuit therein, and electrically conductive contact points; First interconnecting means for interconnecting said die on said respective segments and connecting at least one of said die with at least one of said electrically conductive contact points on said respective segments; Access means for providing access to the electrically conductive contact points on the respective segments; And To electrically interconnect the electrically conductive contact points on the respective segments in the stack and to provide lateral electrical connections to the die located in the respective segments in the stack. A second interconnection means applied to said access means, The segments include interconnected functional dies and non-functional dies, the non-functional dies disconnected with the functional dies, and the metal traces on each of the segments indicate that a particular one of the functional dies is the non-functional die. Routed to be replaced by A conformal dielectric coating formed on the die, the conformal dielectric coating having openings for forming electrical connections at the contact points. Vertically positioning a stack of segments each having a plurality of edges on top of each other, a plurality of dies having circuitry therein, and electrically conductive contact points; Interconnecting the plurality of dies on the respective segments and connecting one or more of the electrically conductive contact points on the respective segments with one or more of the plurality of dies; Providing access to the electrically conductive contact points on the respective segments; Electrically interconnecting the electrically conductive contact points on the respective segments in the stack, and providing lateral electrical connections to the plurality of die located in the respective segments in the stack. step; And Disposing a thermally conductive epoxy preform between each of the segments to epoxy bond the segments Electrical circuit stack forming method comprising a. 25. The method of claim 24, comprising randomly dispersing a plurality of glass spheres in the preform. 26. The method of claim 25 including positioning the electrically conductive contact points along one or more of the edges on the respective segments. 27. The method of claim 26 comprising providing a layer of at least one metal trace. 28. The method of claim 27 wherein in the step of providing a layer of metal traces the layer of metal traces comprises a sandwich of chromium, titanium-tungsten, and gold. 29. The method of claim 28 including providing inwardly inclined edge walls along respective edges of the segments. 30. The method of claim 29 including providing an electrically conductive epoxy. 31. The method of claim 30, comprising providing control bonding pads to the respective segments, wherein the segments have a specific pattern formed on the control bonding pads on the respective segments. A method for forming an electrical circuit stack, characterized in that it is made specifically. 32. The method of claim 31 including providing a functional die and a non-functional die interconnected to the respective segments, the non-functional die disconnected with the functional die, and the metal traces on the respective segments And wherein one of said functional dies is routed to be replaced by said non-functional die.  33. The stack of claim 32 wherein the stack comprises at least two segments, each of the two segments including at least one die, and wherein the stack height having at least one vertical row of dies is greater than the two segments. An electric circuit laminated part formation method characterized by being a die. 34. The stack of claim 33, wherein the stack has at least six segments, each of the six segments comprising at least four dies, the stack having four vertical rows of the die, each vertical column having a height. Wherein the six functional dies are provided with electrically conductive epoxy in the six segments such that the four functional dies are connected to each of the four vertical rows of the die of the stack. Wealth forming method. 35. The electrical circuit stack of claim 34, wherein the stack comprises eight to twelve segments, each of which forms four stacks of eight functional dies, including four vertical rows of dies. Wealth forming method. Positioning a segment stack on top of each other, each segment including at least three edges forming one of each of the segments; Providing a plurality of die on said respective segments, each die including a plurality of first bonding pads; Providing a plurality of edge bonding pads positioned on the one or more edges of each of the segments for external electrical connections; Connecting a layer of metal traces between the plurality of first bonding pads to interconnect the die, the metal traces bonding the plurality of edge bonding to connect the die to the external electrical connections. Is further connected between pads and the plurality of first bonding pads; And Disposing a thermally conductive epoxy preform disposed between each of the segments to epoxy bond the segments. Electrical circuit stack forming method comprising a. 37. The method of claim 36 including randomly dispersing a plurality of glass spheres in the preform. Positioning segment stacks on top of each other comprising at least three edges, a plurality of die having circuitry therein, and electrically conductive contact points; Interconnecting the plurality of dies on the respective segments and coupling one or more of the plurality of dies with one or more of the electrically conductive contact points on the respective segments; Providing access to the electrically conductive contact points on the respective segments; Electrically interconnecting the electrically conductive contact points on each of the segments in the stack and providing lateral electrical connections to the plurality of dies located in the respective segments in the stack; And Disposing a thermally conductive epoxy preform between each of the segments to epoxy bond the segments to each other, Wherein said segments comprise interconnected functional dies and non-functional dies, wherein said metal traces on each of said segments are routed such that a particular one of said functional dies is replaced by said non-functional die. 39. The method of claim 38 including randomly dispersing a plurality of glass spheres in the preform. Positioning each segment stack on top of each other comprising a plurality of edges, at least one die having circuitry therein, and an electrically conductive contact point; Interconnecting said each segment and connecting at least one said die with at least one of said electrically conductive contact points on said each segment; Providing access to the electrically conductive contact point on each segment; Electrically interconnecting the electrically conductive contact points on each segment in the stack and providing lateral electrical connections to the die located in the respective segment in the stack; And Disposing a thermally conductive epoxy preform between each segment to epoxy bond the segments to each other, The segment includes interconnected functional dies and non-functional dies, the non-functional dies disconnected from the functional dies, and the metal traces on each segment are routed such that a particular one of the functional dies is replaced by the non-functional dies. A method for forming an electrical circuit laminate. Providing a wafer having a plurality of dies; Forming a plurality of segments each one formed by grouping one of the plurality of adjacent dies on the wafer; Interconnecting the plurality of adjacent dies on each one of the plurality of segments; Separating each of the plurality of segments from the wafer; Positioning the plurality of segments on top of each other to form a segment stack having an outer vertical side; Electrically interconnecting the segment stacks; And Placing a thermally conductive epoxy preform between each segment to epoxy bond the segments to each other Segment stacking part forming method comprising a. 42. The method of claim 41 including randomly dispersing a plurality of glass spheres in the preform. The method of claim 42, Providing an electrically conductive inner contact point on top of each of the plurality of dies; Providing an electrically conductive outer contact point on top of each one of the plurality of segments; On top of each one of the plurality of segments extending between the electrically conductive inner contact point on top of the plurality of dies and the electrically conductive outer contact point on top of each one of the plurality of segments Providing a layer of metal traces; And Providing an electrically conductive epoxy on at least one of said outer vertical sides of said laminate, A segment stack wherein the plurality of segments in the stack are electrically interconnected by bringing the electrically conductive epoxy into contact with the electrically conductive external contact point over one of the respective segments in the stack. Wealth forming method. The method of claim 43, Providing a control bonding pad on each segment; Providing a control signal from an external source to the stack for access to the segment in the stack; And Making the control signal specific for each of the segments by burning a specific pattern on the control bonding pads on top of each of the segments Segment stacking part forming method further comprising. 45. The method of claim 44 wherein the stack comprises an upper segment and the method comprises Providing a signal transfer substrate having circuitry and holes therein; Fixing the segment stack to the hole; And Electrically connecting said segment stack with said signal board by providing an electrically conductive epoxy trace between said signal board and said electrically conductive contact point on said upper segment of said stack. Segment stack formation method. 46. The method of claim 45, wherein the upper segment is coplanar with the surface of the signal transfer substrate. 47. The method of claim 46, wherein the electrically conductive epoxy trace lies on substantially the same side as the signal transfer substrate. Positioning a die stack on top of each other, each die stack comprising at least one edge and an electrically conductive contact point; Electrically interconnecting at least one of the die with at least one of the electrically conductive contact points; And Disposing a thermally conductive epoxy preform sheet between each die in the stack of dies to epoxy bond the dies to each other. Electrical circuit stack forming method comprising a. 49. The method of claim 48 including randomly dispersing a plurality of glass spheres in the preform sheet.

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