KR100588339B1 - Current reference circuit with voltage-current converter having auto-tuning function - Google Patents

Abstract

A current source circuit having a voltage-current conversion circuit having an autotuning function is disclosed. The current source circuit includes a band gap voltage generation circuit, a voltage buffer, a voltage-current conversion circuit, and an auto tuner. The band gap voltage generation circuit generates a band gap reference voltage that is stable to temperature changes. The voltage buffer receives the band gap reference voltage and generates a first bias voltage and a second bias voltage that are stable to temperature changes. The voltage-current conversion circuit receives the first bias voltage and the second bias voltage and generates a stable power supply current for temperature and process conditions in response to the tuning voltage. The auto tuner receives the input clock signal and generates a tuning voltage to maintain the gm value of the gm circuits at a constant value. The auto tuner can be configured using a phase locked loop. Therefore, the current source circuit can provide a stable power supply current for temperature and process conditions by automatically adjusting the gm value of the transconductance circuit.

Description

CURRENT REFERENCE CIRCUIT WITH VOLTAGE-CURRENT CONVERTER HAVING AUTO-TUNING FUNCTION}

1 is a schematic diagram showing a voltage-current conversion circuit according to the prior art.

2 is a diagram showing an equivalent resistance of a transfer conductance circuit.

3 is a view showing an example of a transfer conductance circuit according to the prior art.

4 is a block diagram showing a current source circuit according to a first embodiment of the present invention.

5 is a diagram illustrating a voltage buffer block of the current source circuit of FIG. 4 in detail.

6 is a circuit diagram illustrating an example of a voltage-current conversion circuit block of the current source circuit of FIG. 4.

FIG. 7 is a diagram illustrating an example of a fully differential amplifier of the voltage-current conversion circuit of FIG. 6.

FIG. 8 is a diagram illustrating in detail an auto tuner block of the current source circuit of FIG. 4.

FIG. 9 illustrates a VCO block of the auto tuner of FIG. 8 in detail.

10 is a circuit diagram illustrating another example of the voltage-current conversion circuit block of the current source circuit of FIG. 4.

11 is a block diagram showing a current source circuit according to a second embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

110, 210: band gap voltage generation circuit

120, 220: voltage buffer

130, 230: voltage-current conversion circuit

131: balanced differential voltage generator

133: common mode voltage generator

135: voltage-current converter

140, 240: auto tuner

141: phase / frequency detector

143: charge pump

145 loop filter

147: voltage controlled oscillator

149: divider

The present invention relates to a current source circuit, and more particularly, to a current source circuit having a voltage-current conversion circuit having an autotuning function.

The current source circuit is an essential circuit for supplying bias current to operational amplifiers, filters, A / D converters, and D / A converters. In general, the current source circuit includes a reference voltage generating circuit for generating a reference voltage and a voltage to current converter for converting the reference voltage into a current. In the design of semiconductor integrated circuits using a Complementary Metal Oxide Semiconductor (CMOS) process, reference voltages are generated using bandgap circuits that are stable to temperature changes. The reference voltage generated by the band gap circuit is called a bandgap reference voltage. The bandgap reference voltage generator circuit is disclosed in US Patent No. 4,931,718, which is invented by Heinz Zitta.

1 is a schematic diagram showing a voltage-current conversion circuit according to the prior art, which is disclosed in US Patent No. 5,231,316. Referring to FIG. 1, in the voltage-current conversion circuit, a reference voltage VREF is applied to a line 1 connected to the positive input terminal of the operational amplifier 2. The output line 3 of the operational amplifier 2 is connected to the gate of the NMOS transistor 9. The feedback loop 6 couples the source of the NMOS transistor 9 to the negative input terminal of the operational amplifier 2. In addition, the source of the NMOS transistor 9 is connected to one end of the resistor R1, and the other end of the resistor R is connected to the ground voltage GND. Output current IO is provided via line 5 connected to the drain of transistor 9. Voltage-to-current conversion can be achieved by using the operational amplifier 2 to maintain the reference voltage VREF in the resistor R. By definition, the voltage VREF on line 1 connected to the positive input terminal of operational amplifier 2 also appears at node 8. The output current IO may be represented by VREF / R.

However, since the resistance R changes sensitively to process and temperature changes, the accuracy of the voltage-current conversion circuit as shown in FIG. 1 is greatly limited. If the resistance value of the resistor R changes significantly with temperature and process changes, the output current IO may change significantly, and circuit blocks in the semiconductor integrated circuit using the current IO may malfunction.

Therefore, there is a need for a voltage-current conversion circuit and a current source circuit insensitive to process and temperature changes.

The present invention is an invention devised to solve the above-mentioned conventional problems, and an object of the present invention is to use a transconductance (hereinafter referred to as gm) as a substitute for the existing resistance, and process the same by adjusting the process and temperature constantly. It is to provide a current source circuit insensitive to over temperature changes.

Another object of the present invention is to provide a current source circuit insensitive to process and temperature changes by using MOS resistors in place of existing resistors and constantly adjusting them according to process and temperature changes.

In order to achieve the above object, the current source circuit according to the first embodiment of the present invention includes a band gap voltage generation circuit, a voltage buffer, a voltage-current conversion circuit, and an auto tuner.

The band gap voltage generation circuit generates a band gap reference voltage that is stable to temperature changes.

The voltage buffer receives the band gap reference voltage and generates a first bias voltage and a second bias voltage that are stable to temperature changes.

The voltage-current conversion circuit receives the first bias voltage and the second bias voltage and generates a stable power supply current for temperature and process conditions in response to the tuning voltage.

The auto tuner receives the input clock signal and generates the tuning voltage to maintain the gm value of the gm circuits at a constant value. The auto tuner can be configured using a phase locked loop.

The voltage buffer may be comprised of an operational amplifier, a feedback resistor, and n resistors.

The operational amplifier includes a first input terminal for receiving the band gap reference voltage, a second input terminal for receiving a voltage of the first node, and an output terminal, and a difference between the band gap reference voltage and the voltage of the first node. Amplify and output.

A feedback resistor is connected between the output terminal of the associative amplifier and the second input terminal of the operational amplifier, and n resistors are connected in series between the first node and ground.

The first bias voltage is output at one end of an i (i is a natural number) th resistance from the first node among the n resistance elements, and the i-1 (i is a natural number) th resistance from the first node. At one end the second bias voltage is output.

Preferably, the n resistors all have the same resistance value.

The voltage-current converter circuit includes a common mode voltage generator, a balanced differential voltage generator, and a voltage-current converter.

The common mode voltage generator maintains a constant gm value in response to the tuning voltage and generates a common mode voltage. The balanced differential voltage generator receives the first bias voltage, the second bias voltage, and the common mode voltage and generates a balanced differential voltage pair based on the common mode voltage. The voltage-to-current converter receives the balanced differential voltage pair and generates a stable power current for temperature and process conditions by a constant gm resistor in response to the tuning voltage.

The auto tuner has a phase / frequency detector, a charge pump, a loop filter, and a voltage controlled oscillator.

The phase / frequency detector detects and outputs a phase difference and a frequency difference between the input clock signal and the feedback signal. The charge pump generates a signal responsive to the output signal of the phase / frequency detector. The loop filter receives the output signal of the charge pump to remove and integrate high frequency components to generate the tuning voltage. A voltage controlled oscillator generates the feedback signal having a frequency corresponding to the level of the tuning voltage.

As a result, the auto tuner receives the input clock signal and generates the tuning voltage to maintain the gm value of the gm circuits at a constant value.

The current source circuit according to the second embodiment of the present invention includes a band gap voltage generation circuit, a voltage buffer, a voltage-current conversion circuit, and an auto tuner.

The band gap voltage generation circuit generates a band gap reference voltage that is stable to temperature changes.

The voltage buffer receives the band gap reference voltage and generates a bias voltage that is stable to temperature changes.

The voltage-to-current converter circuit generates a stable power supply current for temperature and process conditions by a constant MOS resistor that receives the bias voltage and responds to the tuning voltage.

The auto tuner can be configured using a phase locked loop as in the first embodiment.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 is a diagram showing an equivalent resistance of a transfer conductance circuit.

Referring to FIG. 2, the transfer conductance circuit 10 has an output terminal connected to an inverting input terminal and a non-inverting input terminal connected to a ground voltage GND. The input impedance Zin of the circuit of FIG. 2 is 1 / gm, and this value becomes the equivalent resistance of this circuit.

3 is a view showing an example of a transfer conductance circuit according to the prior art, which is disclosed in US Patent No. 6,191,655. The transfer conductance circuit of FIG. 3 (hereinafter referred to as gm circuit) is called 'gm circuit of Nauta' because Nauta first used the filter. The gm circuit of FIG. 4 consists of six inverters 11-16, the inverters 11, 12 generate a gain gm, and the inverters 13-16 fix the common mode voltage. Function

The differential inputs VIN + and VIN- of the gm circuit of FIG. 3 are provided to the input terminals 21 and 22 of the inverters 11 and 12, respectively, and the differential outputs VOUT + and VOUT- of the gm circuit are inverters. Are output to the output terminals 23 and 24 of the fields 11 and 12, respectively. The common mode feedback loop is cross connected to the output terminals 23 and 24 of the gm circuit. The common mode feedback loop includes inverters 13 and 16 connected in series, and the inverter 16 has its input and output terminals coupled together. The input terminal of the inverter 13 is connected to the output terminal of the inverter 11, and the output terminal of the inverter 16 is connected to the output terminal of the inverter 12. The common mode feedback loop also includes inverters 14 and 15 connected in series, and the inverter 15 has its input and output terminals coupled together. The input terminal of the inverter 14 is connected to the output terminal of the inverter 12, and the output terminal of the inverter 15 is connected to the output terminal of the inverter 11. The inverters 11 to 16 each have a pull-up transistor (not shown) composed of a P-type metal oxide semiconductor (PMOS) and a pull-down transistor (not shown) composed of an N-type metal oxide semiconductor (NMOS). The gm value of an inverter composed of a PMOS transistor and an NMOS transistor is expressed by Equation 1. Here, Vdd is the power supply voltage, Vc is the common mode voltage of the inverter, βp is the gain factor of the PMOS transistor, and βn is the gain factor of the NMOS transistor. Vtp represents the threshold voltage of the PMOS transistor, and Vtn represents the threshold voltage of the NMOS transistor. gmp represents gm of the PMOS transistor, and gmn represents gm of the NMOS transistor.

Referring to Equation 1, it can be seen that gm can be adjusted by changing the power supply voltage Vdd. In FIG. 3, the gm value of the gm circuit can be adjusted by changing the power supply voltage Vdd supplied to each of the inverters 11 to 16.

4 is a block diagram showing a current source circuit according to a first embodiment of the present invention.

Referring to FIG. 4, the current source circuit includes a band gap voltage generation circuit 110, a voltage buffer 120, a voltage-current conversion circuit 130, and an auto tuner 140.

The operation of the circuit of FIG. 4 is as follows.

The band gap voltage generation circuit 110 generates a band gap reference voltage VBG that is stable to temperature changes. The voltage buffer 120 receives the band gap reference voltage VBG and generates a first bias voltage VBIAS and a second bias voltage VBIAS + ΔV that are stable to temperature changes. The voltage-current conversion circuit 130 receives the first bias voltage VBIAS and the second bias voltage VBIAS + DELTA V, changes the gm value of the gm circuits in response to the tuning voltage VTUNE, changes the temperature and the process. Generates a stable supply current (IS) for the conditions. The auto tuner 140 is composed of a phase-locked-loop circuit and generates a tuning voltage VTUNE that receives an input clock signal FIN and maintains gm at a constant value.

5 is a diagram illustrating a voltage buffer block of the current source circuit of FIG. 4 in detail.

Referring to FIG. 5, the voltage buffer 120 includes an operational amplifier 121, a feedback resistor RF connected between an output terminal of the operational amplifier 121 and an inverting input terminal, and an inverting input terminal of the operational amplifier 121. The resistors R1 to Rn connected in series between the ground voltage GND are provided.

The band gap reference voltage VBG is applied to the non-inverting input terminal of the operational amplifier 121, and the voltage of the inverting input terminal of the operational amplifier 121 also becomes the band gap reference voltage VBG due to the characteristics of the operational amplifier 121. In order to operate stably in temperature changes, the resistors R1 to Rn and the feedback resistor RF are designed to have the same resistance value. In the circuit of Fig. 5, when R1 = R2 = ... Rn = RF, assuming that the voltage at the point P2 is VBIAS, VBIAS = VBG x (n-2) / n, and ΔV is VBG / n. Becomes

6 is a circuit diagram illustrating an example of a voltage-current conversion circuit block of the current source circuit of FIG. 4.

Referring to FIG. 6, the voltage-current conversion circuit includes a common mode voltage generator 133, a balanced differential voltage generator 131, and a voltage-current converter 135.

The common mode voltage generator 133 generates the common mode voltage VC in response to the tuning voltage VTUNE.

The balanced differential voltage generator 131 receives the first bias voltage VBIAS, the second bias voltage VBIAS + ΔV, and the common mode voltage VC and balances the common mode voltage VC. Generates the captured differential voltage pairs (VO +, VO-). The first differential voltage VO + may be represented by VO + = VC + ΔV / 2, and the second differential voltage VO− may be represented by VO− = VC−ΔV / 2.

The voltage-current converter 135 receives balanced differential voltage pairs VO + and VO-, changes the gm value in response to the tuning voltage VTUNE, and generates a stable power supply current IS for temperature and process conditions. Generate.

The common mode voltage generator 133 shorts the two output terminals of the gm circuit 134 having the differential output pairs VOUT + and VOUT- like the gm circuit of Nauta shown in FIG. 3 and disconnects the two input terminals from the gm circuit. The output terminal (134) is short-circuited. The voltage output to the shorted output terminal is the common mode voltage.

The balanced differential voltage generator 131 may include an input terminal VIN1 + of a first differential input stage of a fully-differential difference amplifier (FDDA) 132. ), And the input terminal VIN1- of the first differential input stage receives the first bias voltage VBIAS. The input terminal VIN2- of the second differential input terminal is connected to the output terminal VO +, and the input terminal VIN2 + of the second differential input terminal receives the second bias voltage VBIAS + ΔV.

The voltage-current converter 135 includes an operational amplifier 136, a gm circuit 137, an NMOS transistor MN1, an NMOS transistor MN2, and an NMOS transistor MN3.

The operational amplifier 136 amplifies and outputs a difference signal between the first output voltage VO + of the balanced differential voltage generator 131 and the voltage of the node N1. The gm circuit 137 is connected to the first input terminal and the second output terminal, and the second input terminal is connected to the node N1 in common with the first output terminal. The gm circuit 137 changes the gm value in response to the tuning voltage VTUNE. The NMOS transistor MN3 has a gate that receives the output signal of the operational amplifier 136 and a source connected to the node N1. The NMOS transistor MN1 has a gate and a source connected to each other, and has a drain connected to the power supply voltage VDD and a source connected to the drain of the NMOS transistor MN3. The NMOS transistor MN2 has a drain connected to the power supply voltage VDD and a gate connected to the gate of the NMOS transistor MN1. The power supply current IS is output to the source of the NMOS transistor MN2.

Hereinafter, the operation of the voltage-current conversion circuit of FIG. 6 will be described.

The balanced differential voltage generator 131 receives the first bias voltage VBIAS and the second bias voltage VBIAS + DELTA V and generates differential output pairs VO + and VO-. The differential output VO + has a value of VC + ΔV / 2 and is input to the non-inverting input terminal of the operational amplifier 136. The differential output VO− has a value of VC − ΔV / 2 and is input to the first input terminal of the gm circuit 137. Due to the characteristics of the operational amplifier, the node N1 receives a voltage of VC +? V / 2, which is input to the second input terminal of the gm circuit 137. Therefore, a voltage of ΔV is applied between the first input terminal and the second input terminal of the gm circuit 137.

The gm values of the gm circuit 134 constituting the common mode voltage generator 133 and the gm circuit 137 in the voltage-current converter 135 change in response to the tuning voltage VTUNE and eventually have a constant value. Keep it. Since the tuning voltage VTUNE keeps the gm value of the gm circuit constant with respect to a change in temperature or process conditions, the tuning voltage VTUNE of the gm circuit 134 and the gm circuit 137 in the voltage-current converter 135 is maintained. The gm value remains constant even if the temperature or process conditions change. If the voltage between the two input terminals of the gm circuit 137 and the value of gm are kept constant, the power supply current IS maintains a constant value even if the temperature or process conditions change.

FIG. 7 is a diagram illustrating an example of a fully differential amplifier (FDDA) 132 of the voltage-current conversion circuit of FIG. 6. The FDDA of FIG. 7 is referred to as “Fully Differential Basic Building Blocks Based on Fully Differential Difference Amplifiers with Unity-gain Difference Feedback”, IEEE Transaction on Circuits and Systems I, Vol. 42, no. 3, March 1995, by J. F. Duque-Carrillo. The FDDA of FIG. 7 includes a differential amplifier and a common mode feedback unit. The description of the operation of the FDDA of FIG. 7 is omitted here.

FIG. 8 is a diagram illustrating in detail an auto tuner block of the current source circuit of FIG. 4. The auto tuner block 140 is composed of a phase-locked-loop circuit using a gm circuit. The auto tuner block 140 receives an input clock signal FIN and generates a tuning voltage VTUNE.

Referring to FIG. 8, the auto tuner block 140 includes a phase frequency detector (hereinafter referred to as a PFD) 141, a charge pump 143, a loop filter 145, and a voltage-controlled oscillator. Oscillator (hereinafter referred to as VCO), and a divider 149.

The PFD 141 detects and outputs a phase difference and a frequency difference between the input clock signal FIN and the feedback signal FFEED. The charge pump 143 outputs a signal having a different level according to the state of the output signal of the PFD 141. The loop filter 145 receives the output signal of the charge pump 143 to generate a tuned voltage VTUNE from which high frequency components are removed and integrated. The VCO 147 generates a signal FOUT having a frequency corresponding to the level of the tuning voltage VTUNE. The divider 149 receives and divides the output signal FOUT of the VCO 147.

FIG. 9 illustrates a VCO block of the auto tuner of FIG. 8 in detail.

Referring to FIG. 9, the VCO 147 may include the first gm circuit 148, the second gm circuit 149, the capacitor Ct1, the capacitor Ct2, the resistor Rt, and the resistor (−Rt). Equipped. A capacitor Ct1 is connected between the inverting output terminal of the first gm circuit 148 and the inverting input terminal of the second gm circuit 149. The non-inverting output terminal of the first gm circuit 148 is connected to the inverting input terminal of the second gm circuit 149, and the non-inverting input terminal of the second gm circuit 149 is inverting the first gm circuit 148. It is connected to the output terminal. A capacitor Ct2, a resistor Rt, and a resistor -Rt are connected between the non-inverting input terminal of the first gm circuit 148 and the inverting output terminal of the second gm circuit 149. The non-inverting input terminal of the first gm circuit 148 is connected to the non-inverting output terminal of the second gm circuit 149, and the inverting output terminal of the second gm circuit 149 inverts the first gm circuit 148. It is connected to the input terminal. The voltage between the non-inverting input terminal of the first gm circuit 148 and the inverting output terminal of the second gm circuit 149 is the output voltage FOUT.

The first gm circuit 148 and the second gm circuit 149 change the gm value in response to the tuning voltage VTUNE. Since the gm circuits 148 and 149 and the capacitor Ct1 function as inductors, the auto tuner circuit of FIG. 9 oscillates. The reason why the resistor (Rt) and the resistor (-Rt) are connected in parallel between the non-inverting input terminal of the first gm circuit 148 and the inverting output terminal of the second gm circuit 149 is that the oscillation amplitude of the VCO is not attenuated. It functions to make the oscillation stable forever.

Hereinafter, the operation of the auto tuner 140 will be described with reference to FIGS. 8 and 9.

First, the operation of the auto tuner 140 when the gm value decreases by temperature or process conditions will be described. When the gm value decreases, the frequency of the output voltage FOUT of the VCO 147 decreases and the frequency of the feedback signal FFEED decreases. The output signal of the PFD 141 becomes high and the magnitude of the output signal of the charge pump 143 increases. Accordingly, the tuning voltage VTUNE, which is an output signal of the loop filter 145, increases and the gm values of the gm circuits 148 and 149 in the VCO increase.

Next, the operation of the auto tuner 140 when the gm value increases by temperature or process conditions will be described. When the value of gm increases, the frequency of the output voltage FOUT of the VCO 147 increases and the frequency of the feedback signal FFEED increases. The output signal of the PFD 141 goes low and the magnitude of the output signal of the charge pump 143 decreases. Therefore, the tuning voltage VTUNE, which is the output signal of the loop filter 145, is decreased and the gm values of the gm circuits 148 and 149 in the VCO are reduced.

In this way, the gm value remains constant.

10 is a circuit diagram illustrating another example of the voltage-current conversion circuit block of the current source circuit of FIG. 4. The voltage-current conversion circuit of FIG. 10 is an example configured using a single-ended transconductance circuit having a single output.

Referring to FIG. 10, the voltage-current conversion circuit 130 includes an operational amplifier 136, a gm circuit 138, an NMOS transistor MN1, an NMOS transistor MN2, and an NMOS transistor MN3.

The operational amplifier 136 amplifies and outputs a difference signal between the bias voltage VBIAS + DELTA V and the voltage of the node N1. In the gm circuit 138, a bias voltage VBIAS is applied to the non-inverting input terminal, and the inverting input terminal is connected to the node N1 in common with the output terminal. The gm circuit 138 changes the gm value in response to the tuning voltage VTUNE. The NMOS transistor MN3 has a gate that receives the output signal of the operational amplifier 136 and a source connected to the node N1. The NMOS transistor MN1 has a gate and a source connected to each other, and has a drain connected to the power supply voltage VDD and a source connected to the drain of the NMOS transistor MN3. The NMOS transistor MN2 has a drain connected to the power supply voltage VDD and a gate connected to the gate of the NMOS transistor MN1. The power supply current IS is output to the source of the NMOS transistor MN2.

The operation of the voltage-current conversion circuit of FIG. 10 will be described below.

The bias voltage VBIAS + DELTA V is applied to the non-inverting input terminal of the operational amplifier 136, and the bias voltage VBIAS is applied to the non-inverting input terminal of the gm circuit 138. Due to the characteristics of the operational amplifier, the node N1 receives a voltage of VC +? V, which is input to the inverting input terminal of the gm circuit 138. Therefore, a voltage of ΔV is applied between the non-inverting input terminal and the inverting input terminal of the gm circuit 138.

The gm value of the gm circuit 138 changes in response to the tuning voltage VTUNE. Since the tuning voltage VTUNE keeps the gm value of the gm circuit constant with respect to a change in temperature or process conditions, the gm value of the gm circuit 138 remains constant even when the temperature or process conditions change. If the voltage between the two input terminals of the gm circuit 138 and the value of gm are kept constant, the power supply current IS maintains a constant value even if the temperature or process conditions change.

11 is a block diagram showing a current source circuit according to a second embodiment of the present invention. In the current source circuit 200 of FIG. 11, the voltage-to-current converter circuit 130 uses one bias voltage VBIAS and uses an NMOS transistor operating in a triode region as a resistor. It is different from the current source circuit.

Referring to FIG. 11, the current source circuit includes a band gap voltage generation circuit 210, a voltage buffer 220, a voltage-current conversion circuit 230, and an auto tuner 240.

The band gap voltage generation circuit 210 generates a band gap reference voltage VBG that is stable to temperature changes. The voltage buffer 220 receives the band gap reference voltage VBG and generates a bias voltage VBIAS that is stable to temperature changes. The voltage-current conversion circuit 230 receives the bias voltage VBIAS, changes the gm value of the gm circuits in response to the tuning voltage VTUNE, and generates a stable power supply current IS with respect to temperature and process conditions. The auto tuner 240 is composed of a phase-locked-loop circuit and generates a tuning voltage VTUNE that receives an input clock signal FIN and maintains gm at a constant value.

The voltage-current conversion circuit 230 includes an operational amplifier 231, a gm circuit 232, an NMOS transistor MN4, an NMOS transistor MN5, an NMOS transistor MN6, and an NMOS transistor MN7.

The operational amplifier 231 amplifies and outputs a difference signal between the bias voltage VBIAS and the voltage of the node N2. The gm circuit 232 shorts the two output terminals of the gm circuit 232 having the differential output pairs VOUT + and VOUT- like the gm circuit of Nauta shown in FIG. 3 and shorts the two input terminals to the gm circuit 232. Short circuit to the output terminal of. The voltage output to the shorted output terminal is the common mode voltage (VC). The gm circuit 232 changes the gm value in response to the tuning voltage VTUNE. NMOS transistor MN7 has a gate that receives common mode voltage VC, a source connected to ground, and a drain connected to node N2. The NMOS transistor MN6 has a gate that receives the output signal of the operational amplifier 231 and a source connected to the node N2. The NMOS transistor MN4 has a gate and a source connected to each other, and has a drain connected to the power supply voltage VDD and a source connected to the drain of the NMOS transistor MN6. The NMOS transistor MN5 has a drain connected to the power supply voltage VDD and a gate connected to the gate of the NMOS transistor MN4. The power supply current IS is output to the source of the NMOS transistor MN5.

The operation of the voltage-current conversion circuit will be described below.

The bias voltage VBIAS is applied to the non-inverting input terminal of the operational amplifier 231. VBIAS is applied to node N2 due to the characteristics of the operational amplifier, and this voltage is applied to node N2. The gm circuit 232 generates the common mode voltage VC, and the gm value is changed by the tuning voltage VTUNE.

The current source circuit 200 of FIG. 11 uses an NMOS transistor operating in a triode region as a resistor. In Nauta's gm circuit, if the transfer conductance gmp of the PMOS transistor constituting the inverter and the transfer conductance gmn of the NMOS transistor are the same, Equation 1 may be expressed as Equation 2.

On the other hand, when the NMOS transistor operates in the linear region, the drain current can be expressed as shown in Equation 3.

Here, Ids is a drain-source current, Vgs is a gate-source voltage, Vds is a drain-source voltage, and Vtn is a threshold voltage of an NMOS transistor. When the NMOS transistor operates in the triode region, Vds has a very small value, so that Equation 3 can be expressed as Equation 4.

Therefore, the resistance of the NMOS transistor can be expressed as in Equation 5.

Here, Vc represents the common mode voltage.

Referring to Equations 2 and 5, when gm is maintained at a constant value due to the tuning voltage VTUNE generated by the auto tuner 240, the resistance of the NMOS transistor may be maintained at a constant value. In order to approximate Equation 5, it is advantageous to operate the MOS transistor in a deep triode region. That is, it is advantageous to operate in a region where Vds is small. In addition, it is possible to reduce the process mismatch by designing the length of the NMOS transistor MN7 used as a resistor in FIG. 11 to be several um or more.

Table 1 shows the results of simulation of the change of the power supply current (IS) according to the temperature and the process change after the current source circuit of FIG. 11 is designed in a 0.18 um CMOS process. In the process corner (Corner), T = Typical, F = Fast, S = Slow is shown, and the process corners of the NMOS transistor and the PMOS transistor are shown together.

Corner Temp [C] Vtune [V] IS [uA] Deviation of IS TT 27 2.14 1.2 TT -40 2.08 1.21 0.8% TT 100 2.21 1.17 -2.5% FF -40 1.89 1.28 6.7% SS 100 2.40 1.13 -5.8% SF -40 2.02 1.17 -2.5% FS 100 2.23 1.19 -0.8%

Referring to Table 1, the simulation results show that the accuracy of the power supply current (IS) is within ㅁ 10% even in the worst case of the process and temperature change.

Although described with reference to the examples, those skilled in the art can understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention described in the claims below. There will be.

As described above, the current source circuit according to the present invention can supply stable power current for temperature and process conditions by automatically adjusting the gm value of the transconductance circuit.

Claims (22)

A band gap voltage generation circuit for generating a band gap reference voltage stable to temperature change; A voltage buffer receiving the band gap reference voltage and generating a first bias voltage and a second bias voltage stable to a temperature change; A voltage-current conversion circuit configured to receive the first bias voltage and the second bias voltage and generate a stable power current with respect to temperature and process conditions by a gm circuit responsive to a tuning voltage; And And an auto tuner configured to receive an input clock signal and generate the tuning voltage to maintain gm values of gm circuits at a constant value. The method of claim 1, wherein the voltage buffer is A first input terminal receiving the band gap reference voltage, a second input terminal receiving the voltage of the first node, and an output terminal, and amplifying a difference between the band gap reference voltage and the voltage of the first node An operational amplifier for outputting; A feedback resistor connected between the output terminal of the associative amplifier and the second input terminal of the operational amplifier; And And n (n is a natural number) resistors connected in series between the first node and ground. The method of claim 2, The first bias voltage is output at one end of an i (i is a natural number) th resistance from the first node among the n resistance elements, and the i-1 (i is a natural number) th resistance from the first node. And the second bias voltage is output at one end. The method of claim 2, And the n resistors all have the same resistance value. The method of claim 1, wherein the voltage-current conversion circuit A common mode voltage generator configured to maintain a constant gm value in response to the tuning voltage and generate a common mode voltage; A balanced differential voltage generator configured to receive the first bias voltage, the second bias voltage, and the common mode voltage and generate a balanced differential voltage pair based on the common mode voltage; And And a voltage-to-current converter for receiving the balanced differential voltage pair and generating a stable power supply current with respect to temperature and process conditions by a gm circuit responsive to the tuning voltage. The method of claim 5, wherein the common mode voltage generator And a first gm circuit having two output terminals shorted to each other and two input terminals commonly connected to the output terminals to generate the common mode voltage. The method of claim 5, wherein the balanced differential voltage generator Having a first output terminal and a second output terminal, A first differential input terminal having a first input terminal connected to the second output terminal and a second input terminal receiving the first bias voltage; And And a second differential input terminal having a first input terminal connected to the first output terminal and a second input terminal receiving the second bias voltage. The method of claim 5, wherein the voltage-current converter An operational amplifier for amplifying and outputting a difference signal between a first output voltage of the balanced differential voltage generator and a voltage of a first node; A first input terminal and a second output terminal are connected, and a second input terminal is connected to the first node in common with the first output terminal, and the second output of the balanced differential voltage generator as the first input terminal A second gm circuit for receiving a voltage and changing a gm value in response to the tuning voltage; A first NMOS transistor having a gate receiving an output signal of the operational amplifier and a source connected to the first node; And And a current mirror circuit connected to the drain of the first NMOS transistor and supplying a first current to the first NMOS transistor and generating the power supply current corresponding to the first current. The method of claim 8, wherein the current mirror circuit A second NMOS transistor having a gate and a source connected to each other, a drain connected to a power supply voltage, and a source connected to a drain of the first NMOS transistor; And And a drain connected to the power supply voltage, a gate connected to a gate of the second NMOS transistor, and a source to which the power supply current is output. The method of claim 1, wherein the auto tuner is A phase / frequency detector for detecting and outputting a phase difference and a frequency difference between the input clock signal and the feedback signal; A charge pump generating a signal in response to an output signal of the phase / frequency detector; A loop filter receiving the output signal of the charge pump to remove and integrate high frequency components to generate the tuning voltage; And And a voltage controlled oscillator for generating the feedback signal having a frequency corresponding to the level of the tuning voltage. The apparatus of claim 10, wherein the auto tuner is And a divider for dividing the feedback signal, which is an output signal of the voltage controlled oscillator, and feeding it back to the phase / frequency detector. The oscillator of claim 10, wherein the voltage controlled oscillator A first gm circuit having first and second input terminals and first and second output terminals, the first gm circuit having a gm value maintained at a constant value in response to the tuning voltage; A second input terminal connected to the first output terminal of the first gm circuit, a first input terminal connected to the second output terminal of the first gm circuit, a first input terminal connected to the first input terminal of the first gm circuit A second gm circuit having a first output terminal and a second output terminal connected to the second input terminal of the first gm circuit and having a gm value maintained at a constant value in response to the tuning voltage; A first capacitor connected between the second output terminal of the first gm circuit and the second input terminal of the second gm circuit; A second capacitor connected between the first input terminal of the first gm circuit and the second output terminal of the second gm circuit; A first resistor coupled between the first input terminal of the first gm circuit and the second output terminal of the second gm circuit; And And a second resistor connected between the first input terminal of the first gm circuit and the second output terminal of the second gm circuit, the second resistor having a polarity opposite to that of the first resistor. The method of claim 1, wherein the voltage-current conversion circuit An operational amplifier for amplifying and outputting a difference signal between the second bias voltage and the voltage of the first node; A first input terminal and a second output terminal are connected, and the second input terminal is connected to the first node in common with the first output terminal, and the first input terminal receives the first bias voltage and the tuning A gm circuit whose gm value changes in response to a voltage; A first NMOS transistor having a gate receiving an output signal of the operational amplifier and a source connected to the first node; And And a current mirror circuit connected to the drain of the first NMOS transistor and supplying a first current to the first NMOS transistor and generating the power supply current corresponding to the first current. The method of claim 13, wherein the current mirror circuit A second NMOS transistor having a gate and a source connected to each other, a drain connected to a power supply voltage, and a source connected to a drain of the first NMOS transistor; And And a third NMOS transistor having a drain connected to the power supply voltage, a gate connected to a gate of the second NMOS transistor, and a source from which the power supply current is output. A band gap voltage generation circuit for generating a band gap reference voltage stable to temperature change; A voltage buffer receiving the band gap reference voltage and generating a stable bias voltage in response to a temperature change; A voltage-current conversion circuit that receives the bias voltage and generates a stable power supply current with respect to temperature and process conditions in response to a tuning voltage; And And an auto tuner for receiving an input clock signal and generating the tuning voltage to maintain a gm value of gm circuits at a constant value. The method of claim 15, wherein the voltage-current conversion circuit An operational amplifier for amplifying and outputting a difference signal between the bias voltage and the voltage of the first node; A first NMOS transistor having a gate receiving an output signal of the operational amplifier and a source connected to the first node; A current mirror circuit connected to the drain of the first NMOS transistor and supplying a first current to the first NMOS transistor and generating the power current corresponding to the first current; A gm circuit having two output terminals shorted to each other and two input terminals commonly connected to the output terminals to generate a common mode voltage; And And a second NMOS transistor having a gate receiving the common mode voltage, a drain connected to the first node, and a source connected to ground. The method of claim 16, wherein the current mirror circuit A third NMOS transistor having a gate and a source connected to each other, a drain connected to a power supply voltage, and a source connected to a drain of the first NMOS transistor; And And a fourth NMOS transistor having a drain connected to the power supply voltage, a gate connected to a gate of the third NMOS transistor, and a source from which the power supply current is output. A common mode voltage generator configured to maintain a constant gm value in response to the tuning voltage and generate a common mode voltage; Generating a balanced differential voltage receiving the first bias voltage, a second bias voltage having a predetermined value greater than the first bias voltage, and the common mode voltage and generating balanced differential voltage pairs around the common mode voltage; part; And And a voltage-current converter configured to receive the balanced differential voltage pair and generate a stable power supply current for temperature and process conditions in response to the tuning voltage. 19. The method of claim 18, wherein the common mode voltage generator And a first gm circuit having two output terminals shorted to each other and two input terminals commonly connected to the output terminals, the first gm circuit generating the common mode voltage. 19. The method of claim 18, wherein the balanced differential voltage generator Having a first output terminal and a second output terminal, A first differential input terminal having a first input terminal connected to the second output terminal and a second input terminal receiving the first bias voltage; And And a second differential input terminal having a first input terminal connected to the first output terminal and a second input terminal receiving the second bias voltage. The method of claim 18, wherein the voltage-current converter An operational amplifier for amplifying and outputting a difference signal between a first output voltage of the balanced differential voltage generator and a voltage of a first node; A first input terminal and a second output terminal are connected, and a second input terminal is connected to the first node in common with the first output terminal, and the second output of the balanced differential voltage generator as the first input terminal A second gm circuit for receiving a voltage and changing a gm value in response to the tuning voltage; A first NMOS transistor having a gate receiving an output signal of the operational amplifier and a source connected to the first node; And And a current mirror circuit connected to the drain of the first NMOS transistor and supplying a first current to the first NMOS transistor and generating the power current corresponding to the first current. . 22. The system of claim 21, wherein the current mirror circuit A second NMOS transistor having a gate and a source connected to each other, a drain connected to a power supply voltage, and a source connected to a drain of the first NMOS transistor; And And a drain connected to the power supply voltage, a gate connected to a gate of the second NMOS transistor, and a source for outputting the power supply current.

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