KR100587602B1 - Method for forming MIM capacitor of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a MIM capacitor of a semiconductor device. The disclosed invention includes forming a plug contact hole in the first interlayer dielectric layer after forming a first interlayer dielectric layer on the lower metal wiring; Forming a contact plug in the plug contact hole; Sequentially forming a conductive layer and an insulating layer on the first interlayer insulating film including the contact plug, and then forming a photoresist pattern thereon; Patterning the conductive layer and the insulating layer using the photoresist pattern as a mask to form a lower electrode and a dielectric film; Forming a second interlayer insulating film only on the first interlayer insulating film; Removing the photoresist pattern to form a trench, and then forming an upper electrode in the trench; Forming a third interlayer insulating film on the second interlayer insulating film including the upper electrode; Sequentially removing the third interlayer insulating film, the second interlayer insulating film, and the first interlayer insulating film to form a via hole exposing the lower metal wiring; Filling the via hole by forming an organic material layer on the third interlayer insulating layer including the via hole; The dual damascene contact hole and the upper electrode contact hole are removed by removing the upper surface of the via hole and the organic material layer embedded therein, and etching part of the third interlayer insulating film on the side surfaces of the third interlayer insulating film and the second interlayer insulating film and on the upper electrode. Forming; And forming an upper metallization wiring in the dual damascene contact hole and the upper electrode contact hole.

Description

Method for forming MIM capacitor of semiconductor device

1A through 1E are cross-sectional views of processes for describing a method of forming a capacitor of a semiconductor device according to the prior art;

2A to 2I are cross-sectional views of processes for explaining a method of forming a capacitor of a semiconductor device according to the present invention.

[Description of Drawing Reference]

41 lower metal wiring 43 barrier film

45: first interlayer insulating film 47: contact plug

49 TiN layer for lower electrode 51 Insulation film

53: first photosensitive film pattern 55: LPD oxide film (second interlayer insulating film)

57 TiN layer for upper electrode 57a: upper electrode

59: third interlayer insulating film 61: via hole

63: organic barc 65: second photosensitive film pattern

67: dual damascene contact hole 69: upper metal wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a capacitor of a semiconductor device, and more particularly, to planarization simultaneously with MIM formation using selective liquid phase deposition (LPD) for patterning metal insulator metal (MIM) of copper wiring. By making it easy to form, the wiring characteristics of the device are improved, and there is no concern about the leakage between the void and the upper and lower electrodes, which may be caused during conventional MIM etching, and thus the MIM of the semiconductor device can improve the reliability of the device. It relates to a method of forming a capacitor.

A method of forming a MIM capacitor of a semiconductor device according to the prior art will now be described with reference to FIGS. 1A to 1E.

1A to 1E are cross-sectional views illustrating processes for forming a MIM capacitor of a semiconductor device according to the prior art.

In the method of forming a MIM capacitor of a semiconductor device according to the related art, as shown in FIG. 1A, a barrier layer 13 and a first interlayer insulating layer 15 are first stacked on a lower metal wiring 11, and then a contact mask is formed thereon. Next, a plug contact hole (not shown) is formed by selectively patterning the interlayer insulating layer 15 and the barrier layer 13 through a contact mask (not shown).

Thereafter, a copper layer (not shown) is deposited on the first interlayer insulating layer 15 including the plug contact hole (not shown) to form a contact plug 17.

Subsequently, the lower electrode layer 19, the dielectric film 21, and the upper electrode 23 are sequentially deposited on the first interlayer insulating film 15 including the contact plug 17, and then selectively patterned.

Next, as shown in FIG. 1B, the etch stop layer 25 and the insulating layer 27 are sequentially deposited on the upper surface of the entire structure.

Subsequently, as shown in FIG. 1C, after the mask forming process for forming the via hole exposing the upper metal wiring 11 is performed, the insulating film 27 and the insulating film 27 are formed by a plasma etching process using the mask (not shown). The etch stop layer 25 and the interlayer insulating layer 15 are sequentially etched to form via holes 29.

Next, as illustrated in FIG. 1D, the dual damascene process selectively etches the insulating layer 27, a portion of the etch stop layer 25, and a barrier layer 13 at the bottom of the bar hole 29 to form the lower portion. The dual damascene contact hole 29a exposing the metal wiring 11 is formed. In this case, portions of the interlayer insulating layer 27 on the upper electrode 23 are also etched to expose the upper surface of the upper electrode 23.

Subsequently, as illustrated in FIG. 1E, a copper layer 33 is deposited on the upper surface of the entire structure including the dual damascene contact hole 29a to form the dual damascene contact hole 29a and the upper electrode 23. Landfill the exposed part.

Then, the CMP process is performed to planarize the insulating layer 27 to form an upper metal wiring.

According to the conventional method of forming a MIM capacitor using copper, it is difficult to set the etching conditions according to the pattern density at the time of upper metal / insulation film / lower metal etching for MIM patterning. Side loss of the insulating film may occur due to the etching selectivity characteristic, which may cause voids during the subsequent deposition of the insulating film. By-products are redeposited on the sidewall of the insulating film during the etching of the lower metal. It is easy to deteriorate liquidity characteristics.

In addition, it is difficult to secure depth of focus (DOF) margin in the subsequent mask process because it causes a step in the deposition of a subsequent interlayer insulating film by MIM patterning, and it is necessary to remove the copper and the insulating film excessively in the subsequent CMP process. There is a risk of dishing.

In addition, due to the above characteristics, the process margin characteristics are degraded because the constraints on the thickness of the electrode and the insulating layer are large.

Furthermore, the application of an etch stop film, that is, a nitride film, in order to minimize the loss of the upper electrode during via hole etching reduces device performance due to an increase in internal capacitance.

Accordingly, the present invention has been made to solve the above problems of the prior art, by using a selective liquid phase deposition (LPD) for the patterning of metal insulator metal (MIM) of copper wiring by implementing a planarization at the same time MIM formation and subsequent By improving the wiring characteristics of the device by facilitating the formation of the wiring, there is no concern about the leakage between the void and the upper and lower electrodes which may be caused during the conventional MIM etching. The object is to provide a method of forming a capacitor.

According to an aspect of the present invention, there is provided a method of forming a MIM capacitor, comprising: forming a plug contact hole in a first interlayer insulating film after forming a first interlayer insulating film on a lower metal wiring; Forming a contact plug in the plug contact hole; Sequentially forming a conductive layer and an insulating film on the first interlayer insulating film including the contact plug, and then forming a photoresist pattern thereon; Patterning the conductive layer and the insulating layer using the photoresist pattern as a mask to form a lower electrode and a dielectric layer; Forming a selective interlayer insulating film only on the first interlayer insulating film; Removing the photoresist pattern to form a trench, and then forming an upper electrode in the trench; Forming a second interlayer insulating film on the selective interlayer insulating film including the upper electrode; Sequentially removing the second interlayer insulating film, the selective interlayer insulating film, and the first interlayer insulating film to form a via hole exposing the lower metal wiring; Filling the via hole by forming an organic material layer on the second interlayer insulating layer including the via hole; Forming a dual damascene contact hole and an upper electrode contact hole by removing the upper surface of the via hole and the organic material film embedded therein, and etching a portion of the second interlayer insulating film on the side of the second interlayer insulating film and the optional interlayer insulating film and on the upper electrode. step; And forming an upper metallization wiring in the dual damascene contact hole and the upper electrode contact hole.

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(Example)

Hereinafter, a method of forming a MIM capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2I are cross-sectional views illustrating a method of forming a MIM capacitor of a semiconductor device according to the present invention.

In the method of forming a MIM capacitor of a semiconductor device according to the present invention, as shown in FIG. 2A, a barrier layer 43 and a first interlayer insulating layer 45 are first stacked on a lower metal wiring 41, and then contacted thereon. A mask (not shown) is formed and then a plug contact hole (not shown) is formed by selectively patterning the interlayer insulating layer 45 and the barrier layer 43 through a contact mask (not shown).

Next, a contact plug 47 is formed by depositing a copper layer (not shown) on the first interlayer insulating layer 45 including the plug contact hole (not shown) by using an electron plating method.

Next, an insulating film 51 for use as a dielectric film composed of a lower electrode TaN or TiN layer 49 and a Si ₃ N ₄ or TaO ₅ or the like on the first interlayer insulating film 45 including the contact plug 47. In order to deposit. At this time, the TiN layer 49 is deposited to a thickness of about 200 to 500 Å, and the insulating film 51 composed of a nitride film or TaO ₅ having a relatively high dielectric constant is deposited to about 200 to 500 Å.

Next, after the photosensitive material is coated on the insulating film 51, the photosensitive material is exposed and developed using a photolithography process technology. Then, the photosensitive material is left so that only the portion of the insulating film 51 corresponding to the contact plug 47 remains. The material layer (not shown) is selectively removed to form the photoresist pattern 53.

Subsequently, as illustrated in FIG. 2B, the insulating layer 51 and the TaN or TiN layer 49 are selectively removed using a plasma etching apparatus using the photoresist pattern 53 as a mask. In this case, the etching equipment is a device having a MID (middle ion density) (1 × 10E11 ions / cm ³ ), and the etching conditions are performed at a pressure of 30 to 50 mTorr, a source power of 1000 to 1500 W, and a bias power of 800. ~1200 W, a gas flow rate of CF ₄ is 50~80sccm, O ₂ is 20~30 sccm, Ar is 400~600 sccm.

Next, as shown in FIG. 2C, the first interlayer insulating film exposed by etching in FIG. 2B without growing the insulating film in the portion where the TiN layer 49 for the lower electrode and the photoresist film on the insulating film 51 remain. In order to selectively grow an oxide film only on (45), an aqueous solution in which boric acid (H ₃ BO ₃ ) was added to selective liquid phase deposition (LPD), that is, supersaturated hydrofluorosilic acid (H ₂ SiF ₆ ) at room temperature The second interlayer insulating film (SiO ₂ ) 55 is selectively grown to a thickness of 3000 to 4000 Å in the exposed interlayer insulating film, that is, the oxide film region, by using a method of growing SiO ₂ only on silicon oxide and silicon by depositing on the film.

In this case, the mechanism of selective liquid phase deposition (LPD) of silicon dioxide, which is the second interlayer insulating film, will be described below.

H ₂ SiF ₆ + ₂ H ₂ O ↔ SiO ₂ + HF

Therefore, SiO ₂ is deposited in an aqueous hydrofluoric acid (H ₂ SiF ₆ ) solution, and HF is generated to etch SiO _{2. In} order to decompose HF, boric acid (H ₃ BO ₃ ) is 20 to 30%. Add to this to increase the resist selectivity and deposition rate by the following reaction.

H ₃ BO ₃ + ₄ HF ↔ BF _4- + H ₃ O + + 2H ₂ O

Subsequently, as shown in FIG. 2D, the photoresist pattern 53 is removed using an O ₂ plasma to form a trench (not shown), and then a PVD method is used on the upper surface of the entire structure to form an upper metal electrode. As a result, TaN or TiN layer 57 which is a barrier metal is deposited.

Next, as shown in FIG. 2E, the TiN layer 57 is planarized using the CMP method to form the upper electrode 57a.

Next, as shown in FIG. 2F, a third interlayer insulating film 59 is deposited on the upper surface of the entire structure including the upper electrode 57a by using a PE-CVD method.

Next, as shown in FIG. 2G, a via hole mask (not shown) is first formed on the third interlayer insulating layer 59 by using the via first dual damascene method to connect the lower metal wiring and the upper electrode. Then, the via hole 61 is formed by sequentially removing the third interlayer insulating layer 59, the LPD oxide layer 55 and the first interlayer insulating layer 45, which are second interlayer insulating layers, using a plasma etching method.

Subsequently, as shown in FIG. 2H, the organic barc layer 63 including the via hole 61 may be formed by using a rotary coating method to prevent exposure of the lower copper layer by subsequent trench etching. It is applied on the three interlayer insulating film 59. In this case, the organic bark layer 63 fills the entire via hole 61.

Next, the metallization mask pattern 65 is formed on the upper surface of the entire structure, and then the organic bark layer 63 filled in the via hole 61 is selectively etched using the plasma etching method.

Subsequently, as shown in FIG. 2I, the organic bark layer 63 and the third interlayer insulating layer 59 are etched using the metallization mask pattern 65 as a mask to form a dual damascene trench 67. do.

Subsequently, the upper metal wiring 69 is formed by filling a copper layer in the via hole 61 and the dual damascene trench 67 by using an electron plating method.

As described above, according to the method of forming a MIM capacitor of a semiconductor device according to the present invention, patterning failure due to the difference in etching characteristics according to the pattern density is achieved by forming the upper metal electrode on the lower metal and the insulating layer without the conventional upper metal etching process. There is no concern.

In addition, since there is no upper metal etching process, there is no concern about deterioration of capacitor characteristics due to an increase in the thickness of the insulating layer considering the etch stop.

In addition, since the formation of the upper metal electrode and the planarization are simultaneously performed by the CMP method after the selective deposition of the insulating film by LPD, the wiring characteristics of the device can be improved by facilitating subsequent processes.

In addition, since the deposition of the insulating film by the deposition method at room temperature does not require a deposition process by HDP (high density plasma) to improve the level difference, there is no fear of deterioration of device characteristics because there is no damage effect by plasma.

In addition, since there is no concern about voids and leakage between upper and lower electrodes that may be caused during conventional MIM etching, device reliability may be improved.

In addition, since there is no need for an etch stop film having a higher dielectric constant than the insulating film, there is no concern about an increase in internal capacitance.

On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (12)

Forming a plug contact hole in the first interlayer dielectric layer after forming a first interlayer dielectric layer on the lower metal interconnection; Forming a contact plug in the plug contact hole; Sequentially forming a conductive layer and an insulating film on the first interlayer insulating film including the contact plug, and then forming a photoresist pattern thereon; Patterning the conductive layer and the insulating layer using the photoresist pattern as a mask to form a lower electrode and a dielectric layer; Forming a selective interlayer insulating film only on the first interlayer insulating film; Removing the photoresist pattern to form a trench, and then forming an upper electrode in the trench; Forming a second interlayer insulating film on the selective interlayer insulating film including the upper electrode; Sequentially removing the second interlayer insulating film, the selective interlayer insulating film, and the first interlayer insulating film to form a via hole exposing the lower metal wiring; Filling the via hole by forming an organic material layer on the second interlayer insulating layer including the via hole; Forming a dual damascene contact hole and an upper electrode contact hole by removing the upper surface of the via hole and the organic material film embedded therein, and etching a portion of the second interlayer insulating film on the side of the second interlayer insulating film and the optional interlayer insulating film and on the upper electrode. step; And And forming an upper buried interconnection in the dual damascene contact hole and the upper electrode contact hole. 2. The method for forming a MIM capacitor of a semiconductor device according to claim 1, wherein TaN or TiN is used as the conductive layer, and the thickness thereof is in the range of 200 to 500 GPa. The method for forming a MIM capacitor of a semiconductor device according to claim 1, wherein a nitride film (Si ₃ N ₄ ) or TaO ₅ is deposited to have a thickness of 200 to 500 GPa. The method of claim 1, wherein the etching of the insulating layer and the conductive layer is performed using a plasma etching apparatus, and has a middle ion density (MID) (1 × 10E11 ions / cm ³ ). Proceed at 30 to 50 mTorr, source power is 1000 to 1500 W, bias power is 800 to 1200 W, gas flow rate is 50 to 80 sccm for CF ₄ , 20 to 30 sccm for O ₂ , and 400 to 600 sccm for Ar. A method of forming a MIM capacitor of a semiconductor device. The method of claim 1, wherein the selective interlayer insulating film is a selective LPD (liquid phase deposition) oxide film. The method of claim 5, wherein the selective LPD oxide film is deposited on an aqueous solution in which boric acid (H ₃ BO ₃ ) is added to a supersaturated hydrofluorosilic acid (H ₂ SiF ₆ ) at room temperature to SiO ₂ only on silicon oxide and silicon. A method of forming a MIM capacitor of a semiconductor device, characterized in that it is selectively grown to a thickness of 3000 ~ 4000 에 in the oxide film region which is an exposed interlayer insulating film by using a method of growing. The method of claim 1, wherein the photoresist pattern is removed using an oxygen plasma. The method of claim 1, wherein the second interlayer dielectric film is formed using a PE-CVD method. The method of claim 1, wherein an organic barc layer is used as the organic material layer, and the organic material layer is formed using a rotation coating method. The method of claim 1, wherein the upper metal wiring is formed by a copper layer using an electron plating method. The MIM capacitor of claim 10, wherein the upper electrode is formed by using TiN or TaN, and forming a TiN or TaN layer on the upper surface of the entire structure including the trench and then planarizing the same by using a CMP process. Formation method. The method of claim 6, wherein the boric acid (H ₃ BO ₃ ) is added in an amount of 20 to 30%.

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