KR100550240B1 - Tiled graphics architecture - Google Patents

Abstract

A device and method for reducing memory bandwidth utilization in a tiled graphics architecture are presented. In one embodiment, the microprocessor reads graphics circular vertex data from graphics memory. The processor determines the bin across the graphics circle. The processor determines the graphics primitives across the first and second bins, and the process writes vertex data for the graphics primitives into a first bin storage area in graphics memory. The processor then writes the pointer to the second empty storage area. The pointer represents the location in memory of the actual vertex data.

Tiled, Graphics Architecture, Memory Bandwidth, Circular, Raw Data, Bin, Pointer

Description

Tiled Graphics Architecture {TILED GRAPHICS ARCHITECTURE}

The present invention relates to the field of computer systems. In particular, the present invention is directed to reducing the primitive storage requirements and improving memory bandwidth utilization in tiled architectures.

In general, in computer graphics systems, the three dimensional (3D) objects represented on the display screen are graphics primitives such as triangle lists, triangle strips, and triangle fans. graphics primitive). In general, the prototypes of the 3D object to be represented are defined by the host computer in terms of primitive data. For example, for each circular triangle, the host computer not only defines the spatial location of the three vertices of the triangle in X, Y, and Z coordinates, but also the red (R), green (G), and blue ( Data defining the color value of B) and texture coordinates may be defined. Additional raw data can be used for specific applications. The rendering hardware in the graphics controller interpolates the raw data to calculate the display screen pixels representing each prototype and the R, G and B color values for each pixel. .

For more efficient use of memory bandwidth, 3D primitives are sorted into a plurality of bins, also referred to as "tiles." This well known technique is often referred to as "tiling".

1 and 2 show an example of classifying graphics circles into a plurality of bins or " tiles. &Quot; In this example, the microprocessor fetches data for the prototypes 110, 120, 130 from the circular storage area. The circular storage area may be implemented as part of the local graphics memory or main system memory connected directly to the graphics controller. These circles 110, 120, 130 are rendered and displayed on the display screen represented by block 100. For this example, block 100 is divided into four or more bins. In general, a frame of display data is divided into more than four bins shown in this example having a typical bin size of 128 * 64 pixels. This example uses four beans to simplify the description.

After retrieving data for the graphics prototype, the processor determines which bin or "tile" traverses the prototype. For example, the processor may determine that the circle 110 crosses the bin 210 as well as the bin 220. The processor then stores the data for the three vertices of the circle 110 in a graphics memory set aside to store the raw data for the bin 220 as well as for storing the raw data for the bin 210. Record it. Similarly, the processor writes the vertex data of the circle 120 to the storage regions of bins 220 and 240, and the vertex data of the circle 130 to the storage regions of bins 210, 230, and 240. do. Once the primitives are classified into bins, the graphics controller retrieves the primitive data from graphics memory and renders the primitives one at a time.

2 illustrates how the graphics controller divides the circles 110, 120, 130 into several circles suitable for the bins 210, 220, 230, 240. Several circles are divided into bins depending on how the circle crosses the empty boundary. For example, when retrieving the raw data of the bin 210 from the graphics memory, the graphics controller divides the prototype 110 to produce the prototype 211. Circle 130 is divided to produce circle 212. The graphics controller continues to render the circles 211, 212. The graphics controller then divides the circles 110, 120 to produce the circles 221, 222, and renders the circles 221, 222 to continue processing of the bin 220.

3 is a block diagram of a conventional computer system implementing a tiled graphics architecture. 3 shows a processor 310, a system memory 330 that includes a graphics circular storage area 332, a graphics controller 340, and a display monitor 350.

Conventional tiled graphics architectures, such as those implemented in the system of FIG. 3, have the drawback of using large amounts of memory bandwidth when moving raw data from one device to another. For example, when processor 310 processes a prototype, processor 310 reads the circular vertex data from graphics circular storage area 332. Processor 310 then determines which bins traverse the circle. The processor 310 then must write back several copies to the graphics circular storage area 332, the number of copies being written depends on how many bins traverse the prototype.

The impact of memory bandwidth utilization can be explained by considering a typical graphics prototype that can be represented by approximately 100 bytes of vertex data and a graphics prototype where several bins can traverse. This example will assume a representative circle across three bins. In this situation, the processor 310 must write an average of 300 bytes of vertex data in the graphics circular storage area 332 for each prototype processed. For one frame of a relatively simple display of 2K graphics primitives, the processor 310 must transmit 600K bytes per frame. If this frame display rate is 60 frames per second, the processor 310 must transmit data to the graphics circular storage area 332 at a rate of 360M bytes per second. For more complex displays consisting of 100K prototypes, the bandwidth requirement increases to 1.8G bytes per second. The same bandwidth requirement must also be met between the graphics circular storage area 332 and the graphics controller 340. The high memory bandwidth utilization for moving graphics circular data from processor 310 to graphics circular storage area 332 and from graphics circular storage area 332 to graphics controller 340 will have a significant negative impact on the performance of the overall system. Can be.

The invention will be more fully understood from the following detailed description and accompanying drawings of embodiments of the invention. However, the specific embodiments described are merely to aid the explanation and understanding of the present invention, but not to limit the present invention.

1 is a diagram illustrating several 3D objects arranged on a display screen according to a conventional system.

FIG. 2 is a diagram for describing several 3D objects of FIG. 1 classified into a plurality of bins according to a conventional system.

3 is a block diagram of a conventional system that includes a tiled graphics architecture.

4 is a flow diagram illustrating one embodiment of a method of reducing memory bandwidth utilization in a tiled graphics architecture.

5 is a flow diagram illustrating one embodiment of a method of reducing memory bandwidth utilization in a tiled graphics architecture when a graphics circular storage area is located in system memory.

FIG. 6 is a flow diagram illustrating one embodiment of a method of reducing memory bandwidth utilization in a tiled graphics architecture when the graphics circular storage area is located in local graphics memory.

7 is a block diagram of a system including one embodiment of a graphics controller that includes a vertex cache.

 One embodiment of an apparatus and method for reducing memory bandwidth utilization in a tiled graphics architecture is described. In this embodiment, the microprocessor reads the graphics primitive vertex data from the graphics memory. The microprocessor determines which bins cross the graphics circle. All vertices of the prototype are written to the vertex buffer for future reference. Vertex buffers can be located in main system memory or local graphics memory. This vertex buffer may be implemented within a portion of an empty storage area or within a separate memory location.

Once the microprocessor has determined the graphics prototype across the first and second bins, the microprocessor writes a pointer to the first and second bin storage areas. This pointer represents the memory location of the actual vertex data. Thus, only one copy of the vertex data is moved from the microprocessor to graphics memory. Because of this, the size of the pointer is smaller than the size of the vertex data, and less data is moved from the microprocessor to the graphics memory, thus improving memory bandwidth utilization.

The microprocessors in the above examples and the following embodiments can be replaced with 3D graphics microprocessors that handle the same circular processing as performed by the microprocessor. For example, further embodiments may include a 3D graphics processor that performs hardware transformation and lighting calculations in hardware.

The graphics memory of the above examples and the following embodiments may be implemented as local graphics memory included as part of main system memory or directly connected to the graphics controller.

The term "pointer" as used herein is intended to include all means for indicating the location of the vertex data, at least in part, including a memory address and an index. For example, the pointer may be a physical or virtual memory address that indicates the location of the vertex data. Alternatively, the pointer may be an index that can be used to calculate the address location of the vertex data. For example, the address may be calculated from the index according to the formula "base address + index * vertex data size".

Although the above examples and the following examples discuss a given number of bins that may cross the graphics circle, other examples may use any number of bins. The graphics circles discussed herein also include triangles containing three vertices, although other forms of circles are possible.

The embodiments described herein also assume that the address is 32 bits wide, the index is 16 bits wide, and the vertex data of the triangle graphics circle is assumed to be approximately 100 bytes long. Other embodiments may use a wide range of addresses, indexes, data sizes and lengths.

4 is a flow diagram of one embodiment of a method for improving memory bandwidth utilization in a tiled graphics architecture. In block 410, determine whether the graphics circle crosses the first and second bins. If it is determined that the graphics circle crosses the first and second bins, block 420 writes data for a plurality of vertices corresponding to the graphics circle to a first bin storage area located in the memory device. This memory device may include main graphics memory or local graphics memory directly coupled to the graphics controller.

At block 430, a plurality of pointers are written to the second empty storage area located in the graphics memory. These plurality of pointers indicate memory locations for the plurality of vertex data. By writing the pointers to the second empty storage area instead of writing the vertex data, less data is moved from the processor to the graphics memory and memory bandwidth utilization is improved. These pointers will be retrieved along with the other second empty circular data by the graphics controller. The graphics controller will use this pointer to fetch vertex data from the first free storage area.

FIG. 5 is a flow diagram illustrating one embodiment of a method for enhancing memory bandwidth utilization in a tiled graphics architecture of a computer system in which a graphics memory is implemented as an area in main system memory and the graphics controller includes a vertex cache. The vertex cache provides a temporary storage for the vertex data and reduces the amount of vertex data that is moved between the graphics memory and the graphics controller located in the main system memory to improve graphics controller bandwidth utilization in the system memory.

Referring to FIG. 5, at block 505, the processor retrieves vertex data for the graphics prototype from system memory, and at block 510 the processor performs calculations on the vertex data. In this example, the vertex data for the graphics primitive includes three vertices, while in other embodiments the data in the graphics primitive may include any number of vertex data.

At block 515, the processor determines whether the graphics primitive crosses the first bin, and if there is any crossing, the processor writes the vertex data of the graphics primitive to the first bin storage area in system memory.

At block 520, the processor determines whether the graphics circle crosses the second bin. If it is determined that the graphics circle crosses the second bin, then at block 525, the processor writes three pointers to the second bin storage area in system memory. These pointers indicate the memory locations of the three vertices previously recorded in system memory.

At block 530, the processor determines whether the graphics circle crosses the third bin. If it is determined that the graphics circle crosses the third bin, then at block 535, the processor writes three pointers to a third bin storage area in system memory. These pointers indicate the memory locations of the three vertices previously recorded in system memory.

At block 540, the processor determines whether the graphics circle crosses the fourth bin. If it is determined that the graphics circle crosses the fourth bin, then at block 545, the processor writes three pointers to a fourth bin storage area in system memory. These pointers indicate the memory locations of the three vertices previously recorded in system memory.

Although the present embodiment describes a graphics circle that may possibly cross four bins, in other embodiments the graphics circle may cross two or more bins. Also, in one embodiment the bin may have a size of 128 * 64 pixels, but other sizes of frequencies are possible. Bin intersection determination may also be performed in a parallel manner instead of the serial approach as described above.

As shown at block 547, blocks 505 to 545 may be repeated until all circles have been classified into a plurality of bins.

At block 550, the graphics controller fetches data from the first free storage area. The data retrieved from the first free storage area and the vertex buffer includes vertex data for the graphics primitives previously written to the system memory at block 515.

In block 555 the graphics controller stores the vertex data in the vertex cache. In one embodiment, the vertex cache includes sixteen 4-way interleaved entries in each entry that can store 32 bytes of vertex data. In other embodiments, different numbers of entries and orientations are possible, and the amount of vertex data each entry can store may vary.

After the graphics controller fetches the first bin data and stores the vertex data in the vertex cache, at block 560 the graphics controller renders the first bin primitives. As part of the rendering process, the graphics controller determines which portion of each graphics prototype contained in the first bin data is included in the first bin and renders only the prototype of that portion.

After rendering the first bean, the graphics controller continues processing of the second bean. As a first step in the second bin process, at block 565 the graphics controller fetches data from the second bin storage area. The data fetched into the second bin storage area includes a pointer to the vertex data of the graphics circle, which is determined at block 520 to cross the second bin. At block 570, the graphics controller uses pointers to access vertex data previously stored in the vertex cache at block 555. Once the graphics controller accesses the vertex data, at block 575 the graphics controller renders the second empty circles.

At block 580, it is determined whether additional beans remain to be rendered. If additional beans remain, processing continues again at block 565. Blocks 565 to 580 are repeated until all bins are rendered, and processing ends at block 585. Note that the order of the empty renderings can be serial or discontinuous. The above embodiment can be normalized by some heuristics, and the second bin can be rendered first, and then the third, first and fourth bins. This allows for an optimization measure of overall system performance.

6 is a flow diagram illustrating one embodiment of a method of improving memory bandwidth utilization in a tiled graphics architecture of a computer system when the graphics memory is implemented with local graphics memory that is directly coupled to a graphics controller. Local graphics memory provides a storage location for the vertex data and reduces the amount of vertex data that is moved between the graphics memory and the graphics controller located in the main system memory to improve graphics controller bandwidth utilization in system memory. .

Referring to FIG. 6, at block 605, the processor retrieves vertex data for a graphics primitive from local graphics memory, or otherwise from system memory, and at block 610 the processor performs calculations on the vertex data. . In this example, the vertex data for the graphics primitive includes three vertices, while in other embodiments the data in the graphics primitive may include any number of vertex data. At block 615, the processor determines whether the graphics primitive crosses the first bin, and if so, the processor writes the vertex data of the graphics primitive to the first bin storage area in the local graphics memory.

At block 620, the processor determines whether the graphics circle crosses the second bin. If it is determined that the graphics prototype traverses the second bin, then at block 625, the processor writes three pointers to the second bin storage area in local graphics memory. These pointers indicate the three vertex memory locations previously recorded in local graphics memory.

At block 630, the processor determines whether the graphics circle crosses the third bin. If it is determined that the graphics circle crosses the third bin, then at block 635, the processor writes three pointers to a third bin storage area in local graphics memory. These pointers indicate the three vertex memory locations previously recorded in local graphics memory.

At block 640, the processor determines whether the graphics circle crosses the fourth bin. If it is determined that the graphics circle traverses the fourth bin, then at block 645, the processor writes three pointers to the fourth bin storage area in local graphics memory. These pointers indicate the three vertex memory locations previously recorded in local graphics memory.

Although the present embodiment describes a graphics circle that may possibly cross four bins, in other embodiments the graphics circle may cross two or more bins. Also, in one embodiment the bin may have a size of 128 * 64 pixels, but other sizes of frequencies are possible. The bin crossing determination may also be performed in a parallel manner instead of the serial approach as described above. For example, a circular bundle box can be used to find all the bins across a circle at once.

As shown in block 647, blocks 605 through 645 may be repeated until all circles have been classified into a plurality of bins.

At block 650, the graphics controller fetches data from the first empty storage area. The data fetched from the first free storage area and the vertex buffer contain vertex data for the graphics primitives previously written to the local graphics memory at block 615.

After the graphics controller fetches the first bin data, at block 660 the graphics controller renders the first bin primitives. As part of the rendering process, the graphics controller determines which portion of each graphics prototype contained in the first bin data is included in the first bin and renders only the prototype of that portion.

After rendering of the first bean, the graphics controller continues to process the second bean. As a first step of the second bin process, at block 665 the graphics controller fetches data from the second bin storage area. The data fetched into the second bin storage area includes a pointer to the vertex data of the graphics circle and is determined to intersect the second bin at block 620. At block 670, the graphics controller uses the pointers to access the vertex data previously stored in the vertex cache at block 615. Once the graphics controller accesses the vertex data, at block 675 the graphics controller renders the second empty circles.

At block 680, it is determined whether there are additional beans left to render. If additional beans remain, processing continues again at block 665. Blocks 665 to 680 are repeated until all bins are rendered, and processing ends at block 685. Note that the order of the empty renderings can be serial or discontinuous. The above embodiment can be generalized by any heuristic teaching method, and the second bin can be rendered first and then the third, first and fourth bins. This enables an optimized measure of overall system performance. For example, load balancing can be used to generalize loading for front-end and back-end processing in graphics controllers.

7 is a block diagram of a computer system including a graphics controller 740 that includes a vertex cache 742. The computer system of FIG. 7 also includes a processor 710 coupled to system logic device 720 via a processor bus 715. System logic device 720 provides communication between processor 710 and system memory 730. System memory 730 includes a graphics circular storage area 732. The graphics circular memory area 732 can be divided into memory areas for a plurality of bins.

System logic device 720 also serves to connect graphics controller 740 to processor 710 and system memory 730. The system of FIG. 7 also includes a display monitor 750 coupled to the graphics controller 740.

The system of FIG. 7 may be used as an embodiment of a method for improving memory bandwidth utilization as discussed above with respect to FIGS. 4 and 5. For example, the processor 710 may read the graphics circular vertex data from the graphics circular storage area 732. Processor 710 may then determine which bins cross the graphics circle. Processor 710 then writes the vertex data to the first empty storage area in graphics circular storage area 732. If it is determined that the graphics circle traverses the other bins, the processor 710 writes the pointers to other bin storage areas in the graphics circle storage area 732. These pointers indicate positions in the first empty storage area in which the vertex data is stored. In this example the pointers contain a 16 bit index from the memory location of the vertex data to be calculated. Still other embodiments may use different length indexes and / or addresses.

When the graphics controller 740 intends to process the first bin, the graphics controller 740 fetches the first bin data from the graphics circular storage area 732. The graphics controller 740 stores the vertex data for the graphics prototype in the vertex cache 742. Graphics controller 740 then renders the first bin including some of the graphics primitives contained within the first bin area.

For this example, the bin is 1328 * 64 pixels in size. Vertex cache 742 in this example is a 4-way set-associative scheme and contains 16 entries that store 32 bytes of vertex data. In other embodiments, different bin sizes and / or different cache arrangements are possible.

When the graphics controller 740 is ready to process the second bin, the graphics controller 740 fetches data for the second bin from the graphics circular storage area 732. If processor 710 previously determined that the graphics circle traversed the second bin, then the data for the second bin would include pointers to the vertex data of the graphics circle. Graphics controller 740 then uses that pointer to access vertex data stored in vertex cache 742. The vertex cache 742 improves memory bandwidth utilization by eliminating the need to fetch vertex data from the graphics circular storage area 732 when a copy of the vertex data is stored in the vertex cache 742, as in this example. It plays a role.

Once the vertex data is retrieved from the vertex cache 742, the graphics controller 740 can render the second bean. Subsequent beans can be processed in the same way until all beans are rendered.

In the foregoing specification, the invention has been described with reference to specific embodiments. However, it is apparent that various modifications and changes can be made without departing from the spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

In the specification, "an embodiment", "an embodiment", "an embodiment" or "another embodiment" includes at least some embodiments of a particular feature, structure, or characteristic described in connection with the embodiment, It is not meant to be included in all embodiments. Various appearances of "an embodiment", "one embodiment" or "an embodiment" do not necessarily all refer to the same embodiment.

Claims (17)

Determining if a graphics primitive crosses the first tile and the plurality of second tiles, Writing a plurality of vertices corresponding to the graphics prototype in a first bin storage area located in a memory device, and Writing a plurality of pointers indicating positions of data with respect to the plurality of vertices, into a plurality of second empty storage areas located in the memory device; How to include. In claim 1, The writing of the plurality of vertices corresponding to the graphics primitives in a first empty storage area located in the memory device may include: writing data about the plurality of vertices corresponding to the graphics primitives in a first frame buffer; Writing to an empty storage area. In claim 2, Writing a plurality of pointers to a plurality of second empty storage areas located in the memory device includes writing the plurality of pointers to a plurality of second empty storage areas located in a frame buffer. . In claim 1, The writing of the plurality of vertices corresponding to the graphics primitives in a first empty storage area located in the memory device may include: writing data about the plurality of vertices corresponding to the graphics primitives in a first memory; Writing to an empty storage area. In claim 4, Writing a plurality of pointers into a plurality of second empty storage areas located in the memory device, comprising recording a plurality of pointers into a plurality of second empty storage areas located in main memory. In claim 5, The method is Loading one of the plurality of vertices into a vertex cache, Reading one of the plurality of pointers into the graphics controller, and Accessing data for one of a plurality of vertices stored in the vertex cache using one of the plurality of pointers How to include more. An apparatus comprising a graphics controller for fetching raw data from a plurality of free storage areas located in memory, the apparatus comprising: The raw data includes a plurality of pointers indicating memory locations for data corresponding to vertices, The graphics controller further extracts data corresponding to the vertices indicated by the plurality of pointers from an additional empty storage area. Device. In claim 7, And the memory comprises a main memory device. In claim 7, And the graphics controller fetches data corresponding to the vertices indicated by the plurality of pointers from the frame buffer. In claim 7, And the graphics controller fetches data corresponding to the vertices indicated by the plurality of pointers from the main memory device. In claim 7, The device further comprises a vertex cache, And the graphics controller fetches data corresponding to vertices indicated by the plurality of pointers from the vertex cache. In claim 11, And wherein the vertex cache comprises a plurality of entries each storing 32 bytes of vertex data. Processor, A memory controller connected to the processor, A main memory connected to the memory controller, and A graphics controller for extracting raw data from a plurality of free storage areas located in the main memory As a system comprising: The raw data includes a plurality of pointers indicating memory locations for data corresponding to vertices, The graphics controller further extracts data corresponding to the vertices indicated by the plurality of pointers from an additional empty storage area. system. In claim 13, And the graphics controller fetches data corresponding to vertices indicated by the plurality of pointers from a frame buffer connected to the graphics controller. In claim 13, And the graphics controller fetches data corresponding to the vertices indicated by the plurality of pointers from the main memory. In claim 13, The graphics controller further includes a vertex cache, And the graphics controller fetches data corresponding to the vertices indicated by the plurality of pointers from the vertex cache. The method of claim 16, The vertex cache includes a plurality of entries each storing 32 bytes of vertex data.

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