KR100531840B1 - Method for computing branch metric in viterbi decoder and circuit thereof - Google Patents

Abstract

The present invention relates to a method for calculating a branch metric of a Viterbi decoder and a circuit thereof. In particular, in a Viterbi decoder using multiple ACS, the input branch metric of each ACS can be obtained simultaneously using simple hardware for faster data processing. It aims to make it possible and to facilitate the circuit design. The present invention for this purpose assumes that two Add-Compare-Select (ACS) processing one butterfly operation constitute one Processing Unit (PES), the branch metric of Viterbi decoder with multiple ACS. A calculation method comprising: a first step of obtaining a plurality of encoded data bits for one branch of one butterfly by sequentially counting a state value excluding an index value for each of a plurality of PEs; A second step of obtaining a bit metric corresponding to a code rate and an inverted bit metric inverted for each of the plurality of encoded data bits for the plurality of encoded data bits, and selecting one of the bit metric and the inverted bit metric for each of the plurality of PEs And summing the selected metrics to perform a third step of simultaneously obtaining each branch metric.

Description

METHODO FOR COMPUTING BRANCH METRIC IN VITERBI DECODER AND CIRCUIT THEREOF

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital communications, and more particularly, to branch branch metric calculation methods and circuits in a Viterbi decoder with multiple Add-Compare_Select (ACS).

An error occurs during data transmission in digital communication, and error correcting coding is required to correct the error.

In error correction encoding, a block code for encoding / decoding data in units of blocks and a convolutional code for performing encoding by comparing previous data with current data using a predetermined length of memory. code).

The most representative method of convolutional coding is the Viterbi algorithm.

The Viterbi algorithm increases the complexity exponentially in proportion to the magnitude of the constraint length (k), which is currently used up to k = 9 and more than k> 9 so complex that it is not actually used.

In fact, the structure of k = 9 is used in the CDMA (IS_95) system, and the Viterbi code with k = 9 is used together with the Turbo code in the IMT-2000 system for the next generation mobile communication.

In general, the Viterbi decoder is largely composed of a branch metric generator (BMG), add-compare-select (ACS), and trace back (TB).

The BMG is a part for obtaining a branch metric value from input data.

The ACS compares two branch metric values and path metric values generated by previous data and compares two values that transition to the same state, and selects a small value or a large value as state transition information. This is a part for transmitting to TB the decision bit stored in the PM and indicating the path.

The TB stores a decision bit obtained from the ACS and then obtains a survival path through trace back and outputs a result value from the path.

The branch metric is a metric for the transition between states at a time on Trellis as determined by a convolutional encoder.

That is, the branch metric represents the degree of likelihood between the encoded data and the received data generated in one branch of the trellis.

Here, the encoded data is determined when the convolutional encoder is determined, and thus can be obtained in advance at the receiving end.

The path metric is a value obtained by continuously adding branch metric values for each state from the beginning of a reception information block to a point in time, and is a metric for each state at that time.

Figure 1 shows a basic trellis element for a convolutional encoder with a code rate of 1 / n.

In Figure 1 Represents the jth state at time (t) Represents a branch metric that transitions from state j to state 2j when time t becomes (t + 1).

A code rate of 1 / n means that n bits are output after convolutional encoding on one input bit.

The table of FIG. 2 shows an example of a branch metric for the case where the received signal r is divided into four values, where y is obtained from the state transition of the trellis at the transmitting signal or the receiving end, that is, encoded n bits Represents one bit value of data.

In FIG. 2, an underlined value means a stronger value than an underlined value.

Therefore, when the transmission signal y or the value obtained by the reception side is' 0 ', the reception signal r becomes' 'With the largest metric, that is, the largest likelihood value, and' 0 ',' 1 ',' The size of the metric value is large in order.

In general, the branch metric is calculated based on a lookup table that contains mainly a bit metric.

In other words, a branch metric reads a value from a lookup table that stores a bit metric of each bit-wise with the corresponding received bit for n bits generated in each branch. Find in addition.

In general, the same look-up behavior per Trellis step is used to obtain branch metrics. This is done n times for each branch.

So for a very fast decoder It will be designed to have two lookup table circuits, and for a simple decoder it will use the same lookup table. It will be designed to read once.

here, Represents the number of memories of the convolutional encoder Indicates the number of unit input information.

For example, the code rate 1/3 convolutional encoder used in the IMT-2000 system may be implemented as shown in FIG. 3.

At this time, , , And the total number of states is 256.

Accordingly, the Viterbi decoder corresponding to the convolutional encoder of FIG. You need to read the burnup lookup table or create 768 lookup table circuits.

However, in the related art, even a Viterbi decoder having a simple structure corresponding to a convolutional encoder as shown in FIG. 3 requires much time because the lookup table has to be read 768 times, resulting in a long overall decoding time.

In addition, in the prior art, when implementing a fast Viterbi decoder corresponding to the convolutional encoder as shown in FIG. 3, since the circuit has to be read out as many times as the number of ACS used among 768 values, the complexity becomes very large. There is a problem.

However, in most cases, it is not necessary to implement access to all the bit metrics at the same time, so it is only necessary to simultaneously obtain the number of branch metrics as many as the number of ACSs.

Accordingly, the present invention provides a Viterbi decoder using multiple ACS to improve the above problems, by implementing the input branch metric of each ACS at the same time by using the characteristics of the state of each ACS input. Viterbi decoder designed for easy circuit design by enabling fast data processing and simple implementation of a circuit for simultaneously obtaining the input branch metric of each ACS with the complexity of obtaining the input branch metric of one ACS. It is an object of the present invention to provide a metric calculation method and a circuit thereof.

In order to achieve the above object, the present invention assumes that two Add-Compare-Select (ACS) processing one butterfly operation constitute one Processing Unit (convolution code). In the Viterbi decoder's branch metric calculation method, which obtains a branch metric for a state transition at any time determined by the summation by a butterfly operation, a state value excluding an index value is sequentially counted for each of a plurality of PEs. A first step of obtaining a plurality of encoded data bits for one branch of one butterfly, a bit metric corresponding to a code rate for each of the plurality of encoded data bits for each of the plurality of PEs, and an inverted bit inverting them Obtaining a metric, and selecting one of a bit metric and an inverted bit metric for each of the plurality of PEs and selecting the selected metric. Calculated by summing the rigs is characterized in that configured to perform the third step to obtain the respective branch metrics at the same time.

The first step is to calculate the encoded data bits for one path metric by logically combining the coefficient values while sequentially counting the PE state values excluding the processing unit (PE) index value, and the four branches of the butterfly structure. encoding data for the four path metrics included in the input ACS from the encoding data bits obtained in the above process by referring to the relationship between each path metric having the same bit inversion relationship between the two encoded data generated in the (branch). It is characterized in that the process of simultaneously obtaining the bits.

In the second step, the bit metrics for encoding data bits '0' and '1' are simultaneously obtained by selecting a survival path having a minimum value.

The bit metric may be obtained by inverting a lower bit except for the most significant bit of the received data with respect to the encoded data bit '0' and inverting the most significant bit of the received data with respect to the encoded data bit '1'.

The third step may include selecting each number of bit metrics corresponding to a code rate according to encoding data bits of one path metric, inverting the selected bit metric, and a relationship between each path metric. And summing up the eight selected metrics for the four path metrics by summing the respective selected bit metrics and the inverted bit metrics.

In addition, the present invention, in the Viterbi decoder having multiple ACS in order to achieve the above object, while counting the PE state value excluding the processing unit (PE) index value sequentially and logically combines the count value to the input ACS An encoding data bit operator that simultaneously obtains each encoded data bit for four path metrics, and a plurality of consecutive received data bits corresponding to a code rate by performing logical operation simultaneously for each of the encoded data bits. A bit metric operator that simultaneously obtains the bit metrics of and selects the corresponding bit metric according to the encoding data bits for the one path metric obtained above, and adds the selected bit metric and its inverted bit metric to obtain the branch metric Refer to the relationship to the metrics from the branch metrics Provided with a branch metric computing unit to obtain the respective branch metrics for the remaining path metric at the same time, characterized in that configuration.

Hereinafter, the present invention will be described in detail with reference to the drawings.

In the embodiment of the present invention, for convenience of description, an operation of a Viterbi decoder corresponding to the code rate 1/3 convolutional encoder of FIG. 3 used in the IS-95 and IMT-2000 systems will be described.

4 illustrates an arbitrary butterfly structure on the trellis corresponding to the convolutional code of FIG.

here, Is 8-bit data indicating a state, which is a memory (flip-flop) value in the convolutional encoder of FIG.

The LSB (Least Significant Bit) of the state 'Is assumed.

Represents branch metrics, with subscripts representing input information values.

In other words, Is the branch metric when the input value is '0' in the current state. In FIG. 4, when the code rate is 1/3, three bits of encoded data ( , , or , , ) And a bit metric, which is a similarity value of the received data value corresponding to the position.

Referring to FIG. 4, two states at one time point t and two states at a next time point t + 1 always have a paired structure, which is called a butterfly.

The two states at time t are MSB (Most Significant Bit) ' If the value of 'is'0' and '1' and the remaining bits have the same value.

In addition, the two states at the time point t + 1 are set to '0' if the input of the convolutional encoder is '0' for the last bit LSB after shifting the state value at the time point t to the left. Status is '1' if it is '1'.

As shown in Figure 4, one butterfly on the trellis of a convolutional encoder with a code rate of 1 / n has four branches, most of the convolutional encoder structure, i.e. each output bit. In a structure where the input value and the MSB value must be XORed to obtain a value, a three-bit value encoded in one butterfly has two values, and the two values are bit-wise. inversion) relationship.

That is, the encoded data of each branch has an inverse relationship of '0' and '1' in bits.

Therefore, only two branch metrics are needed for four branches of a butterfly.

3 and 4, the top branch, that is, the MSB of the state value Is the '0' and the encoded output bit when the input is '0' ( , , ) Can be obtained as shown in Equation 1 below.

[Equation 1]

here, Wow Are inversely related to each other, so if only the encoded bits in one branch are obtained, all encoded bits in the other three branches can be known.

By the way, the receiving side may have all these output bits in advance, but when using multiple ACS, it is difficult to simultaneously access the corresponding memory in order to obtain these values simultaneously.

However, when using multiple ACSs, the butterfly structural characteristics of a typical convolutional encoder and the state characteristics of the inputs of each ACS can be used to obtain encoded data in a very simple structure, and to obtain branch metrics from it quickly and easily. .

An ACS operation for obtaining a path metric of any one state is called one ACS, and FIG. 5 shows two ACS structures corresponding to one butterfly of FIG.

Since the block diagram of FIG. 5 is a general circuit configuration, detailed description thereof will be omitted.

In the embodiment of the present invention, it is assumed that the structure of FIG. 5, which consists of two ACSs that process all one butterfly, is one processing unit (PE).

The table of FIG. 6 shows each PE input / output state of a Viterbi decoder having four PEs, that is, eight ACSs.

The input branch metric in each state of each PE can be obtained from the encoding bit values for only one branch of the butterfly.

The table of FIG. 7 shows a state of the first input of two inputs of each PE, and each bit representing the state corresponds to each m value of Equation 1 above.

In the table of Figure 7, MSBs of all PE states ( ) Is '0' and the 2 bits after the MSB are equal to each PE's number and are not changed in that PE.

That is, looking at the table of Figure 7, the most significant bit ( ) Is '0' and the lower 5 bits ( To ) Is '00000 ~ 11111', and each PE has the same value and 2 bits after the most significant ( , It can be seen that has a value corresponding to the number of each PE, that is, '00, 01,10,11 'respectively.

Therefore, in [Equation 1] Wow The value of is determined for each PE.

Therefore, at the same time, the lower 5 bits of the state value of all PEs ( To ) Is sequentially increased from '00000' to '11111' to obtain encoded data and branch metrics corresponding to the state.

In the case of using 8 ACSs, that is, using 4 PEs, the input metrics of all PEs can be obtained using a 5-cycle counter of 32 cycles for all 256 states at one time, as shown in the table of FIG.

Therefore, the relationship between the status bits corresponding to each PE and the encoded data may be represented as shown in the table of FIG. 8, where Represents an XOR operation.

In the embodiment of the present invention, a circuit for obtaining encoded data for all PEs based on the table of FIG. 8 is shown in FIG.

That is, the circuit of FIG. 9 includes a 5-bit counter 110 that sequentially counts the lower 5 bits of PE from '00000' to '11111', and the count value of the counter 110 ( , , ) And the exclusive OR of the encoded data bits of PE0, PE3 ( ) XOR gate 121 to obtain the value and the count value of the counter 110 ( , , ) And the exclusive OR of the encoded data bits of PE0, PE1 ( ) XOR gate 122 to obtain the coefficient value of the counter (110) , , ) And the exclusive OR of the encoded data bits of PE0 to PE3 ( XOR gate 123 to obtain and inverts the output value of the XOR gate 121 to encode the encoded data bits of PE1 and PE2 ( ) And the output values of the XOR gate 122 are inverted to encode the encoded data bits of PE2 and PE3 ( Is configured to include an inverter (132) for obtaining.

However, since only the encoded data bits of PE0 can be obtained, the encoded data bits of the remaining PE1 to PE3 can be obtained, so that the inverters 131 and 132 provided in the circuit of FIG. 9 are unnecessary components in the actual circuit configuration.

Therefore, the bit metric can be obtained from the encoded data and the received data.

That is, the bit metrics corresponding to the encoded data bits and the received data may be obtained as in the lookup table shown in the table of FIG. 10.

In the table of FIG. 10, the bit metric corresponding to '0' of the encoded data bit is set to '0' when the value obtained by quantizing the received data of the Viterbi decoder with 4 bits has the largest positive value, that is, 0111. The bit metric corresponding to data bit '1' is set to '15'.

Therefore, the Viterbi decoder selects a path having a small path metric value as a survival path.

That is, referring to the table of FIG. 10, when the encoding data bit is '0', the bit metric is a bit-wise inversion of the lower 3 bits of the 4-bit received signal and the encoding data bit is '1'. In this case, it can be seen that the bit metric is a value obtained by inverting the upper 1 bit of the 4-bit received signal.

Here, it can be seen that the two bit metric values have a bit-wise inversion relationship with each other.

Therefore, a circuit for obtaining a bit metric using the above characteristics can be configured as shown in FIG.

That is, the circuit of FIG. , Inverters 211 to 214 for inverting each bit of the < RTI ID = 0.0 > and < / RTI > ) And the receive bit corresponding to the encoded data bit " 1 " ) And a first buffer 221 for outputting the received signal ( ) And a reception bit corresponding to encoding data bit "0" by storing the inverted signal of the inverters 212 to 214. It is configured to include a second buffer 222 that outputs.

In other words, the circuit for obtaining the bit metric can be configured with 12 inverters and 6 buffers.

By the way, the lookup table shown in FIG. 10 may vary depending on how the quantization is performed and how the bit metric value is determined. However, if the bit metric characteristic between the received data and the encoded data is analyzed, the circuit can be implemented with a simple configuration as shown in FIG. Do.

In addition, in order to obtain a branch metric when the code rate is 1/3, each bit metric for encoding data bits '0' and '1' is obtained for three consecutive received signals, and the encoding data bits are obtained. It is necessary to select a bit metric corresponding to and sum it with its inverted bit metric.

delete

In this case, since the encoded data bits have an inverse relationship having both '0' and '1' in each PE (butterfly structure) as described above, both the encoded data bits '0' and '1' as shown in FIG. It is highly desirable to obtain a bit metric from the received signal at the same time.

A circuit configuration for this is shown in FIG.

The circuit of FIG. 12 utilizes the characteristics between the encoded data bits obtained from the circuit of FIG. 9 and the encoding bits generated from each branch, that is, the pairs have the same bit-wise inversion relationship. Fig. 11 shows a method of simultaneously obtaining the input branch metrics of each PE by selecting and adding the bit metric values obtained in the circuit of Fig. 11.

That is, the circuit of FIG. According to the bit metric ( ) ( A multiplexer 311 that selects one of the According to the bit metric ( ) ( A multiplexer 312 that selects one of the According to the bit metric ( ) ( Multiplexer 313 to select one of the multiplexers, inverters 321 to 323 for inverting the bit metrics respectively selected by the multiplexers 311 to 313, and bits in the multiplexers 311, 312 and 313. Sum the metrics to get branch metrics ( The adder 331 for outputting the bit metric and the bit metrics from the inverters 321, 322, 323 are added to the branch metrics ( And adds the bit metric of the adder 332 and the inverter 321 and the multiplexer 312, 313 to the branch metric ( And adds the bit metric of the adder 333 and the multiplexer 311 and the inverters 322 and 323. The adder 334 for outputting the sum of the bit metrics in the inverters 321 and 322 and the multiplexer 313 is added to the branch metrics ( The adder 335 outputting the sum of the bit metrics from the multiplexers 311 and 312 and the inverter 323 adds the branch metrics ( The adder 336 outputting the sum of the bit metrics of the multiplexer 311 and 313 and the inverter 322 is added to the branch metric. The adder 337 for outputting the sum of the bit metrics from the multiplexer 312 and the inverters 321 and 323 adds the branch metrics ( It is configured to include an adder 338 for outputting a).

The reason why the inverters 321 to 323 are connected to the output terminals of the multiplexers 311 to 313 is when encoding data bits '0' obtained from the circuit of FIG. 11 having a bit-wise inversion relationship with each other. This is for simultaneously obtaining a bit metric of when and a bit metric when the encoding data bit is '1'.

If there is no bit-wise inversion relationship between the bit metric when the encoding data bit is '0' and the bit metric when the bit is '1', the value corresponding to the output value of the inverters 321 to 323 is a multiplexer ( 311 to 313) are not selected by the encoding data bit value.

On the other hand, the present invention as described above is applicable in the same way in most systems using the Viterbi decoding method.

For example, even if you selectively use two convolutional encoders with different code rates, such as an IMT-2000 system, you can use a multiplexer (MUX), an XOR gate, and an inverter, depending on which code rate you use. You can implement it.

As described in detail above, the present invention enables faster data processing by simultaneously obtaining the input branch metrics of each ACS using simple hardware so that each of the multiple ACSs constituting the Viterbi decoder can operate simultaneously. This has the effect of improving system performance.

1 is an exemplary diagram showing a basic trellis structure of a convolutional code having a code rate of 1 / n.

2 is a table illustrating branch metrics.

3 is a circuit diagram of a code rate 1/3 convolutional encoder;

4 is an exemplary view showing a butterfly structure on trellis for the convolutional code in FIG.

5 is a block diagram of an ACS circuit for general path metric calculation.

6 is a table showing four PE input and output states.

7 is a view of FIG. Table shows four PE status values.

8 is a table showing a relationship between four PE state values and encoded data.

9 is a circuit diagram of an encoded data bit operator in an embodiment of the present invention.

10 is an exemplary view of a lookup table showing bit metric values.

Figure 11 is a circuit diagram of a bit metric operator in an embodiment of the invention.

Figure 12 is a circuit diagram of a branch metric operator in an embodiment of the invention.

Explanation of symbols on the main parts of the drawings

110: counter 121-123: XOR gate

131,132,211 ~ 214,321 ~ 323: Inverter 221,222: Buffer

311 ~ 313: Multiplexer 331 ~ 338: Adder

Claims (9)

Assuming that two Add-Compare-Selects (ACSs) processing one butterfly operation constitute one Processing Unit (PE), at any point in time determined by convolutional coding In the Viterbi decoder branch metric calculation method wherein the branch metric for the state transition is obtained by the butterfly operation, A first step of sequentially counting state values excluding index values for each of a plurality of PEs to obtain a plurality of encoded data bits corresponding to one branch of one butterfly; Obtaining a bit metric corresponding to a code rate and an inverted bit metric inverted for each of the plurality of encoded data bits for each of the plurality of PEs; And performing a third step of selecting one of a bit metric and an inverted bit metric for each of the plurality of PEs, and summing the selected metrics to simultaneously obtain each branch metric. . The method of claim 1 wherein the first step is A first process of obtaining a plurality of encoded data bits for one path metric using a state value for a processing unit (PE) of a plurality of PEs, Obtaining each encoded data bit for the path metric corresponding to each of the remaining PEs except the arbitrary PE from the encoded data bits by referring to the relationship of the respective encoded data for each of the plurality of path metrics for the plurality of PEs; A method for calculating branch metrics of a Viterbi decoder, characterized by performing two processes. The method of claim 1 wherein the second step is A method for calculating the branch metrics of a Viterbi decoder, wherein the bit metrics for encoding data bits '0' and '1' are obtained by selecting a survival path whose path metric is the minimum value. The method of claim 1 or 3, wherein the bit metric is A method for calculating branch metrics of a Viterbi decoder, characterized by inverting the least significant bits of the received data with respect to the encoded data bit '0' and inverting the most significant bits of the received data with respect to the encoded data bit '1'. The method of claim 1 wherein the third step is A first process of respectively selecting a number of bit metrics corresponding to a code rate according to encoding data bits for one path metric; A second process of inverting the selected bit metric; The branch of the Viterbi decoder is performed by summing the bit metrics selected above and the inverted bit metrics with reference to the relationship between the path metrics to obtain two branch metrics for each of the plurality of path metrics. How metrics are calculated. Assuming that two Add-Compare-Selects (ACSs) processing one butterfly operation constitute one Processing Unit (PE), at any point in time determined by convolutional coding In a Viterbi decoder that obtains a branch metric for a state transition by a butterfly operation, Encoded data bit calculating means for obtaining respective encoded data bits for four path metrics, Bit metric calculating means for obtaining a bit metric for obtaining a bit metric corresponding to a code rate and an inverted bit metric for each of the four encoded data bits; And branch metric calculating means for summing each bit metric and the inverted bit metric for each of the four path metrics to obtain each branch metric. The method of claim 6, wherein the encoding data bit calculating means Status value of lower bit except PE index value (( To ) Is a counter that sequentially counts '00000' through '11111', Count value of the counter ( , , ) And the exclusive OR of the encoded data bits of PE0, PE3 ( A first XOR gate to obtain Encoding data bits of PE1 and PE2 by inverting the output value of the first XOR gate A first inverter for obtaining Count value of the counter ( , , ) And the exclusive OR of the encoded data bits of PE0, PE1 ( And a second XOR gate for Inverts the output value of the second XOR gate so that the encoded data bits of PE2 and PE3 ( And a second inverter for obtaining Count value of the counter ( , , ) And the exclusive OR of the encoded data bits of PE0 to PE3 ( And a third XOR gate for obtaining < RTI ID = 0.0 > The method of claim 6, wherein the bit metric calculation means Receive signal ( , Third to sixth inverters that invert each bit of The output signal and the reception signal of the third inverter ( ) And the receive bit corresponding to the encoded data bit " 1 " A first buffer for outputting Receive signal ( ) And a reception bit corresponding to encoding data bit "0" by storing the inverted signals of the fourth to sixth inverters. And a second buffer for outputting C), wherein the branch metric calculation circuit of the Viterbi decoder is configured. The method of claim 6, wherein the branch metric calculating means Encoding data bits ( According to the bit metric ( ) ( A first multiplexer that selects one of Encoding data bits ( According to the bit metric ( ) ( A second multiplexer that selects one of Encoding data bits ( According to the bit metric ( ) ( A third multiplexer that selects one of A seventh to ninth inverters for inverting bit metrics selected from the first to third multiplexers, respectively; The bit metrics in the first to third multiplexers are summed to form branch metrics ( A first adder for outputting The bit metrics in the seventh to ninth inverters are summed to form branch metrics ( A second adder that outputs A branch metric is obtained by summing bit metrics of the seventh inverter and the second and third multiplexers. With a third adder that outputs A branch metric is obtained by summing bit metrics of the first multiplexer and the eighth and ninth inverters. With a fourth adder that outputs A branch metric is obtained by summing bit metrics of the seventh and eighth inverters and the third multiplexer. With a fifth adder that outputs A branch metric is obtained by summing bit metrics of the first and second multiplexers and the ninth inverter. A sixth adder for outputting A branch metric is obtained by summing bit metrics of the first and third multiplexers and the eighth inverter. With a seventh adder that outputs A branch metric is obtained by summing bit metrics of the second multiplexer and the seventh and ninth inverters. And an eighth adder for outputting a), wherein the branch metric calculation circuit of the Viterbi decoder is configured.