KR100521323B1 - Jtag circuit of semiconductor memory device with ball pin - Google Patents

Abstract

The J-TECH circuit of the semiconductor memory device according to the present invention provides a test target circuit section, a step control circuit, a command register, a confirmation information register, a bypass register, a selection circuit, and a test control circuit. The step control circuit receives a test mode selection signal synchronized with a test clock and outputs a test mode code of 4 bits corresponding to the test mode. The command register accepts test data and outputs a three-bit command code corresponding to the test mode by controlling the lower third bit code of the test mode codes of the step control circuit. The test control circuit combines the test mode code and the command code to output a control signal that cuts off the current supplied to the test target circuit during an operation other than a test operation. This can reduce current consumption during operation other than the test operation.

Description

JTAG CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE WITH BALL PIN

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a joint test access group circuit (JTAG circuit) for testing a connection state of a ball grid array (BGA).

Applications of semiconductor memory devices range from home appliances to the industrial sector. Recently, as the size of home appliances decreases, the size of the semiconductor memory device also decreases. In line with this trend, the package form has been changed to a BGA package in which a ball is mounted instead of a pin. In the case of a semiconductor memory device using a BGA package, an international standard test circuit described in JTAG IEEE 1149.1 is incorporated to check pin open or short. The test operation of the semiconductor memory device may be performed independently of the operation of the semiconductor memory cell.

1 is a block diagram of a semiconductor memory device having a conventional J-Tech circuit.

Referring to FIG. 1, the semiconductor memory device 1 may include a memory cell / core 100, a test target circuit unit 200, a step control circuit 300, a command register 400, a confirmation information register 500, and a bypass. A register 600 and selection circuit 700 are provided. The memory cell / core 100 includes a plurality of cells for storing data and pads for transferring data input / output to the cells. The test target circuit unit 200 includes n test circuits BSR1, BSR2,... BSRn-1, BSRn connected to the corresponding pads, respectively, where n is a positive integer. The step control circuit 300 receives a test mode selection signal TMS synchronized with a test clock TCK and transmits test mode codes CD1, CD2, CD3, and CD4 corresponding to the test mode to the command register 400. ), The confirmation information register 500, the bypass register 600, and the selection circuit 700.

The command register 400 outputs the command codes IR0, IR1, IR2 to the selection circuit 700 under the control of the test mode code CD3 supplied from the step control circuit 300. The bypass register 500 outputs the test data TDI input from the outside to the selection circuit 700 under the control of the test mode code CD1 supplied from the step control circuit 300. The confirmation information register 600 is internally controlled by the control of the test mode code CD2 informing the confirmation operation of the memory characteristic information (characteristics of memory such as x4, x8, and x16) supplied from the step control circuit 300. Output the characteristic information programmed as. The selection circuit 700 is controlled in the registers 400, 500, 600 and the nth th test target circuit BSRn by the control of the test mode code CD4 supplied from the step control circuit 300. Optionally outputs the supplied pin data Dn.

The operation of the test target circuit unit 200 is independent of the operation of the memory cell / core 100. That is, when the test operation is terminated, the test target circuit unit 200 does not need to operate during the normal operation of the memory cell / core 100. However, the conventional circuit to be tested 200 has a problem in that an on state is maintained even during normal operation of the memory cell / core 100 other than a test operation, thereby causing continuous current consumption.

Accordingly, an object of the present invention is to provide a J-TECH circuit of a semiconductor memory device capable of reducing current consumption generated during normal operation other than the test operation.

(Configuration)

According to one aspect of the present invention for achieving the above object, a semiconductor memory device having a plurality of ball pins as an input / output device corresponds to a test mode selected in response to a test mode selection signal synchronized with the test clock A step control circuit for outputting a test mode code; Command storage circuitry for receiving test data and storing the command code corresponding to the test data in response to the test mode code; A test control circuit outputting a control signal informing of the start of a test operation in response to the test mode code and the command code; A plurality of test target circuits for storing pin data supplied through corresponding ball pins in response to the control signal and for shifting the stored pin data in response to the test clock; Each of the circuits to be tested has an output terminal, a comparator for comparing a voltage level of corresponding pin data with a reference voltage in response to the control signal and outputting a comparison signal through the output terminal as a comparison result; An inverter for inverting the comparison signal; A register to store an output of the inverter synchronized with the test clock; A switch connected to an output terminal of the comparator and discharging the output terminal in response to the control signal.

In this embodiment, the test control circuit comprises: a first logic circuit for combining the command code to output a first combined signal; A second logic circuit for combining the test mode codes to output a second combined signal; A third logic circuit for combining the first and second combined signals to output a third combined signal; A fourth logic circuit for combining the third combined signal to output a fourth combined signal; And a flip-flop that stores the fourth combined signal as the control signal in response to the third combined signal.

In this embodiment, the switch circuit includes an NMOS transistor having a current path formed between the comparison circuit and a ground power supply and a gate controlled by the control signal.

In this embodiment, the register includes a shift register for shifting the output of the inverter stored in response to the test clock.

In this embodiment, the command code is composed of three bits, and the first logic circuit includes: a first NAND gate which combines and outputs the lower two bits of the command code; An inverter for inverting and outputting the highest 1 bit of the command code; And a second NAND gate configured to combine the output signals of the first NAND gate and the inverter to output the first combined signal.

In this embodiment, the test code is composed of four bits, and the second logic circuit comprises: a first inverter for inverting the least significant one of the test mode codes; A second inverter for inverting the highest 1 bit of the test mode code; And a NAND gate configured to combine the lower second bit of the test mode code and the output signals of the first and second inverters to output the second combined signal.

In this embodiment, the third logic circuit includes a NOR gate that outputs a third combined signal by combining the first and second combined signals.

In this embodiment, the fourth logic circuit comprises: a first delay circuit for inverting and outputting the third combined signal; A second delay circuit for delaying and outputting the inverted third combined signal; And a NOR gate configured to combine the output signals of the first delay circuit and the second delay circuit to output the fourth combined signal.

In this embodiment, the first delay circuit comprises an odd number of inverters connected in series.

In this embodiment, the second delay circuit comprises an even number of inverters connected in series.

(Action)

Such a device can cut off current consumed during normal operation of the cell memory / core other than the test operation.

(Example)

Reference to the drawings according to an embodiment of the present invention will be described in detail with reference to Figs.

2 is a block diagram of a semiconductor memory device having a J-Tech circuit of the present invention.

Referring to FIG. 2, the J-TECH circuit of the semiconductor memory device according to the present invention may include a memory cell / core 100, a test target circuit unit 200, a step control circuit 300, a command register 400, and a confirmation information register 500. ), A bypass register 600, a selection circuit 700, and a test control circuit 800. The memory cell / core 100 includes a plurality of cells for storing data and pads for transferring data input / output to the cells. The test target circuit unit 200 includes n test circuits BSR1, BSR2,... BSRn-1, BSRn connected to the corresponding pads, respectively, where n is a positive integer. Each of the test target circuits BSR1, BSR2,... BSRn-1, BSRn performs a next test on the pin data D input to the comparator and the comparator for receiving pin data D from the ball pin. It includes a shift register for transfer to the target circuit. In addition, a current path formed between the PMOS transistor PM0 having a current path formed between the voltage power supply VCC and the comparator and a gate controlling the current path and the comparator and the ground power supply VSS; An NMOS transistor NM0 having a gate for controlling the current path is included.

The step control circuit 300 receives a test mode selection signal TMS synchronized with a test clock TCK and transmits test mode codes CD1, CD2, CD3, and CD4 corresponding to the test mode to the command register 400. ), The confirmation information register 500, the bypass register 600, the selection circuit 700, and the test control circuit 800. The command register 400 stores the command codes IR0, IR1, and IR2 by the selection circuit 700 and the test control circuit under the control of the test mode code CD3 supplied from the step control circuit 300. To 800.

The bypass register 500 outputs test data TD input from the outside to the selection circuit 700 under the control of the test mode code CD1 supplied from the tap control circuit 300. The confirmation information register 600 is internally controlled by the control of the test mode code CD2 informing the confirmation operation of the memory characteristic information (characteristics of memory such as x4, x8, and x16) supplied from the step control circuit 300. Output the characteristic information programmed as. The selection circuit 700 is controlled in the registers 400, 500, 600 and the nth th test target circuit BSRn by the control of the test mode code CD4 supplied from the step control circuit 300. Optionally outputs the supplied pin data Dn. The test control circuit 800 combines the test mode codes CD1, CD2, and CD4 of the step control circuit 300 and the command codes IR0, IR1, and IR2 of the command register 400 to perform the test. A control signal for controlling the target circuits BSR1, BSR2, ... BSRn-1, BSRn is output.

3 is a detailed circuit diagram of a test control circuit included in the J-Tech circuit of the present invention.

Referring to FIG. 3, the test control circuit 800 included in the J-Tech circuit according to the present invention includes a first logic circuit 810, a second logic circuit 820, a Noah gate 830, and a third circuit. Logic circuit 840 and flip-flop 890. The first logic circuit 810 includes two NAND gates 811 and 813 and an inverter 812. First and second input terminals of the NAND gate 811 are connected to first and second output terminals of the command register 400, respectively, and output terminals are connected to first input terminals of the NAND gate 813. do. An input terminal of the inverter 812 is connected to a first output terminal of the command register 400, and an output terminal is connected to a second input terminal of the NAND gate 813. The first input terminal of the NAND gate 813 is connected to the output terminal of the NAND gate 811, the second input terminal is connected to the output terminal of the inverter 812, and the output terminal is the noah. Is connected to the first input terminal of the gate 830.

The second logic circuit 820 includes inverters 821 and 822 and a NAND gate 823. An input terminal of the inverter 821 is connected to a first output terminal of the step control circuit 300, and an output terminal is connected to a first input terminal of the NAND gate 823. An input terminal of the inverter 822 is connected to a third output terminal of the tap control circuit 300, and an output terminal is connected to a third input terminal of the NAND gate 823.

A first input terminal of the NAND gate 823 is connected to the output terminal of the inverter 821, a second input terminal is connected to a second output terminal of the step control circuit 300, and a third input A terminal is connected to the output terminal of the inverter 822 and an output terminal is connected to the second input terminal of the noah gate 830. The first input terminal of the NOR gate 830 is connected to the output terminal of the NAND gate 813 of the first logic circuit 810, and the second input terminal is connected to the output terminal of the second logic circuit 820. The output terminal is connected to the NAND gate 283 and the output terminal is connected to the SET terminal of the flip-flop 850.

The third logic circuit 840 includes an inversion circuit 841, a delay circuit 842, and a NAND gate 843. The inverting circuit 841 may include inverters IN1, IN2, connected in series between an output terminal of the NOR gate 830, a connection point of the flip-flop 850, and a first input terminal of the NOA gate 833. IN3). The delay circuit 842 includes inverters IN4, IN5, ..., connected between an output terminal of the inverter IN3 of the inverting circuit 841 and a second input terminal of the NOR gate 843. IN10, IN11). The first input terminal of the NOR gate 843 is connected to the output terminal of the inverter IN3, the second input terminal is connected to the output terminal of the inverter IN11, and the output terminal is the flip-flop ( 390 is connected to the clock terminal. The SET terminal of the flip-flop 850 is connected to the output terminal of the Noah gate 840, the clock terminal is connected to the output terminal of the Noah gate 853, and the output terminal is It is connected to the control signal input terminals of the n test circuits BSR1, BSR2, ... BSRn-1, BSRn.

5 is an operation timing diagram of the test control circuit of the present invention.

2 to 5, the tap control circuit 300 receives a test mode selection signal TMS and a test clock TCK. The test mode selection signal TMS is a signal supplied to the tap control circuit 310 of FIG. 2 in synchronization with the test clock TCK to select respective test modes. The signal BSCAN is a signal obtained by combining the command codes IR0, IR1, and IR2, and is a signal output from the first logic circuit 810 of FIG. 3. The signal PIN is a signal obtained by combining the test mode codes CD1, CD2, and CD4, and is a signal output from the second logic circuit 820 of FIG. 3. The signal SEL is a signal obtained by combining the signals BSCAN and PIN, and is a signal output from the NOR gate 830 of FIG. 3. The signal CLK is a combination of the signal SEL supplied through the inversion circuit 841 and the delay circuits 842, and is a signal output from the noah gate 383 of FIG. 3. The signal JZZ is a signal obtained by combining the signals SEL and CLK in the flip-flop 390 and is supplied to the test circuits BSR1, BSR2,... BSRn-1 and BSRn. .

Hereinafter, the operation of the J-tech circuit of the present invention will be described with reference to FIGS. 2 to 5.

Referring back to FIGS. 2 to 5, the J-TECH circuit of the present invention uses the ball pins to parallel the data D1, each of the circuits under test BSR1, BSR2, ... BSRn-1, BSRn, respectively. Input D2, ... Dn-1, Dn) at the same time to test whether the connection part is open / short. The test operation is performed independently of the normal operation of the memory cell / core 100. When the test operation starts, the test mode selection signal TMS synchronized with the test clock TCK is supplied to the step control circuit 300. The step control circuit 300 transmits the 4-bit code CD1, CD2, CD3, and CD4 corresponding to the test mode signal TMS among 16 finite codes to the command register 400 and the code. A confirmation information register 500, the bypass register 600, the selection circuit 700, and the test control circuit 800 are supplied.

The command register 400 receives a code CD3 among the four-bit codes CD1, CD2, CD3, and CD4 supplied from the test data TDI and the step control circuit 300 to correspond to a test operation. The command code IR0, IR1, IR2 of three bits among the eight finite codes are supplied to the selection circuit 700 and the test control circuit 800. The first logic circuit 810 of the test control circuit 800 of FIG. 3 combines the command codes IR0, IR1, IR2 supplied from the command register 400 to output the signal BSCAN. . The logic expression of the first logic circuit 810 is expressed as BSCAN = IR2 * IR1 + IR0. The second logic circuit 820 of the test control circuit 800 of FIG. 3 combines the test mode codes CD1, CD2, and CD4 supplied from the step control circuit 300 to convert the signal PIN. Output The logical expression of the second logic circuit 820 is It is expressed as

The NOR gate 830 of FIG. 3 supplies the signal SEL to the third logic circuit 840 by combining the signals BSCAN and PIN. The signal BSCAN is a signal indicating the start of the pin test operation. The signal PIN is a signal indicating the detection and shift operation of the pin data D of the test target circuits BSR1, BSR2,..., BSRn-1, and BSRn. When the voltage of the signal BSCAN is at a low level, the NOR gate 830 outputs the signal SEL having a logic low regardless of the voltage level of the signal PIN. If the voltage of the signal BSCAN is at a high level, the voltage level of the signal SEL is determined according to the voltage level of the signal PIN.

The inversion circuit 841 of the third logic circuit 840 of FIG. 3 inverts the signal SEL and supplies it to the delay circuit 842. The delay circuit 842 delays the inverted signal SEL and supplies it to the NOR gate 843. The NOR gate 843 outputs the signal CLK to the flip-flop 850 by combining the inverted signal SEL and the inverted and delayed signal SEL. The flip-flop 850 outputs the signal CLK when the signal SEL is logic high (when the signals BSCAN and PIN are logic low).

That is, during normal operation of the memory cell other than the test operation, the flip-flop 850 outputs a high level signal JZZ, and the low level signal JZZ during the test operation. ) The MOS transistors PM0 and NM0 of the test target circuit BSRn−1 of FIG. 4 receive the signal JZZ of the flip-flop 850. Thus, when the memory cell / core 100 other than the test operation is operated, the test target circuits BSR1, BSR2, ... BSRn-1, BSRn are controlled by the control of the signal JZZ at a high level. The current paths of the PMOS transistors PM0 of NF are blocked, and the current paths of the NMOS transistor NM0 are conducted. In the test operation, the current paths of the PMOS transistors PM0 are conducted by the control of the signal JZZ at a low level, and the current paths of the NMOS transistors NM0 are blocked. As a result, it is possible to reduce current consumption generated in the test target circuits BSR1, BSR2,...

6 is a waveform diagram showing current consumption of the J-Tech circuit of the related art and the present invention.

Referring to FIG. 6, during normal operation of the memory cell / core 100 other than the test operation, the current consumption (solid line) of the J-TECH circuit of the present invention and the current consumption (dashed line) of the conventional J-TECH circuit differ by ΔI. see. In general, in the case of a 128K x 36 memory, 70 test circuits BSR1, BSR2, ... BSR69, and BSR70 are provided. In this case, the J-TECH circuit of the present invention can reduce the current consumed during the operation other than the test operation by 70 × ΔI.

As described above, by interrupting the current path of the circuit under test during normal operation other than the test operation, current consumption occurring during the normal operation can be reduced.

1 is a block diagram of a semiconductor memory device having a conventional J-Tech circuit;

2 is a block diagram of a J-Tech circuit of the present invention;

3 is a detailed circuit diagram of a test control circuit provided in the J-Tech circuit of the present invention;

4 is a block diagram of a circuit under test included in the J-Tech circuit of the present invention;

5 is an operation timing diagram of a J-Tech circuit according to the present invention; And

6 is a waveform diagram showing current consumption of J-Tec circuits according to the related art and the present invention.

* Explanation of symbols on the main parts of the drawings

100: memory device 200: circuit under test

300: step control circuit 400: command register

500: confirmation information register 600: bypass register

700: selection circuit 800: test control circuit

Claims (10)

A semiconductor memory device having a plurality of ball pins as an input / output device, comprising: A step control circuit for outputting a test mode code corresponding to the selected test mode in response to a test mode selection signal synchronized with the test clock; Command storage circuitry for receiving test data and storing the command code corresponding to the test data in response to the test mode code; A test control circuit outputting a control signal informing of the start of a test operation in response to the test mode code and the command code; A plurality of test target circuits for storing pin data supplied through corresponding ball pins in response to the control signal and for shifting the stored pin data in response to the test clock; Each test target circuit, A comparator having an output terminal, comparing a voltage level of corresponding pin data with a reference voltage in response to the control signal and outputting a comparison signal through the output terminal as a comparison result; An inverter for inverting the comparison signal; A register to store an output of the inverter synchronized with the test clock; And a switch connected to an output terminal of the comparator and discharging the output terminal in response to the control signal. The method of claim 1, The test control circuit, A first logic circuit for combining the command codes to output a first combined signal; A second logic circuit for combining the test mode codes to output a second combined signal; A third logic circuit for combining the first and second combined signals to output a third combined signal; A fourth logic circuit for combining the third combined signal to output a fourth combined signal; And a flip-flop for storing the fourth combined signal as the control signal in response to the third combined signal. The method of claim 1, The switch circuit, And an NMOS transistor having a current path formed between the comparison circuit and a ground power source and a gate controlled by the control signal. The method of claim 1, The register is, And a shift register for shifting the output of the inverter stored in response to the test clock. The method of claim 2, The command code consists of 3 bits, The first logic circuit, A first NAND gate which combines and outputs the lower two bits of the command code; An inverter for inverting and outputting the highest 1 bit of the command code; And a second NAND gate configured to combine the output signals of the first NAND gate and the inverter to output the first combined signal. The method of claim 2, The test code consists of 4 bits, The second logic circuit, A first inverter for inverting the lowest 1 bit of the test mode code; A second inverter for inverting the highest 1 bit of the test mode code; And a NAND gate configured to combine the lower second bit of the test mode code and output signals of the first and second inverters to output the second combined signal. The method of claim 2, The third logic circuit, And a NOR gate configured to combine the first and second combined signals to output a third combined signal. The method of claim 2, The fourth logic circuit, A first delay circuit for inverting and outputting the third combined signal; A second delay circuit for delaying and outputting the inverted third combined signal; And a NOR gate configured to combine the output signals of the first delay circuit and the second delay circuit to output the fourth combined signal. The method of claim 7, wherein And the first delay circuit comprises an odd number of inverters connected in series. The method of claim 7, wherein And the second delay circuit comprises an even number of inverters connected in series.