KR100511684B1 - The pseudo random number generator - Google Patents

Abstract

The present invention relates to a pseudo-random number generator, which receives a variable-sized key as an input and is designed to generate different pseudo-random numbers according to the size of the input key.

According to the present invention, a key management means for storing and processing a key (Key) input from the outside; S box management means for storing and processing the S box used in RC4; S box access address generating means for reading data of the S box and generating an address for writing data to the S box; Pseudo random number address generating means for storing data read from the S box and generating pseudo random number addresses; By presenting a control means for generating a signal for controlling the configuration means to present a pseudo-random number generator characterized in that to perform a RC4 pseudo-random number generation by receiving a variable key.

Therefore, the present invention can be applied to a pseudo random number generator of WEP, which is a cryptographic security system of WLAN (IEEE 802.11), which has different sizes of keys and generates different pseudo random numbers.

Description

Pseudo random number generator

The present invention relates to a pseudo-random number generator, which receives a variable-sized key as an input and is designed to generate different pseudo-random numbers according to the size of the input key.

The pseudo-random number generator for the Web (Wired Equivalent Privacy (WEP)), which is a wireless LAN (IEEE 802.11) security system, uses the existing stream cipher algorithm RC4. The RC4 has a structure in which random numbers are generated through three stages: 1) initializing an internal array, 2) changing an S box array state, and 3) generating a pseudo random number.

Each time a new key is entered, steps 1) and 2) must be performed. Similarly, random numbers for the input key can be obtained by repeating steps 3) only once through steps 1) and 2). The pseudo code for each step is shown below.

1) internal array initialization

for i = 0 to 255

Si = i

Ki = KEY (i mod key_length)

end for

2) S box array status change

j = 0

for i = 0 to 255

j = (j + Si + Ki) mod 256

swap Si and Sj

end for

3) pseudo random number generation

i = j = 0

while (as many pseudorandom numbers as desired)

i = (i +1) mod 256

j = (j + Si) mod 256

swap Si and Sj

t = (Si + Sj) mod 256

PRN = St

end while

Figure 1 shows "A CPLD-based RC-4 Cracking System", Paul D. Kundarewich, Steven J.E. Wilton, Alan J. Ju, 1999] is a hardware implementation of RC4 with a 32-bit key.

As shown in FIG. 1, the memory used for the key memory 110 and the S box memory 120 is a memory in which the data bus is 8 bits (4 * 8 bit, 256 * 8 bit), respectively, and the input signal is a key. KEY_ADDR indicating an input KEY, an address for reading and writing a key memory, i, a data to be stored in the S box memory 120 and a value used as an address in a read request, and an output signal is an 8-bit pseudorandom PRN.

In addition, adders 1, 2 (130, 140), a multiplexer, a j register, a Si register, an Sj register, and the like are provided. RC4 processing of this structure is performed as follows.

1) internal array initialization

(1) The key to be used is stored in the key memory 110.

(2) The value corresponding to each address is stored in the S box memory 120 from address 0 to address 255. That is, 0 is stored at 0, 1 is stored at 1, and 255 is stored at 255 in this order.

2) S box array status change

(1) The j register is initialized to zero.

(2) A read request is made to the key memory 110 using the externally input KEY_ADDR as an address to obtain a part of the key, and its value is referred to as Ki, and the S box memory 120 using the externally input i as the address. The data obtained by reading from is called Si. The Si is stored in a Si register.

(3) The value stored in the j register and the Si and Ki values obtained in the step (2) are added together using the adder 1 (130), and the value is stored in the j register and j is used as the address of the S box memory (120). In S), the value obtained by reading request is called Sj and stored in Sj register.

(4) The values stored in the Si register are written to the S box memory 120 using j as the address, and the values stored in the Sj register are written to the S box memory 120 using i as the address and exchanged with each other. Be sure to

(5) Repeat the above steps (2) to (4) until i input from the outside increases from 0 to 255.

3) pseudo random number generation

(1) The j register is initialized to zero.

(2) The data obtained by reading request from the S box memory 120 using i input from the outside as an address is called Si, and this value is stored in the Si register.

(3) The value stored in the j register and Si added using the adder 1 (130) is called j, and the value is stored in the j register and obtained by reading a request to the S box memory 120 using j as an address. The data is called Sj and stored in the Sj register.

(4) The values stored in the Si register are written to the S box memory 120 using j as the address, and the values stored in the Sj register are written to the S box memory 120 using i as the address and exchanged with each other. Be sure to

(5) The value obtained by reading the S-box memory 120 from the value stored in the Si register and the Sj register by using the adder 2 (140) as an address is a pseudo-random number.

(6) Repeat the process of (2) ~ (5) as many as the similar random number that you want to generate.

As described above, in the structure of FIG. 1, only a fixed size key may be received as an input, and only pseudo random numbers for the key may be generated. There is a problem in that it cannot be used for a pseudo random number generator of WEP of a wireless LAN (IEEE 802.11), which is a security system using RC4 that requires a variable key size.

In addition, the RC4 structure of FIG. 1 uses a memory to store a key memory and an S box memory. Using memory consumes a large amount of clock to initialize. Since 256 clocks are consumed to initialize the internal array of step 1, there is a problem that a large delay time occurs in initializing the S box. In addition, when the Si and Sj values are exchanged in step 2) and 3), memory writing cannot be performed simultaneously, resulting in a delay of 2 clocks.

In addition, in the structure of FIG. 1, since the address for accessing the S-box memory is input from the outside, it is complicated to control from the outside, and in the case of key memory access, since the key and the key memory address must be input from the outside, The disadvantage is that the logic is complicated.

Accordingly, the present invention is to solve the above problems, an object of the present invention is to provide a pseudo-random number generator that receives a variable size of the key as input and generates different pseudo-random numbers according to the size of the input key. have.

In addition, another object of the present invention is to provide a pseudo random number generator that can be processed at a high speed by reducing the internal array initialization time and pseudo random number generation time by using a register instead of a memory to reduce the internal array initialization time and pseudo random number generation time .

As a technical idea for achieving the above object of the present invention, the present invention is a 256-bit signal to receive a variable key having a different size of data to be used in RC4 from the outside to store and manage in a key register Key management means for; S box management means for storing and managing the data of the S box to be used in the RC4; S box for reading the data of the S box, and generates an S box access address for writing data to the S box Box access address generating means; pseudo random number address generating means for storing data read from the S box and generating a pseudo random number address; And

It provides a pseudo-random number generator including a control unit for generating a signal for controlling the input and output of the key register and the data of the respective configuration means.

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Hereinafter, with reference to the accompanying drawings, the configuration and operation of the embodiment of the present invention will be described in detail.

According to the present invention, keys of 64, 128, 152, and 256 bits can be input, and pseudo-random numbers corresponding to the keys can be generated.

2 is a block diagram of a pseudo-random number generator according to the present invention. 2 is largely divided into a key manager 210, a controller 220, an S box manager 230, an S box access address generator 240, and a pseudo-random address generator 250.

The key management unit 210 serves to store and manage externally input keys and perform necessary processing, and the S box management unit 230 stores and processes S boxes used in RC4.

The S box access address generation unit 240 reads data of the S box and generates an address for writing data to the S box, and the pseudo-random address generation unit 250 stores data read from the S box. The controller 220 may generate a pseudo random number address and generate a signal for controlling other components.

First, KEY, which is an input signal, is a 256-bit signal and a key to be used in RC4. KEY_SEL is a 2-bit signal that selects how many bits of a key enter an input. 00 is 64 bits, 01 is 128 bits, 10 is 152 bits, 11 is 256 bits. The PRN, which is an output signal, is a pseudo random number generated with 8 bits.

At this time, RC4 processing is performed by the flowchart as shown in FIG.

When the key is input from the outside is stored in the key register of the key management unit 210 (S301),

In the S box register file of the S box management unit 230, an initialization value is selected by an internal multiplexer, and the initialization value is stored in each internal register (S302).

Initialize the j register of the S box access address generator 240 to 0 (S303),

The control unit 220 generates a control signal for selecting a part of the key and an address (key_mux_sel, i) for reading data from the S box management unit 230 (S304). (One)

Request the read from the S box management unit 230 with i as an address to obtain data (Si), store it in the Si register of the pseudo-random address generation unit 250 (S305),

The value j_out stored in the j register of the S box access address generator 240, Si, and key_out, which are outputs of the key manager 210, are all added using the adder of the S box access address generator 240 (j) ( S306),

While storing j in the j register and making a read request to the S box management unit 230 with j as an address, the value is obtained (Sj) and stored in the Sj register (S307),

Si and Sj are stored in the S box management unit 230 with j and i as addresses (S308),. (2)

The process of steps (1) to (2) is repeated until the i generated by the controller 220 increases from 0 to 255 until it becomes 255 (S309),

The j register of the S box access address generator 240 is initialized to 0 (S310),

The control unit 220 generates an address for reading data from the S box management unit 230 (i) (S311),. (3)

Request the read to the S box management unit 230 with i as an address to obtain data (Si) and store it in the Si register of the pseudo-random address generation unit 250 (S312),

The value (j_out) stored in the j register of the S box access address generator 240 is added to Si using the adder of the S box access address generator 240 (j) (S313),

In addition to storing j in the j register and making a read request to the S box management unit 230 using j as an address to obtain a value (Sj) and storing it in the Sj register (S314),

Si, Sj are stored in the S box management unit 230 with j and i as addresses (S315),

Si and Sj are added using the adder of the pseudorandom address generator 250 (t) (S316),

A request is made to the S box management unit 230 for reading, with t as the address (PRN) (S317),... (4) Here, the obtained value is a pseudorandom number.

The process of (3) to (4) is repeated as many as the number of similar random numbers to be generated (S318).

The key manager 210 illustrated in FIG. 2 is configured as shown in FIG. 4.

The key register 211 shown in FIG. 4 may receive a maximum of 256 bits as a 256 bit register. Because the register is 256 bits in size, it can store 64-bit keys, 128-bit keys, 152-bit keys, and 256-bit keys. For example, if a 64-bit key is input, only 64 bits of the key register are stored. When using a memory, data must be input several times by 8 bits when inputting a key from an external source. However, when using a register, input the desired size of a key at a time.

The key multiplexer 212 is a part that outputs a necessary part of the entire key in the RC4 execution process. The key stored in the key register 211 is divided into 32 8-bit signals (k0 to k31) to select the required portion of the key, respectively. Depending on the size of the variable key, the signal used is different because the part of the actual key data is different depending on the variable key. For example, for 64-bit keys, only the signals from k0 to k7 There is key data, and there is no key data in k8 to k31. Similarly, for 128-bit keys, only the signals k0 through k15 contain the actual key data, and k16 through k31 have no key data; for 152 bits, the signals from k0 through k18 have the actual key data, and k19 through k31 have the key data. There is no. For 256 bits, all signals from k0 to k31 have key data. Therefore, the key multiplexer 212 selects and outputs a required signal from among signals having actual key data controlled according to the input variable key size. At this time, a signal without key data (depending on the variable key as described above) is not selected at all. The key_mux_sel, which is a control signal for selecting a key, is generated and input by an external controller 220. Since the key register 211 and the key multiplexer 212 can process 64, 128, 152, and 256 bits, they are variable. It is possible to generate different RC4 pseudorandom numbers for the in-key so that it can be integrated in one circuit.

The multiplexer 213 is a portion for selecting and outputting a predetermined portion of the key and 0. In the process that does not require the partial key in the RC4 execution process, it selects and prints 0, and in the process requiring the partial key, it outputs a certain portion of the key.

The output key_out is input to the S box address generator 240.

S box management unit 230 shown in Figure 2 is configured as shown in FIG.

This structure has two write ports and one read port. There are 256 8-bit registers (231-0… 231-255) for storing S-box data, and a multiplexer (232-0… 232-255) with three inputs is arranged at the input of each register to Input data and initialization data can be selected, the combination circuit 233 for controlling the signal from the outside to output the desired signal from the inside and the output multiplexer 234 for outputting one from 256 registers, the external The address selection multiplexer 235 for selecting from among multiple S-box read addresses input from and an address register 236 for temporarily storing the read address.

The 256 registers 231-0 ... 231-255 are selectively input to each of the three data through the multiplexer 232-0 ... 232-255. At this time, the combination circuit 233 mux_sel0, mux1_sel,... Which are the selection signals of the multiplexer. It generates mux255_sel and prints out the desired data. In the internal memory initialization, each register has a constant value from 0 to 255 as an input of the multiplexer (232-0… 232-255) to receive a constant value according to the register number.

That is, when the internal array is initialized, multiplexer 0 (232-0) outputs 0 as an output, 0 is stored in register 0 (231-0), and multiplexer 1 (232-1) outputs 1 as an output and register 1 1 is stored in (231-1), and is stored in this manner so that multiplexer 255 (232-255) outputs 255 as an output so that 255 is stored in register 255 (231-255). Therefore, when the S box is implemented using memory, 256 clocks are consumed when initializing the internal array. However, in the case of FIG. 5, the internal array initialization is performed with one clock.

In order to store Si and Sj output from the pseudo-random address generation unit 250 in the S box, only registers in which data is to be stored must be enabled, so the i and S box access addresses output from the controller 220 are stored. Reg j_en, reg2_en,... Output by controlling the j output from the generation unit 240 by the combination circuit 233. The reg_255_en signal is input to each register to enable or disable each register.

When an external read request is made, one of the i output from the controller 220, the j output from the S box access address generator 240, the j_out output from the pseudorandom address generator 250, and the t is selected from the address selection multiplexer. In step 235, the output value is temporarily stored in the address register 236, and the value output from the address register 236 is input as the selected value of the output multiplexer 234 to output the output value to the outside (s_out). )

The output s_out is input to the pseudo random number generator 250 and the S box access address generator 240, respectively.

S box access address generator 240 shown in Figure 2 is configured as shown in FIG.

It consists of an adder 241 and a register 242. The adder 241 adds all three data input (j_out output from the j register, key_out output from the key management unit 210, and s_out output from the S box management unit 230) to be output to the outside (j). At the same time, it is stored in the j register and outputs the value of the stored j register to the outside.

The output signal j is input to the S box management unit 230 and j_out is input to the S box access address generator 240 again.

The pseudo-random address generator 250 shown in FIG. 2 is configured as shown in FIG. 7.

It consists of two Si and Sj registers 251 and 252 and an adder 253, and stores the s_out output from the S box management unit 230 in the Si or Sj registers 251 and 252. The data input from the outside is not stored in Si and Sj at the same time, but is stored in the necessary register among two registers, and the values stored in the Si and Sj registers 251 and 252 are output to the outside.

The adder 253 adds the values of the Si and Sj registers 251 and 252 to output to the outside t. The value obtained by adding the values of the Si and Sj registers 251 and 252 is an address in which the pseudo-random number of the S box management unit 230 is stored.

The output Si, Sj, t are all input to the S box management unit 230.

According to the pseudo-random number generator according to the present invention as described above has the following effects.

First, compared to the conventional method of generating a pseudo random number by inputting a fixed key, the proposed method generates pseudo random numbers by receiving a variable key of 64, 128, 152, and 256 bits as input. The hardware area is reduced to 1/4 because the circuit is shared without the need to implement separate RC4 circuits, and according to the WLAN (IEEE 802.11), an area that generates different pseudo-random numbers with different sizes of keys. It is suitable for use in the pseudo random number generator of WEP.

Second, the time required to initialize the internal array using registers in the S box was reduced to 1/256 compared to the case of using memory by using only one clock, and using memory that provided only one write port by providing two write ports. Compared to the conventional method, two data can be written at the same time, which is suitable for high-speed RC4 pseudo random number generation.

Third, in the conventional method, an address for S box access has to be input from the outside, but in the present invention, an external logic can be simplified by generating an address for S box access from the inside.

1 is a block diagram of a RC4 having a 32-bit key according to the prior art.

2 is an overall block diagram of a pseudo-random number generator according to the present invention.

3 is a flowchart showing in detail the RC4 processing of the pseudo-random number generator according to the present invention.

FIG. 4 is a detailed configuration diagram of the key manager shown in FIG. 2.

5 is a detailed configuration diagram of the S box management unit shown in FIG. 2.

6 is a detailed block diagram of the S box access address generator shown in FIG. 2.

FIG. 7 is a detailed configuration diagram of the pseudo-random number address generator shown in FIG. 2.

Claims (9)

Key management means for receiving a variable key having a different size of data to be used in RC4 from a 256 bit signal from outside and storing and managing the same in a key register; S box management means for storing and managing the data of the S box used in the RC4; S box access address generating means for reading data of the S box and generating an S box access address for writing data to the S box; Pseudo-random address generation means for storing data read from the S box and generating pseudo random number addresses; And A pseudo random number generator including control means for generating a signal for controlling input and output of key registers and data of each of the components. delete The pseudo-random number generator of claim 1, wherein the pseudo-random number generation can be extended even for combinations of multiples of 8 bits. The pseudo random number generator of claim 1, wherein the control means generates an address for accessing the S box. The method according to claim 1, wherein the key management means A key register for managing and storing an externally input key; A key multiplexer for selecting a portion of the key; And And a multiplexer for selecting and outputting a portion of the key and zero. The method of claim 1, wherein the S box management means N registers for storing S box data; N multiplexers for selecting data as inputs to each register; An address selection multiplexer for selecting an externally input S box reading address; An address register for temporarily storing the read address; An output multiplexer for outputting any one of the outputs of each register to the outside; And a combination circuit for controlling an externally input address to generate control signals of N registers and N multiplexers. The pseudo-random number generator of claim 6, wherein the N multiplexer includes three input terminals to select data inputted from outside of each register and initialization data. The pseudo random number generator of claim 1, wherein the S box access address generating means further obtains an adder and a register to read S box data and generate an address for writing data to the S box. The pseudo-random number generator according to claim 1, wherein the pseudo-random address generation means further comprises an adder and two registers for storing data read from the S box and generating a pseudo-random address.