KR100508585B1 - Packet transmission / reception method of all electronic switch I / O interface circuit pack - Google Patents

Abstract

The present invention relates to a method for transmitting and receiving a packet of an input / output interface circuit pack (IOPA) in a full-electronic exchange input / output control system block (HMPH block). The present invention is a method for changing the transmission / reception structure of an input / output interface circuit pack of an electronic switch to a simpler and less error-free structure, and a packet transmission / reception structure between a concurrent real time operation system (CROS) and IOPA. In a complex linked list structure in which a node array of a conventional linear list does not coincide with a address and the storage space is independent, the transmission / reception packet pointer is stored using an array, which is the simplest data structure that lists one or more data elements of the present invention. By using queues to simplify the work of electronic switchboards This improves the performance and solves the problem of assigning error pointers due to the complex structure that was the biggest problem in the linked list structure.

Description

Packet transmission / reception method of all electronic switch I / O interface circuit pack

The present invention relates to a packet transmission / reception method of an input / output interface circuit assembly (IOPA) in a full-electronic exchange input / output control system block (HMPH block). In particular, the method of transmitting and receiving packets by a linked list structure between a concurrent real-time operation system (CROS) and IOPA using a simpler static structure, Array, is used to transmit and receive packets. It is about how to.

In general, 512 Kbytes of static RAM is used as the local memory of IOPA, and 128 Kbytes of static RAM is used for the shared memory.

Through this shared memory, CROSs and packets are transmitted / received. The input data is processed through an external device connected to IOPA, and the result of the input data is the external device connected to IOPA. The process is as follows.

When data is input from an external device such as a PC or CRT, this data is stored in the Rx queue of IOPA F / W (Firm Ware), which is because Rx request from CROS is always waiting. Messages are written by CROS as they are delivered to the Rx queue, and the data is saved in the shared memory of IOPA through CROS, and the result data is output to the external device by generating an interrupt from the CROS terminal to IOPA side. Do it.

Conventionally, the packet transmission / reception scheme between IOPA and CROS has a linked list structure.

The linked list consists of a pointer to a packet and a next pointer to a list to be linked next, and dynamic memory management such as allocating if necessary and releasing if not necessary. Refers to a possible data structure.

1 shows a packet transmission and reception structure in a conventional connection list structure.

As shown in this figure, it serves to receive command packets and to receive status pointers and the first pointer (1) output from the pointer pool allocated to shared memory of CROS and IOPA. Command packet processing step (8) for processing the command list transmitted from the CROS side and the connection list (4, 6, 10, 12) consisting of the second pointer (2) outputted from the packet pointer and the next pointer If there is no command packet to transmit, the first connection list 3 is filled with an odd address in place of the next pointer, and null is filled in place of the packet pointer. It is composed of a second connection list (9) that operates in the same way.

The process of packet transmission and reception between CROS and IOPA characterized by the above configuration is as follows.

When external data is input from the input / output device, CROS takes two pointers out of the 100 connection list pointers available in the pointer pool of the shared memory, that is, the first pointer 1 and the second pointer 2 and transfers them to the IOPA side. It also uses the first pointer 1 as a start pointer.

The first pointer 1 is for receiving an instruction packet from the CROS at the IOPA side, and the second pointer 2 is used for sending a status packet to the CROS after processing at the IOPA. It is used as a path for constructing and connecting packets for the first time.

As a result, a path of the command packet to be processed received from CROS and a path to insert a status packet composed of the packet processing result of the IOPA side are established between CROS and IOPA.

Then, the command packets 5 and 7 to be transmitted from the CROS side to the IOPA side are connected to the packet pointers 4 and 6 of the connection list, respectively.

Since it is a linked list structure, the command pointer is transmitted by connecting NEXT pointer to the packet pointer of the next connection list, and if there is no command packet to transmit any more, it sets an odd address in place of the next pointer so that there is no command packet to transmit anymore. Display.

Then, an interrupt to process the packet is output from the CROS side to the IOPA side, and the packet pointer of the connection list is continuously updated until the next pointer is an odd address by the packet processing 8 of the IOPA side which inputs the interrupt. Is stored in the local memory of IOPA, and when the next pointer becomes an odd address, the packet is accessed and the IOPA outputs the data stored in the local memory to the external device or receives input from the external device.

The processed instruction packet on the IOPA side becomes a status packet containing the result again and is connected to the second pointer 2 received at the time of initialization.

Since the number of command packets processed by the IOPA side is two, two status packets containing the result are also connected to the connected list in succession.

As in the process of sending the command packet, if there is no status packet to be sent to CROS from the IOPA side, an odd address is set at the next pointer to indicate that there is no status packet to be sent anymore.

After that, IOPA interrupts CROS.

Then, CROS can obtain the status packet delivered by IOPA through the second pointer 2 stored at the time of initialization.

CROS also reads the status packet, processes it, and puts it back into the pointer pool in shared memory so that it can be used next time.

Therefore, the first pointer 1 and the second pointer 2 are pointers used for the first packet transmission and reception after IOPA initialization, and memory use is dynamically performed thereafter.

FIG. 2 is a flowchart showing the operation of the packet processing 8 of FIG.

As shown therein, determining whether the next pointer of the connection list is an odd address (ST 1); If the next pointer is not an odd address, storing a packet pointer in a local memory (ST 2); Continuously updating the next pointer to the next connection list pointer (ST 3); When the next pointer of the connection list is an odd address, a step of accessing the command packet to output data to the external device or accepting data input from the external device (ST 4).

However, when the linked list structure is used to transmit and receive a packet as described above, a single staggered pointer not only significantly affects the entire program due to the complicated structure that is connected to each other in a non-contiguous space, but also recovers the CROS. The ability wasn't implemented either, so it was a problem.

On the IOPA side, the service routine for interrupts received from CROS stores the points of the connection list described above in local memory and updates them with next pointers. Since the interrupts are at level 4, they are at level 4 or higher. Can affect the pointer value of the connection list, and in addition, if the problem is caused by a problem that can occur in a multi-tasking environment, a serious situation occurs where the entire port is down. Could be

In addition, in case of a problem related to the linked list pointer, the error pointer is not implemented at the CROS stage, and thus, once the misaligned pointer is not recovered, the entire external device may be brought down. There was a problem.

Accordingly, the present invention has been proposed to solve the above-mentioned conventional problems, and an object of the present invention is to provide a concurrent real time operation system (CROS) and an input / output interface board assembly (IOPA). IOPA that can be generated due to the dynamic linked list structure by sending and receiving packets using a simpler static structure, Arrival, which is a method of sending and receiving packets by a linked list structure It provides a way to implement more stable IOPA firmware by reducing errors and improving speed performance.

In order to achieve the above object, the packet transmission / reception method of the electronic switching device I / O interface circuit pack according to the present invention includes a packet transmission / reception structure between CROS and IOPA in a linked list structure such as front, rear, count, flag, and the like. A first circular queue for storing instruction packet pointers and a second circular queue for storing status packet pointers are provided using an array structure controlled by variables, and the instruction packet is accessed according to the state of the flag. It consists of command packet processing steps for processing such as access) or storing in local memory.

Hereinafter, an embodiment according to the technical concept of the packet transmission and reception method of the present invention, all electronic switch I / O interface circuit pack (IOPA) configured as described above are as follows.

3 shows a packet transmission / reception structure between a CROS (parallel real time operating system) and an IOPA using an array structure according to the present invention.

As shown therein, a command packet constructing unit 10 constituting a command packet at a CROS (parallel real time operating system) side when inputting data from an external device; A first circular queue 20 in which a space for placing a packet pointer to be processed from CROS is arranged in shared memory and allocated as 100; A packet processing unit 30 on the IOPA side for processing the command packet of the first circular first queue 20; The command packet processed by the packet processing unit 30 becomes a status packet, and the second circular queue 40 has been allocated to 100 by arranging a space for the packet pointer to process the status packet in an array; It consists of a status packet receiver 50 which receives an interrupt output from the IOPA (input / output interface circuit pack) side and processes a status packet at the CROS side.

The first circular cue 10 and the second circular cue 40 are controlled by variables such as rear (front), front (front), count, flag, and the like. Points to the structure to reuse the allocated space.

Looking at the variables used in the circular queue, the rear is used to put the packet pointer in the queue, the front is used to take out the packet pointer in the queue.

Count is incremented by one each time a packet pointer is put on the queue, and decrements by one after it is processed, indicating the number of packets to be processed and used as a variable to prevent overflow or underflow.

The flag is assigned for each packet pointer of each circular queue, so the USED is inserted in the case of a packet to be processed and FREE in the case of a processed packet.

4 is a flowchart illustrating an operation of the packet processing unit 30 of FIG. 3.

As shown in the figure, checking whether the flag of the circular queue is FREE (ST 10); if the flag is not FREE, storing the packet pointer in the local memory using the front (ST 20); A variable manipulation step (ST 30) for manipulating variables such as making the flag FREE and filling the packet pointer with NULL, decreasing the count, increasing the front, and the like; When the flag is FREE in the step (ST 10) of checking whether the flag is FREE, an input / output step (ST 40) for accessing a packet to output data to an external device or accepting a data input from the external device is configured.

Referring to Figures 3 and 4 attached to the operation of the packet transmission and reception method of the electronic switchboard input and output interface circuit pack according to the present invention configured as described above are as follows.

First, CROS (parallel real-time operating system), if there is a command packet to be transmitted to the IOPA (input and output interface circuit pack) side, after configuring the command packet in the command packet configuration unit 10, the packet pointer of the first circular queue 20 Insert the start address where the instruction packet is located at the position and manipulate the variable as follows (first variable operation step).

To access the packet pointer that can accept the current command packet, increase rear by 1, and set the variable flag to USED because it is a packet to be processed, and increase the count to 1 to indicate that one packet has to be processed.

As described above, the command packet is placed in the packet pointer position of the first circular queue 20, and after the first variable manipulation step as described above, CROS sends an interrupt requesting packet processing to IOPA.

Then, the IOPA firmware receives an interrupt from CROS, and as shown in the flowchart of FIG. 4, when the variable flag of the first circular queue is FREE, the packet is accessed to output data to an external device or to accept data input from an external device. (ST 40).

If the flag is not FREE, that is, USED, the packet pointer is stored in the local memory in the interrupt service routine (ST 20), and the variable operation is performed as follows (ST 30. Second variable operation step).

First, the flag is set to FREE to indicate that the packet pointer has been processed.

In other words, CROS becomes a space that can be used again.

In addition, since the packet is processed, it is filled with NULL (null) so that CROS can be reused.

After accessing the packet pointer to be processed, increase the front so that the next packet pointer can be accessed.

In addition, the IOPA firmware configures a status packet containing the result after the processing of the command packet as described above, and the status packet is located at the packet pointer of the second circular queue 40 in the same manner as the processing of the command packet. Insert the start address and manipulate the variable as follows (3rd variable operation step).

Indicates that this is a packet pointer area used to increase rear by 1 and to set the flag to USED to access the packet pointer that can receive the current status packet.

It also increments count by one, indicating that one packet has to be processed.

When the status packet is placed in the packet pointer as described above and these variables are manipulated, IOPA issues an interrupt requesting packet processing to CROS.

Then, CROS receives the interrupt from the IOPA firmware, accesses the packet pointer in the interrupt service routine, performs the corresponding processing, and manipulates the variable as follows (fourth variable manipulation step).

First, the flag is set to FREE to indicate that it is a used packet pointer.

That is, it becomes a reusable area in CROS.

In addition, since the packet is processed, it is filled with NULL so that CROS can be reused. Since the packet is processed, the count is decreased by one.

After accessing the packet pointer to be processed, increase the front so that the next packet pointer can be accessed.

This enables IOPA to process the command packet configured by CROS after inputting data, to input / output the corresponding message, and to transmit the configured status packet to CROS.

As described above, the packet transmission / reception method of the electronic switching device input / output interface circuit pack according to the present invention implements a simple arrangement structure when transmitting / receiving packets between a CROS (parallel real time operating system) and an IOPA (input / output interface circuit pack). Simpler structure than linked list improves speed performance and facilitates handling in software by using simple structured array. Also, interrupt service routine is simplified to solve the error pointer allocation problem that occurred in previous linked list structure. Will be.

FIG. 1 is a block diagram illustrating a packet transmission / reception process using a connection list structure used in a conventional all-electronic exchanger input / output interface circuit pack (IOPA).

FIG. 2 is a flow chart of instruction packet processing shown in FIG. 1;

3 is a block diagram showing a packet transmission / reception structure using an arrangement structure used in an all-electronic exchanger input / output interface circuit pack (IOPA) according to the present invention;

FIG. 4 is a flow chart for instruction packet processing shown in FIG.

<Explanation of symbols for the main parts of the drawings>

20: first circular queue 30: instruction packet processing unit

40: second round queue

Claims (2)

In the packet transmission / reception method of an I / O interface board in an I / O control system block in an electronic switch, A command packet constructing step of constructing a command packet to be transmitted from a CROS (parallel real time operating system) to an IOPA (input / output interface circuit pack); A command pointer setting step of setting the command packet at a packet pointer position of a first circular queue; After the command pointer setting step, the variable that is the rear of the first circular queue is increased by 1, the flag is set to USED, and the variable that is counted is increased by 1. A first variable manipulation step; A first interrupt output step of outputting an interrupt for requesting instruction packet processing to IOPA by CROS after the first variable manipulation step; An instruction packet processing step of processing the instruction packet at an IOPA side after the first interrupt output step; A status packet setting step of placing a status packet configured after the command packet processing step at a packet pointer position of a second circular queue; A third variable manipulation step of manipulating a variable that increases the variable rear of the second circular queue by 1, sets the flag to USED, and increases the count by 1 after the state packet setting step; A second interrupt output step of outputting an interrupter for requesting a state packet processing to the CROS (parallel real-time operating system) after the third variable manipulation step; After the second interrupt output step, the variable flag of the second circular queue is set to FREE, the packet pointer is set to NULL, the count is decreased by 1, and the front is decreased. And a fourth variable operation step of performing a variable operation of increasing one. The method of claim 1, wherein the command packet processing step, An input / output step of accessing a packet to output data to an external device or accepting a data input from an external device when the variable flag (state) of the first circular queue is FREE (end of processing); A storage step of storing a packet pointer in a local memory in an interrupt service routine when the variable flag of the first circular queue is USED; And a second variable manipulation step of setting the flag to FREE after the storing step, filling the packet pointer with NULL, decreasing the variable count by 1, and increasing the front by one. Packet transmitting / receiving method of an all-electronic switching device I / O interface circuit pack.