KR100506254B1 - Apparatus and method for handling interrupt in non-privileged of embedded system - Google Patents

Abstract

The present invention provides a method for handling interrupts in a system having an operating system that provides a different execution mode of privileged and non-privileged modes, wherein the processor processes certain interrupts in any process operating in the non-privileged mode. And registering an interrupt service routine (ISR) for performing the step, and suspending a previous process task and performing the registered interrupt service routine (ISR) when an interrupt corresponding to the interrupt service routine (ISR) occurs. It is characterized by.

Description

Apparatus and method for interrupt handling in non-privileged mode of embedded system {APPARATUS AND METHOD FOR HANDLING INTERRUPT IN NON-PRIVILEGED OF EMBEDDED SYSTEM}

The present invention relates to an apparatus and method for handling interrupts in an embedded system, and more particularly to an interrupt handling in a system having an operating system that provides different modes of execution of privileged and non-privileged modes. An apparatus and method for

Embedded systems are generally specific application systems that include hardware and software for performing specific tasks. Development of such an embedded operating system (OS) (hereinafter, referred to as 'OS') has been actively developed in recent years. The reason is that without an embedded OS, new functional requirements or high-quality creative services cannot be delivered on time. Until now, the embedded system was able to be controlled with a monitor program or a control program, which is not an OS developed by itself. However, the demand for the embedded OS is rapidly increasing because existing programs cannot provide rapid technical advances and newly generated functional requirements or creative services in the desired time with the Internet-based information society. .

Such embedded operating systems include a Windows OS, a Java OS, and the like, and a Linux OS. In the following description, the Linux OS will be described as an embodiment. The OS is a basic set of programs embedded in all computer systems, the most important of which is called a kernel. The kernel is loaded into random access memory (RAM) when the system is booted and contains various procedures necessary for the system to operate. Therefore, the OS and the kernel may be used in the same sense. The Linux OS hides details related to the physical structure of the computer from the application running by the user. So the program must ask the OS to use the hardware device. The OS makes a decision on the request and decides to allow the request to interact with the associated hardware component on behalf of the user program. In order to carry out this procedure, the OS may use a non-privileged mode for the user program and a privilege for the OS to prevent any program from directly interacting with hardware components or accessing any memory location. It offers a different execution mode called privileged mode. The non-privileged mode is also referred to as user mode and the privileged mode is also referred to as kernel mode or OS mode.

First, Privileged Mode handles critical data structures, direct hardware access (I / O or memory mapped), direct memory access (DMA), and InterRupt reQuest (IRQ). Allows the user to run the application. In general, there are two cases of switching between the modes.

1. Calling a system call: After calling a system call, the process automatically calls code in privileged mode.

2. When an IRQ occurs: After the InterRupt reQuest (IRQ) occurs, the interrupt handler is called, and when the interrupt processing is complete, the control path returns to the nonprivileged mode.

Here, the interrupt is a signal coming from a device mounted on the computer or a program in the computer that allows the OS to stop doing what it is supposed to do next. The OS recognizes the interrupt signal for any signal as follows.

1. The process called a system call.

2. The CPU that is executing the process throws an exception, which is an abnormal situation such as incorrect instruction execution. The kernel handles the exception handler on behalf of the process that caused the exception.

3. The peripheral device sends an interrupt signal to the CPU to signal an event that the state has changed, or that the I / O operation has completed. The interrupt signal is handled in a kernel program called an interrupt handler. Unlike the CPU, the peripheral device asynchronously generates an interrupt at an unexpected time.

4. Controlling Flow in the Kernel

In each of these cases, the OS detecting the interrupt signal resumes the program being executed or starts execution of another program. Here, the uniprocessor system refers to a system in which only one process occupies the CPU. Because of this, the CPU can proceed only one for each performed task. However, because of the interrupt signal, you can have an order in which other programs or statements can be executed. This is called multitasking. The multitasking allows the user to do several tasks at the same time. The OS simply manages the order in which the programs are to be executed so that the user can work effectively. Of course, the computer runs at a high speed so that all of the user's tasks appear to be performed simultaneously. In addition, the OS usually has the interrupt management function. The interrupt management device, which serves as the interrupt management function, prioritizes interrupts and stores them in a queue when one or more interrupts are to be processed. The queue refers to a data structure that is removed in the order in which data is entered. The operating system also has another small program called a scheduler, which gives control to the next program to be executed.

As described above, when an interrupt generated from a hardware resource occurs, an interrupt service routine (ISR), which is present in the privileged mode, receives and processes the interrupt. In addition, the non-privileged mode cannot execute a central processing unit (CPU) instruction that can be executed in the privileged mode. Hereinafter, a process in which an interrupt is processed in a privileged mode and a non-privileged mode will be described with reference to FIG. 1.

1 is a diagram illustrating interrupt processing in a conventional privileged mode.

Prior to the discussion, all operating systems utilize a process, which is basically an abstract concept. The process may be defined as an instance of a program in an execution state or an execution context of a running program. Therefore, since one user program may be mixed with one process, the following describes a user program and a process as a process without particular distinction.

Referring to FIG. 1, first, a process performed in a non-privileged mode in terms of software includes a first process 102 and a second process 104, and a privileged mode identifies an ISR 108 performed in the mode. Include. On the other hand, there are hardware devices 1 126, 2 110, and 3 128 that request interrupts in terms of hardware. The hardware devices may be input / output devices such as a network device, a keyboard, and a mouse.

When the first process 102 requests the operation of the hardware device 2 (110), a mode transition occurs in the privileged mode as shown in 112. The OS in the privileged mode acts for the work request for 112 and waits for the work to complete. At this time, the OS in the privileged mode generates a mode transition of 114 so that the second process 104 can be executed in order not to waste CPU resources. When the hardware device 2 104 completes the task, it generates an interrupt of the task completion signal 116 and simultaneously generates a mode transition of 118 to perform the ISR 108. The ISR 108 performs a process of notifying the first process 102 of a task completion event of the hardware device 2 110. If the second process 104 has a higher execution priority than the first process 102, the second process 104 occupies the CPU, and the first process 102 occupies the CPU. When the CPU allocation time of the two processes 104 ends, the operation is performed after the mode transitions of 122 and 124. Here, when the first process 102 has a higher priority than the second process 104, the first process 102 is performed through a mode transition of 124 when the ISR is completed.

Next, the internal CPU and the memory structure for performing the interrupt will be described with reference to FIG. 2.

2 is a diagram illustrating the structure of a CPU and a main memory device for conventional interrupt processing.

First, the CPU 200 includes an instruction reader 203 for reading CPU instructions from a memory or cache, a register 206 which is a temporary storage device of the CPU, and a general register 204 constituting the register. ), A page directory 205 used for converting a virtual address into a physical address, an arithmetic logic operator 209 for performing data operations, and instructions for temporarily storing CPU instructions. The cache 212, the controller 215 responsible for overall CPU control, and the data cache 218 area that is a temporary data storage area. Meanwhile, the main memory device 250 may be divided into several fields by programming, and ISR0 253, ISR1 256, and ISRn represent an interrupt vector. 221 is a signal indicating that an interrupt is generated from the outside, and a memory bus 224 is a path connecting the CPU and the main memory.

Here, the interrupt vector is a data structure in which the start address of the ISR is stored in an array according to the interrupt number. For example, when an interrupt 0 occurs, the CPU completes an instruction currently being executed, stores the current state in the general register 204, and performs context switching to ISR0 253 to perform ISR. In the above context switching is a series of tasks that, when a running process is replaced according to a scheduling, memorizes the state of the replaced process, restores the previous execution state of the new process, and passes it to the processor. That is, referring to FIG. 1, the context switch may be referred to as performing a task performed between a privileged mode and a non-privileged mode.

In FIG. 2, when the CPU 200 detects the occurrence of an external interrupt 221, the CPU 200 is input to an interrupt pin of the CPU and transferred to the controller 215. The controller 215 interrupts the existing work and controls the information to be stored in the general register 204. The command reader 203 then determines the interrupt request device and performs ISR in the main memory device after the context switch to the interrupt handler. When the controller 215 detects the end of interrupt execution, the controller 215 reads information about the interrupted task from the register and resumes the task. The temporary storage area is divided into a register and a cache. The cache memory is a memory inserted between the main memory 250 and the CPU 200 in the storage hierarchy, and improves the processing speed of the CPU. The cache also works by leaving the copy in cache memory in anticipation that the data in the main memory will be used once by the CPU and then used again. The instruction cache 212 and the data cache 218 may be configured as one cache without being separated according to the CPU as described above.

As described above, the embedded system and the real time system need to react quickly to external events, so rapid processing in the event of an interruption determines the overall performance of the system. In addition, since the system processes the external event processing method and the required data structure, most of the systems manage the external event rather than simply processing the external event when the ISR processes the interrupt. It is often just to pass on. In this case, the processing time is delayed than when the user process directly receives and processes the interrupt.

In addition, when the CPU detects the occurrence of an interrupt in the system that divides the privileged mode and the non-privileged mode, an ISR corresponding to the corresponding interrupt number in the interrupt vector is executed after the transition to the privileged mode. The reason for distinguishing the system into the privileged mode and the non-privileged mode is to prevent the system from collapsing due to an incorrect malfunction or execution of a user process. However, when the rapid processing of external events as described above is required, There is a problem that causes the cause.

Accordingly, an object of the present invention is to provide an apparatus and method for performing ISR in a non-privileged mode of an embedded system.

Another object of the present invention is to provide an apparatus and method for handling interrupts quickly and efficiently by performing ISR in a non-privileged mode of an embedded system.

A method of the present invention for achieving the above objects is a method for handling an interrupt in a system having an operating system that provides different modes of execution of privileged and non-privileged modes, wherein any of the operating in the non-privileged mode is performed. Registering an interrupt service routine (ISR) for processing a predetermined interrupt in a process furnace, suspending a previous process operation when an interrupt corresponding to the interrupt service routine (ISR) occurs, and registering the interrupt service routine (ISR). It is characterized in that it comprises a process to perform the).

An apparatus of the present invention for achieving the above objects is an apparatus for processing an interrupt in a system having an operating system providing different modes of execution of privileged and non-privileged modes, the interrupt for processing a predetermined interrupt A controller for registering a service routine (ISR) to suspend a previous process operation and to perform the registered interrupt service routine (ISR) when an interrupt corresponding to the interrupt service routine (ISR) occurs, according to the ISR registration request; And a main memory device for storing the ISR registration information in an interrupt vector, and an interrupt temporary memory device for temporarily storing interrupt processing information when performing the ISR.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to distract from the gist of the present invention.

Prior to the description, context switching or mode transition means when execution is switched from one process to another, and the operating system is responsible for registering register information that is needed when the context switched process is subsequently performed again. Memory usage information must be stored.

3 is a diagram illustrating interrupt processing in a processor in a non-privileged mode according to an embodiment of the present invention.

Referring to FIG. 3, the first processor 302 and the second process 304 in a central processing unit (CPU) are referred to as a non-privileged mode. The operating system (hereinafter referred to as 'OS') 308 operates in a privileged mode. Interrupt Service Routine (ISR) (hereinafter referred to as 'ISR') 306 performs an operation for processing an interrupt that occurs. In FIG. 3, the ISR requests registration with the OS in a first process. If the registration request is permitted according to the determination result of the OS, the first process performs an interrupt process. A process of requesting the ISR registration by the first process will be described in detail with reference to FIG. 5 to be described later. Next, a process of processing by the CPU when the hardware device 2 310 generates an interrupt will be described.

In FIG. 3, it is assumed that the second process has a higher priority than the first process and the first process has completed ISR registration. If the hardware device 2 310 requests an interrupt 316 while the second process is running in the non-privileged mode, the ISR 306 is executed. Here, the procedure up to execution of the ISR when the interrupt occurs will be described in detail with reference to FIG. 6 to be described later. 314 means that the second process is performed and the context switch occurs to the first process by the occurrence of an interrupt. Thereafter, when the ISR 306 completes the interrupt request of the hardware device 2 310, the process of FIG. 7 to be described later is performed to resume the operation of the second process interrupted by the interruption. 316 means that the first process completes all work and a context switch occurs to the second process.

4 is a diagram illustrating a configuration of a CPU and a main memory device to which an embodiment of the present invention is applied to perform ISR in the non-privileged mode process.

4 is a diagram illustrating the structure of a CPU and a main memory device according to an embodiment of the present invention.

Referring to FIG. 4, the CPU 400 according to the embodiment of the present invention has a new configuration in which the interrupt register file 408 and the interrupt page directory 409 are newly registered in the register 410 as compared with the conventional CPU 200. Element, the existing instruction cache area 212 was added to add a new interrupt cache 425, and the existing data cache 218 was added to add a new interrupt data cache 435. The controller 430 has modified the existing controller 215 to perform ISR in a non-privileged mode process according to an embodiment of the present invention. 6 to 7 are flowcharts illustrating a process performed by the controller 430. On the other hand, the main memory device 450 is a process identifier (PID) (hereinafter referred to as "PID") 454, a stored page directory (456) and a flag (flag) for each ISR New addition to the field.

Next, a function of the newly added region will be described.

The interrupt register file 408 temporarily stores information about a task performed while an interrupt is processed in a corresponding ISR in a register. The interrupt page directory 409 is an area where the storage page directory 456 is loaded when an interrupt occurs. Here, the page means a memory space having a predetermined length. Linear addresses within a page use physically contiguous addresses, and the kernel presents the physical address and approach only page by page. In addition, the page may mean a physically continuous space, and the data therein may also be referred to as a page. A page frame is a physical memory divided by a certain amount of RAM is assumed to have a page. The page may be on disk or may occupy a page frame of the main memory device. On the other hand, there is a page table (page table) for the purpose of managing page frames. The page table is a data structure on the main memory having a list of page frames. The page directory contains a list of page tables. That is, one entry of the page table becomes a pointer to the page table.

The interrupt cache 425 and the interrupt data cache 435 are memory areas in which instructions and data are temporarily stored while the ISR is performed, and thus, the ISR is performed to prevent the intrusion of the cache area used when a normal process is performed. In the present invention, the cache area is divided into a cache area in normal operation and a cache area in interrupt processing. The cache may be referred to as a memory, and the cache memory may be a RAM which a microprocessor may access faster than a general random access memory (RAM). When a microprocessor processes data, it first finds it in cache memory, and when it finds the data it wants, it does not have to go to main memory, which requires more time to read. The cache memory is sometimes divided into two stages depending on how close and accessible the microprocessor is. The Level-1 (L1) cache is in the same chip as the microprocessor. Level-2 (L2) caches are typically separate RAM chips. Main memory devices usually use DRAM (Dynamic RAM) chips. On the other hand, the Linux OS ignores the hardware technology and assumes one cache without separately distinguishing the L1 and L2 caches.

The PID 454 of the main memory device 450 is provided to the OS as a part of a memory for storing the process ID, and is used when the OS accesses a process-related data structure for performing ISR. The saved page directory 456 is a part of the main memory 450 that stores a page directory used by a process that performs ISR, and includes information for converting a physical address into a virtual address. The flag includes information on whether the interrupt cache 425 and the interrupt data cache 435 are used in interrupt processing. Meanwhile, the PID 454, a stored page directory, and a flag are registered as a process in FIG. 5 to be described later, and the ISR is registered in the process as an entry of an interrupt vector of the main memory 450. Included.

Here, referring to FIG. 4, a process performed when an interrupt request 445 is requested to the CPU 400 is performed. First, any process performs a normal operation, and the controller 430 requests the interrupt request from the hardware device. When receiving 445, the stored page directory 456 in the main memory 450 is loaded into the page directory 409 in the CPU 400. Thereafter, the controller 430 determines whether the cache is used, and stores the cache information in the main memory 450 when the normal process job uses the cache. Whether or not the cache is used is determined by information stored by a flag 458. In response to the interrupt request, the corresponding ISR of the interrupt vector of the main memory 450 processes the interrupt and ends. When all interrupt processing processes are completed in this way, the controller 430 again controls information to be loaded from the general register 410 to perform the normal process tasks. The interrupt vector is a table of contents embodied programmatically to store the address where the interrupt is located.

Next, as described in the case of the first process 302 of FIG. 3, a process in which an arbitrary process requests an ISR to the OS will be described.

5 is a flowchart illustrating a procedure that an OS processes upon receiving an ISR registration request from a process according to an embodiment of the present invention.

First, when the OS receives an ISR registration request from an arbitrary process in step 502, it proceeds to step 504. In step 504, the OS determines whether the process has a right to make an ISR registration request. The reason for the determination may be the authority of the process, the authority of the user, the validity of the ISR start address, and the like. In step 504, if ISR registration is possible, the process proceeds to step 506. The OS sets to not perform the interrupt processing even if an interrupt occurs, and proceeds to step 508. In step 508, the OS stores the ISR information requested by the process in an interrupt vector and proceeds to step 510. The ISR information may be a PID 454, a saved page directory 456, and a flag 458. Thereafter, when the OS receives an interrupt request from an arbitrary hardware device in step 510, the OS transitions to an ISR registered in the process to perform interrupt processing.

Next, a process of controlling the execution of the ISR when the interrupt request occurs by the controller 430 will be described with reference to FIG. 6.

6 is a flowchart illustrating a process of controlling a controller to perform ISR according to an embodiment of the present invention.

First, the controller 430 that receives the interrupt request from any hardware device in step 602 proceeds to step 604. In step 604, the controller 430 determines whether the interrupt is set to use the cache by using flag 458 information of the ISR information corresponding to the interrupt request. If the controller 430 determines that the interrupt is set to use the cache, the process proceeds to step 606. In step 606, the controller 430 stores cache information previously stored in the general cache in the main memory 450. Herein, the generic cache refers to the instruction cache 420 or the data cache 440. If the controller 430 determines that the cache is not used in step 604, the controller 430 proceeds to step 608 to load the stored page directory 456 into the interrupt page directory 409 and proceeds to step 610. In step 610, the controller 430 branches to the start address of the process registered ISR 306 to perform interrupt processing. For example, the process uses a virtual address and the main memory uses a physical address. Therefore, when the process is executed, ISR is performed by mapping a virtual address to a physical address. The page directory 409 serves to perform the address mapping.

Next, a procedure of processing an interrupt and operating in a previous execution mode will be described with reference to FIG. 7.

7 is a flowchart illustrating a process performed by a controller at the end of an ISR execution according to an embodiment of the present invention.

First, when the controller 430 detects the ISR execution termination signal in step 702, the controller 430 proceeds to step 704. In step 704, the controller 430 determines whether the cache is set as flag 458 information in the ISR information in the interrupt vector. If it is determined that the controller 430 is set to use the cache, the process proceeds to step 706. In step 706, the controller 430 stores cache information previously stored in the interrupt cache in the main memory 450. In this case, the interrupt cache refers to an interrupt cache 425 or an interrupt data cache 435. If the controller 430 determines that the cache is not used in step 704, the controller 430 proceeds to step 708 to control to perform the process work before the interrupt occurs. Afterwards, the CPU 400 uses the general register 406, the instruction cache 420, and the data cache 440 as temporary storage for all operations until the interrupt is generated again, and the virtual address / physical address translation page. Directory 407 is used.

In this case, the virtual memory is a virtual memory for increasing the address space that a program can use, and processes do not use the actual physical address to store instructions or data. Use a virtual address. It is only when the process is executed that the virtual address is converted to the actual physical address.

As described above, if any user process requests the OS and registers an ISR corresponding to the OS, the ISR can be performed even in the non-privileged mode. In this way, the ISR in the non-privileged mode can be processed immediately when an interrupt occurs, thereby reducing the time delay occurring between several mode conversions. In addition, the cost of copying memory can be reduced because the information and resources in the user process's address space can be accessed as is.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention has an advantage of reducing processing delay time by registering an ISR in a non-privileged user process so that no transition between multiple modes occurs when an interrupt occurs. In addition, by dividing the register and cache areas, which are temporary storage areas, into areas for interrupt processing and normal operation, unnecessary mode switching or context switching and register storage operations can be eliminated, thereby improving system performance. .

1 illustrates interrupt processing in a conventional privileged mode.

2 is a diagram illustrating the structure of a CPU and a main memory device for conventional interrupt processing;

3 illustrates interrupt processing in a processor in a nonprivileged mode according to an embodiment of the present invention.

4 is a diagram illustrating the structure of a CPU and a main memory device according to an embodiment of the present invention;

5 is a flowchart illustrating a procedure that an OS processes upon receiving an ISR registration request from a process according to an embodiment of the present invention.

6 is a flowchart illustrating a process of controlling a controller to perform ISR according to an embodiment of the present invention.

7 is a flowchart illustrating a process performed by a controller at the end of an ISR execution according to an embodiment of the present invention.

Claims (10)

CLAIMS What is claimed is: 1. A method for handling interrupts in a system having an operating system that provides different modes of execution, privileged and non-privileged. Registering an interrupt service routine (ISR) for processing a predetermined interrupt in any process operating in the non-privileged mode; And suspending a previous process task and performing the registered interrupt service routine (ISR) when an interrupt corresponding to the interrupt service routine (ISR) occurs. The method of claim 1, Registering an interrupt service routine (ISR); Determining whether the process permits ISR registration, and if the registration is possible, registering one or more of a process identifier (PID), a storage page directory, and a flag in the corresponding interrupt vector of the main memory device. Said method. The method of claim 1, Performing a registered ISR when an interrupt corresponding to the ISR occurs; And storing the information on the previous process operation in a general register and a cache, and then loading the registered interrupt service routine (ISR) into an interrupt register and a cache to perform the ISR. The method of claim 2, Wherein the registered ISR operates in a non-privileged mode. An apparatus for handling interrupts in a system having an operating system that provides different modes of execution, both privileged and nonprivileged. A controller that registers an interrupt service routine (ISR) for processing a predetermined interrupt so as to suspend a previous process operation and perform the registered interrupt service routine (ISR) when an interrupt corresponding to the interrupt service routine (ISR) occurs. Wow, A main memory device for storing the ISR registration information in an interrupt vector according to the ISR registration request; And an interrupt temporary memory for temporarily storing interrupt processing information when performing the ISR. The method of claim 5, The controller determines whether to allow the Interrupt Service Routine (ISR) registration of the process, and if the registration is possible, the controller identifies a process identifier (PID), a saved page directory, and a flag in the corresponding interrupt vector. flag) to be registered in the interrupt vector of the main memory device. The method of claim 5, And the temporary memory device includes at least one selected from an interrupt register and an interrupt cache. The method of claim 7, wherein And said interrupt register comprises an interrupt register file and an interrupt page directory. The method of claim 7, wherein And said interrupt cache comprises an interrupt cache and an interrupt data cache. The method of claim 5, The main memory device generates a process identifier (PID), a saved page directory, and a flag field in a corresponding interrupt service routine (ISR) when the interrupt occurs, and stores the interrupt field in an interrupt vector.