KR100505600B1 - Programmable microcontroller including a serial interface circuit and data writing/reading method thereof - Google Patents

Abstract

Disclosed are a programmable microcontroller capable of reducing the number of pins required during write and read operations, a data writing method thereof, and a data reading method thereof. The programmable microcontroller, which performs the data writing method and the data reading method, serially receives and serially receives serial data applied through an input / output pin externally in synchronization with a shift clock applied through a clock pin during a write operation. And a serial interface circuit configured to transmit the data transferred to the memory unit and parallelly transmitted from the memory unit during a read operation to the outside through the input / output pin in synchronization with the shift clock. Therefore, the programmable microcontroller includes the serial interface circuit, so that only one data input / output pin and one clock pin are required for write and read operations, thereby reducing the number of pins.

Description

Programmable microcontroller including a serial interface circuit and data writing / reading method

The present invention relates to a programmable microcontroller, and more particularly, to a programmable microcontroller having a serial interface circuit and a method of writing and reading data thereof.

Microcontrollers include Mask ROM Type microcontrollers and Programmable microcontrollers. The mask ROM type microcontroller is a ROM ROM type in which an application program is coded and embedded, and is mainly used for mass production. Programmable microcontrollers, on the other hand, use either an OTP (One Time Programmable) type EPROM, MTP (Multiple Time Programmable) type EEPROM or Flash ROM. Therefore, the use of a programmable microcontroller in the development of an application has the advantage of sufficiently verifying the code of the application. In addition, the cost of using a programmable microcontroller is slightly higher if you want to produce a small quantity of systems. The advantage is that production is possible.

In particular, in a programmable microcontroller, a parallel interface method is used in which an address and data are simultaneously applied in parallel through a plurality of pins to write an application program code to an embedded ROM. However, the programmable microcontroller using the parallel interface method requires a plurality of address pins, data pins, and control pins, so that the number of pins is increased. In addition, even if the programmable microcontrollers have the same pin count package, that is, even if the pin count is the same in the normal mode, the number of address pins, data pins, and control pins are different according to the capacity of the internal ROM in the program mode, and the pin positions are different. Program sockets are difficult to share.

Accordingly, an object of the present invention is to provide a programmable microcontroller capable of reducing the number of pins required for write and read operations.

Another object of the present invention is to provide a data writing method of a programmable microcontroller capable of reducing the number of pins required for a writing operation.

Another object of the present invention is to provide a data reading method of a programmable microcontroller capable of reducing the number of pins required during a read operation.

Programmable microcontroller according to the present invention for achieving the above technical problem, the memory unit, the central processing unit for performing the operation and control functions by reading data from the memory unit and, in particular during the write operation is applied through the input and output pins from the outside The serial data is synchronized with the shift clock applied through the clock pin to serially receive and parallelly transfer the serial data to the memory unit, and during the read operation, the data transmitted parallelly from the memory unit is synchronized with the shift clock. And a serial interface circuit for serially transmitting to the outside through an input / output pin.

The serial interface circuit includes an address field detector, a shift register, an address register section, and a write / read buffer.

The address field detector detects an address field condition from the serial data and the shift clock to generate an address flag. The shift register shifts the serial data to the right in synchronization with the shift clock to store and then outputs the parallel data. In the read operation, the shift register is moved to the right and parallel to the read data. Output to the outside. The address register section stores data output in parallel from the shift register while the address flag is activated, and outputs the data as the first address of the memory section. The write / read buffer buffers data output from the shift register in parallel when the address flag is non-active, and outputs the buffered data as write data to be written to the memory unit. The data read from the memory unit is buffered and output as the read data.

In particular, the address field detector activates the address flag when the data transitions from logic "low" to logic "high" while the shift clock is logic "high", and then M of the data which is serially input. By recognizing a byte (M is an integer) as an address field, the active state of the address flag is maintained, and then inputting N bytes (N is an integer) as a data field to non-activate the address flag. The address register section outputs the first address and then generates an address that is automatically incremented.

According to another aspect of the present invention, there is provided a data writing method of a programmable microcontroller according to an embodiment of the present invention, in which serial data applied through an input / output pin is externally synchronized in parallel with a shift clock applied through a clock pin. And writing to the memory unit.

(1) generating an address flag by detecting an address field condition from the serial data and the shift clock, and sequentially synchronizing the serial data to the first to eighth clocks of the shift clock. (2) shifting to the right to store one byte and outputting one byte in parallel in synchronization with the ninth clock; and M-byte data output in parallel by one byte while the address flag is activated. (3) storing the data as the first address of the memory unit, and sequentially storing and buffering the N-byte data output after the N-byte data while the address flag is non-active. And outputting as write data to be written (4).

The step further includes the step of automatically incrementing the address every ninth clock of the shift clock after step (3). Further, the address flag of step (1) is activated when the serial data transitions from logic "low" to logic "high" while the shift clock is logic "high" and the M in step (3). It remains active until you store bytes of data sequentially.

According to another aspect of the present invention, there is provided a data read method of a programmable microcontroller according to an embodiment of the present invention, wherein a data read parallel from a memory unit is synchronized with a shift clock applied through a clock pin to externally output through a input / output pin. Characterized in that it comprises the step of transmitting.

(1) generating an address flag by detecting an address field condition from the serial data and the shift clock, and sequentially synchronizing the serial data to the first to eighth clocks of the shift clock. (2) shifting to the right to store one byte and then outputting M bytes in parallel one byte in synchronization with the ninth clock; and M bytes output in parallel one by one while the address flag is activated. (3) storing data sequentially and outputting the data as a first address of the memory unit; and sequentially storing and buffering data read in parallel from the memory unit one byte from the memory unit while the address flag is non-active (4). Step) and the read data buffered by 1 byte From the first bit of the clock it is made in synchronization with 8 to sequentially move to the right on the second clock (5) for a real shear outputted to the outside via the input-output pins step.

The step further includes the step of automatically incrementing the address every ninth clock of the shift clock after step (3). The address flag of step (1) is activated when the serial data transitions from logic " low " to logic " high " while the shift clock is logic " high " and the M bytes in step (3). It stays active until you save the data sequentially.

Hereinafter, the configuration and operation of a programmable microcontroller according to the present invention and a method of writing and reading data in the circuit will be described in detail with reference to the accompanying drawings. Referring to FIG. 1, the programmable microcontroller according to the present invention includes a central processing unit 11, a memory unit 13, and a serial interface circuit 15.

The central processing unit 11 reads data stored in the memory unit 13 to perform arithmetic and control functions. The memory unit 13 is a built-in ROM, which is an OTP type EPROM or an MTP type EEPROM. Or it consists of a flash ROM and stores the data that is applied to the application coded from the outside. The serial interface circuit 15 transmits the serial data SDAT, ie, the address and data of the memory unit 13, which are externally applied through the input / output pin 17 during a write operation, through the clock pin 19. In synchronism with the applied shift clock SCLK, the signal is serially received and transferred to the memory unit 13 in parallel. In addition, the serial interface circuit 15 serially transmits data transmitted in parallel from the memory unit 13 to the external clock through the input / output pin 17 in synchronization with the shift clock SCLK during a read operation. do.

In particular, the serial interface circuit 15 includes an address field detector 15a, a shift register 15b, an address register section 15c, and a write / read buffer 15d.

The address field detector 15a receives the serial data SDAT and the shift clock SCLK, detects an address field condition in the serial data SDAT, and generates an address flag FLAG.

The shift register 15b is an 8-bit shift register. During the write operation, the serial data SDAT, which is externally applied one bit at a time, is moved to the right in synchronization with the shift clock SCLK (Shift). right) After 8 bits are stored, 8-bit data is stored in parallel. In addition, the shift register 15b synchronizes 8-bit read data input parallel from the memory unit 13 through the write / read buffer 15d to the right side in synchronization with the shift clock SCLK during a read operation. It moves and outputs serially to the outside through the input / output pins 17 bit by bit.

The address register section 15c includes three 8-bit address registers, that is, first through third address registers 15c1, 15c2, and 15c3, and the shift register 15b while the address flag FLAG is activated. 24 bits, that is, three bytes of data of the address field, which are output in parallel from each other by 8 bits are sequentially stored and output as the first address of the memory unit 13. The address register section 15c then outputs the first address and then generates an address that is automatically incremented.

The write / read buffer 15d is composed of 8 bits, and in the case of the write mode while the address flag FLAG is non-active, data output in parallel from the shift register 15b by 8 bits, that is, the 3 bytes. The data of the data field of one byte or more input after the address field of the buffer is buffered and output as write data to be written to the memory unit 13. In the read mode, the write / read buffer 15d buffers 8 bits of data read from the memory unit 13 and outputs the read data as the read data.

FIG. 2 is a diagram illustrating a protocol of the serial data (SDAT) format shown in FIG. 1.

Referring to FIG. 2, in the serial data (SDAT) format protocol, a start condition 21 of a first part and an address of three consecutive bytes, that is, addresses of first to third addresses 22, 23, and 24, are described. Field, a plurality of consecutive bytes, that is, a data field of first to nth data 25 to 28, and a termination condition 29 of the last part.

FIG. 3 is a waveform diagram of the serial data SDAT and the shift clock SCLK shown in FIG. 1.

Hereinafter, the operation of the programmable microcontroller according to the present invention shown in FIG. 1 and the data writing and reading method performed in the circuit will be described in detail with reference to FIGS. 2 and 3.

First, in the data writing method, the serial data SDAT applied through the one input / output pin 17 is externally synchronized with the shift clock SCLK applied through the clock pin 19. And writing to the memory unit 13 in parallel. Here, the first byte of the serial data SDAT continuously input after the start conditions 21 and 31 shown in FIGS. 2 and 3, that is, the least significant bit LSB of the first address 22 (FIG. When A16) shown in 3 is " 0 ", the write mode is entered.

In more detail, first, the address field detector 15a receives the serial data SDAT and the shift clock SCLK to detect an address field condition in the serial data SDAT to detect the address flag FLAG. (Step 1). In this case, the address flag FLAG is set to the logic condition that the serial data SDAT is logic low when the start conditions 21 and 31 shown in FIGS. 2 and 3, that is, the shift clock SCLK is logic "high". Active when transitioning from "logical to high". Next, three bytes of the serial data SDAT continuously inputted after the start conditions 21 and 31, that is, first to third addresses 22, 23 and 24 (A23 to A0 shown in FIG. 3). Is recognized as an address field so that the address flag FLAG remains active during the address field. Thereafter, a plurality of bytes input after the three-byte address field, that is, the first to n-th data 25 to 28 are recognized as data fields, and the address flag FLAG is non-active.

After the first step, the shift register 15b sequentially synchronizes the serial data SDAT externally applied one bit at a time to the first to eighth clocks of the shift clock SCLK. (Shift right) stores one byte at a time, and then synchronizes with the ninth clock, that is, the dummy clock, in parallel with three bytes of data of one byte, that is, the first to third addresses (22, 23, 24). Output sequentially (step 2).

After the second step, the address register unit 15c outputs the three bytes of data, which are parallelly outputted one by one from the shift register 15b while the address flag FLAG is activated, that is, the first to third ones. Addresses 22, 23, and 24 are sequentially stored and output as the first address of the memory unit 13 (third step). Thereafter, the address register section 15c automatically increments the address for every ninth clock of the shift clock SCLK, that is, a dummy clock, and outputs an address to be written next.

After the third step, the write / read buffer 15d is parallelized by one byte from the shift register 15b after the three bytes of data while the address flag FLAG is non-active. That is, the first to n-th data 25 to 28 are sequentially buffered and output as write data to be written to the memory unit 13 (fourth step).

By the above operation, after the first address is output from the address register section 15c and the first data 25 is output from the write / read buffer 15d, the ninth of the shift clock SCLK is performed. The first data 25 is written at the falling edge of the clock, that is, the dummy clock. The second to n-th data 26 to 28 are sequentially written to the addresses sequentially increased by the address register section 15c. Thereafter, after the dummy data FF is further input from the outside, the writing operation is terminated.

In addition, the data reading method, through the input and output pin 17 in synchronization with the shift clock (SCLK) applied through the clock pin 19 to the data read out by 8 bits in parallel in the memory unit 13 Serially transmitting to the outside. Here, the first byte of the serial data SDAT continuously input after the start conditions 21 and 31 shown in FIGS. 2 and 3, that is, the least significant bit LSB of the first address 22 (FIG. When A16 shown in 3 is " 1 ", the read mode is entered.

More specifically, as in the writing operation, the address field detector 15a first receives the serial data SDAT and the shift clock SCLK to detect an address field condition in the serial data SDAT. To generate the address flag FLAG (first step).

After the first step, the shift register 15b sequentially synchronizes the serial data SDAT externally applied one bit at a time to the first to eighth clocks of the shift clock SCLK. (Shift right) stores one byte at a time, and then synchronizes with the ninth clock, that is, the dummy clock, in parallel with three bytes of data of one byte, that is, the first to third addresses (22, 23, 24). Output sequentially (step 2).

After the second step, the address register unit 15c outputs the three bytes of data, which are parallelly outputted one by one from the shift register 15b while the address flag FLAG is activated, that is, the first to third ones. Addresses 22, 23, and 24 are sequentially stored and output as the first address of the memory unit 13 (third step). Thereafter, the address register section 15c automatically increments the address for every eighth clock of the shift clock SCLK and outputs an address to be read next.

After the third step, the write / read buffer 15d sequentially buffers data read-by-byte in parallel from the memory unit 13 according to the address while the address flag FLAG is non-active ( Step 4).

After the fourth step, the shift register 15b receives the read data buffered by one byte in parallel in synchronization with the dummy clock of the shift clock SCLK, and includes the first to eighth clocks of the shift clock SCLK. Are sequentially synchronized to the right side and serially output to the outside one by one through the input / output pin 17.

According to the operation as described above, the first to n-th data 26 to 28 read out from the address sequentially increased by the address register unit 15c are serially through the input / output pin 17. It is output to the outside. Then, when the serial data SDAT transitions from logic "high" to logic "low" while the shift clock SCLK is logic "high", that is, the termination condition 29 shown in FIGS. At 33, the read operation is terminated.

As described above, the present invention has been limited to one embodiment, but not limited thereto. It is obvious that various modifications to the present invention can be made by those skilled in the art within the scope of the spirit of the present invention. .

As described above, the programmable microcontroller for performing the data writing and reading method according to the present invention includes a serial interface circuit, so that only one data input / output pin and one clock pin are required for writing and reading operations, thereby reducing the number of pins. do. Therefore, there is an advantage that can be assembled in a package with a small number of pins. In addition, since only one data input / output pin and one clock pin are needed regardless of the capacity of the internal memory, even if the programmable microcontrollers have different capacity of internal memory, they can be assembled in the same package. There is an advantage that can be used.

1 is a block diagram of a preferred embodiment of a programmable microcontroller according to the present invention.

FIG. 2 is a diagram illustrating a protocol of the serial data format shown in FIG. 1. FIG.

FIG. 3 is a waveform diagram of the serial data and shift clock shown in FIG.

Claims (18)

A memory unit; A central processing unit which reads data from the memory unit and performs arithmetic and control functions; And Serial data applied externally through an input / output pin during a write operation is synchronized with a shift clock applied through a clock pin to serially receive and parallelly transfer the serial data to the memory unit. A serial interface circuit for serially transmitting data to the outside through the input / output pins in synchronization with the shift clock; The serial interface circuit, An address field detector for receiving the serial data and the shift clock to detect an address field condition in the serial data to generate an address flag; In the write operation, the serial data is shifted to the right in synchronization with the shift clock, stored, and then output in parallel. In the read operation, the parallel data is moved to the right and serially output to the outside. register; An address register section for storing data output in parallel from the shift register while the address flag is activated and outputting the first address as the first address of the memory section; And In the write mode while the address flag is non-active, the data output in parallel from the shift register is buffered and output as write data to be written in the memory unit. In the read mode, the data read from the memory unit is read. And a write / read buffer which is buffered and output as the read data. The programmable microcontroller of claim 1, wherein the memory unit comprises at least one selected from an EPROM, an EEPROM, and a flash memory. The address field detector of claim 1, wherein the address field detector activates the address flag when the data transitions from logic "low" to logic "high" while the shift clock is logic "high" and then serially inputs. Recognizes M bytes (M is an integer) of the data as an address field to maintain an active state of the address flag, and then recognizes N bytes (N is an integer) input as a data field to recognize the address flag. Programmable microcontroller, characterized in that the active. 4. The programmable microcontroller according to claim 3, wherein M is 3 and N is at least one. 2. The programmable microcontroller of claim 1, wherein the shift register is an 8-bit shift register. The programmable microcontroller of claim 1, wherein the address register unit generates an address that is automatically incremented after outputting the first address. The programmable microcontroller according to claim 1, wherein the address register section includes N 8-bit address registers and sequentially stores N bytes of data sequentially output from the shift register in parallel. The programmable microcontroller according to claim 1, wherein the write / read buffer is composed of 8 bits. A data writing method of a programmable microcontroller having a memory unit and a central processing unit configured to read data from the memory unit and perform arithmetic and control functions. And serially receiving serial data applied through an input / output pin externally and synchronizing with a shift clock applied through a clock pin and writing parallel to the memory unit. The step, (1) receiving the serial data and the shift clock to detect an address field condition in the serial data to generate an address flag; (2) sequentially synchronizing the serial data to the first to eighth clocks of the shift clock, moving the serial data to the right to store one byte, and outputting one byte in parallel to the ninth clock; (3) sequentially storing data of M (M is a natural number) bytes sequentially outputted in parallel by one byte while the address flag is activated and outputting the data as the first address of the memory unit; And (4) sequentially storing and buffering N (N is a natural number) bytes of data output after the M bytes of data while the address flag is non-active, and outputting them as write data to be written to the memory section. And a data writing method. 10. The method of claim 9, wherein said step further comprises the step of automatically increasing said address every ninth clock of said shift clock after said step (3). 10. The method according to claim 9, wherein the address flag of step (1) is activated when the serial data transitions from logic "low" to logic "high" while the shift clock is logic "high". And maintaining an active state until the M-bytes of data are sequentially stored in the step S). 10. The method of claim 9, wherein M is 3 and N is at least one. 10. The method of claim 9, wherein the memory unit is one selected from an EPROM, an EEPROM, and a flash memory. A data reading method of a programmable microcontroller having a memory unit and a central processing unit configured to read data from the memory unit and perform arithmetic and control functions. Synchronizing data read parallel from the memory unit with a shift clock applied through a clock pin and transmitting the data serially to the outside through an input / output pin; The step, (1) receiving the serial data and the shift clock to detect an address field condition in the serial data to generate an address flag; (2) The serial data is sequentially synchronized with the first to eighth clocks of the shift clock, shifted to the right, and stored by one byte, and then synchronized with the ninth clock, M by one byte in parallel (M is a natural number). Outputting bytes; (3) sequentially storing M-bytes of data output in parallel by one byte while the address flag is activated and outputting the data as a first address of the memory unit; (4) sequentially storing and buffering data read in parallel from the memory unit by one byte while the address flag is non-active; And (5) receiving the read data buffered by 1 byte and sequentially synchronizing with the first to eighth clocks of the shift clock to the right to serially output to the outside through the input / output pins; Data reading method. 15. The method of claim 14, wherein the step further comprises, after step (3), automatically increasing the address for every ninth clock of the shift clock. The address flag of claim 14, wherein the address flag of the step (1) is activated when the serial data transitions from a logic "low" to a logic "high" while the shift clock is logic "high." And keeping the active state until the M-bytes of data are sequentially stored in step). 15. The method of claim 14, wherein M is three. 15. The method of claim 14, wherein the memory unit comprises one selected from an EPROM, an EEPROM, and a flash memory.