KR100499755B1 - Method of fabricating deep sub-micron cmos source/drain with mdd and selective cvd silicide - Google Patents

Abstract

The present invention relates to a method of forming a MOS or CMOS device on a silicon substrate, comprising: forming a substrate to include a conductive region having a device active region therein; Forming a gate electrode on the device active region; Depositing and forming a gate electrode sidewall insulating layer on each gate electrode; Implanting ions of a first type to form source and drain regions in one device active region; And implanting a second type of ions to form a source region and a drain region in the other device active region.

Description

METHODS OF FABRICATING DEEP SUB-MICRON CMOS SOURCE / DRAIN WITH MDD AND SELECTIVE CVD SILICIDE}

The present invention relates to a method for fabricating a metal oxide semiconductor (MOS) and a complementary metal oxide semiconductor (CMOS) integrated circuit (IC), and more particularly to a new method having fewer steps than conventional sub-micron MOS and CMOS fabrication methods. It is about.

Known state-of-the-art processes for forming the source / drain regions of active devices in integrated circuits including MOS and CMOS transistors, followed by little ion implantation, known as LDD implantation, gate sidewall insulator formation, and n + and p + ion implantation. After n + and p + ion implantation, a salicide process is generally required to reduce parasitic resistance in the source / drain regions of the device. This requires four separate masking operations using the prior art. That is, two masks are required for LDD ion implantation, a third mask is required for n + ion implantation, and a fourth mask is required for p + ion implantation. One example of a silicide process is the deposition of refractory metals, followed by rapid thermal annealing (RTA) to form mono salicides. After the RTA, another RTA step is followed to etch the unreacted metal and form a low resistance di-silicide.

Accordingly, there is a need for a method of manufacturing a MOS device and a CMOS device in which mask level and ion implantation steps are reduced.

There is also a need for a method of providing a silicide layer using only a single selective CVD silicide deposition.

The present invention provides a method of forming a MOS device on a silicon substrate. The steps in one embodiment of the present invention include forming a substrate to include a conductive region of a first conductivity type having a first device active region; Forming a gate electrode structure having a gate electrode and an insulating sidewall on the first device active region; Implanting ions of a type opposite to the conductivity type of the first device active region into the exposed portion of the conductive region to form a source region and a drain region on opposite surfaces of the gate electrode structure; And depositing a silicide layer by selective CVD over the source and drain regions and over the gate electrode.

In addition, the preferred method of the present invention, in the implantation step, to form a surface ion concentration in the source and drain region in the range of about 1.0 x 10 ¹⁹ cm ^-3 to 1.0 x 10 ²² cm ^-3 , from about 0.5 keV to 2 keV Ion implantation using plasma immersion ion implantation in an implantation amount ranging from about 1.0 × 10 ¹⁴ cm ⁻² to 1.0 × 10 ¹⁵ cm ⁻² in the energy range of.

In another preferred embodiment of the present invention for carrying out the above steps, low energy ion implantation is used prior to forming the gate sidewalls. When using low energy ion implantation, ions in an energy range of about 0.5 keV to 10 keV are formed to form surface ion concentrations in the range of about 1.0 x 10 ¹⁹ cm ^-3 to 1.0 x 10 ²² cm ^-3 in the source and drain regions. Carry out the injection.

In another embodiment of the present invention, a method of forming a CMOS device on a silicon substrate is provided. In this embodiment, a second type of conductive region having a first type of active region having a first device active region in a first type of conductive region and having a second device active region in a second type of conductive region is provided. The substrate is formed to include. Also, forming a plurality of gate electrodes on the first and second device active regions, depositing and forming a gate electrode sidewall insulating layer on each gate electrode, masking a first type of conductive region, source Implanting ions of a first type into an exposed portion of a second type of conductive region to form a region and a drain region, removing a mask, masking a second type of conductive region, and source and drain regions Implanting a second type of ions into an exposed portion of a first type of conductive region to form, removing a mask, and preferably over the source / drain regions of the first device active region and the second device active region Depositing a silicide layer by selective CVD.

In another embodiment, the method further includes implanting ions to form source / drain regions using plasma immersion ion implantation as described above.

In another embodiment of the present invention, a CMOS device is formed by the steps described above except that ion implantation is performed prior to forming the gate sidewall using low energy ion implantation, and the gate sidewall is formed after the ion implantation steps. Is formed.

The method of the present invention for forming a CMOS device on a substrate is described. The present invention provides a CMOS device fabrication technique in which at least two of the masking and photoresist removal steps used in conventional CMOS fabrication are reduced. In addition, the salicide layer is deposited in a single chemical vapor deposition (CVD) process to reduce time and cost in the manufacturing process. One embodiment of the present invention utilizes plasma immersion ion implantation, which is generally efficient and desirable for forming the required CMOS. Low energy ion implantation may also be used and is presented as another embodiment of the present invention.

"Sub-micron" means that the width of the gate electrode used in the structure of the present invention is less than 1000 nm. Suitable integrated circuit interconnect materials are any available including all such refractory metals where the most common refractory metal is aluminum. In embodiments of the present invention, structures and fabrication processes may be used to form p wells in n-type substrates but n wells in p-type substrates to form complementary metal oxide semiconductor (CMOS) devices.

Plasma Immersion Ion Implantation

Referring to FIG. 1, structure 10 includes a substrate 12, which may be single crystal silicon, in which the structure in the preferred embodiment is an n-type substrate. A state-of-the-art process is performed to form the p well, which is the first device active region, in the n channel region, which in the present invention is called the first type of conductive region. An n well 16 is formed on the substrate 12, which functions as a second device active region in the p channel region and is referred to herein as a second type of conductive region. The terms "first type" and "second type" may be used interchangeably with the terms "first conductivity type" and "second conductivity type" in the present invention, and the first conductivity type may refer to the second conductivity type. N-type or p-type semiconductor material that is opposite. Appropriate device isolation and threshold voltage regulation is performed on the substrate, resulting in isolation region 21, followed by gate oxidation and gate electrode formation, as a result of p well gate electrode across gate region 17. An n well gate electrode 20 is formed over the gate 18 and the gate region 19.

An insulating thin film layer such as silicon oxide or silicon nitride is deposited by CVD and formed by plasma anisotropic etching, so as to show the gate electrode sidewall insulating layers 22 and 24 on the gate electrodes 18 and 20, as shown in FIG. Will be formed respectively.

Referring to Fig. 3, photoresist layer 26 is formed over the p-channel region, which is the second device active region in this embodiment. Plasma immersion ion implantation is performed to implant n-type ions into the exposed portion of the first device active region 14, where n-type ions are referred to as ions of the second type. Arsenic or phosphorus ions are implanted by plasma immersion ion implantation with implantation energy in the range of about 0.5 keV to 2 keV to dope the surface of the p well 14. Generally, the preferred dosage range of implanted ions is 1.0 × 10 ¹⁴ cm ⁻² to 1.0 × 10 ¹⁵ cm ⁻² . As a result, n + source region 30 and n + drain region 32 are formed. The surface concentration of ions in the n + source / drain region is 1.0 × 10 ¹⁹ cm ⁻³ to 1.0 × 10 ²² cm ⁻³ . In various embodiments described herein, an intermediate (or suitably) doped drain (MDD) region is generated by the method of forming the source / drain regions. Thereafter, the mask 26 is removed.

4, the photoresist 34 is deposited over the n channel region, which is the first device active region 14. Plasma immersion ion implantation is performed to implant p-type ions into the exposed portion of the second device active region 16. Boron or BF ₂ ions are implanted again using plasma immersion ion implantation with implantation energy in the range of about 0.5 keV to 2 keV to dope the surface of the p channel region 16. In general, the preferred amount of ion implantation is about 1.0 × 10 ¹⁴ cm ⁻² to 1.0 × 10 ¹⁵ cm ⁻² . As a result, the p + drain region 38 and the p + source region 40 are formed. The surface concentration of ions in the p + source / drain region is 1.0 × 10 ¹⁹ cm ⁻³ to 1.0 × 10 ²² cm ⁻³ . Thereafter, the mask 34 is removed.

Referring to FIG. 5, a silicide layer is deposited over the source and drain regions, resulting in the silicide layer 42 in the n channel region and the silicide layer 44 in the p channel region. The silicide is deposited by performing selective CVD of the silicide only onto the conductive region of the substrate including the source, gate electrode, and drain regions. Selective CVD of silicide does not deposit silicide on insulating surfaces such as isolation region 21 and gate sidewalls 22, 24. Selective CVD of silicides is a prior art already known to those skilled in the art of IC fabrication. For example, Maa's "Selective Deposition of TiSi2 On Ultra-Thin Silicon-on-Insulator (SOI) Wafers" published in Thin Solid Films, Vol. 332, pages 412-417, 1998, Mat.Res.Soc.Symp. .Proc. Maa, "Effects on Selective CVD of Titanium Disilicide by Substrate Doping and Selective Silicon Deposition", vol. 564, pp. 85-89, 1999, Mat.Res.Soc.Symp.Proc. Maa's "Prevention of Corner Voiding in Selective CVD Deposition of Titanium Silicide on SOI Device," pages 564, pages 29-34, and J.Vac.Sci.Technology B 17 (5), September / October 1999 See, "Selectivity to Silicon Nitride in Chemical Vapor Deposition of Titanium Silicide", disclosed in 2243-2247.

The structure can be activated by annealing before or after the selective CVD deposition step. Annealing proposed for use in the various embodiments described herein is generally in the range of 600 ° C. to 1000 ° C. for about 10 seconds to 30 minutes.

As shown in FIG. 6, an oxide layer 46 is deposited by CVD, followed by metallization. The electrode 48 to the nMOST source 30, the electrode 50 to the nMOST gate 18, the electrode 52 to the nMOST drain 32, the electrode 54 to the pMOST drain 38, and the electrode ( 56 is connected to the pMOST gate 20 and the electrode 58 to the pMOST source 40.

Ions can pass significantly laterally through the insulating sidewall spacers at the gate electrode by low energy plasma immersion ion implantation. Thus, by using known techniques for selecting sidewall thicknesses, an appropriate sidewall insulator thickness and appropriate gate to source / drain overlap can be obtained. See, for example, "Plasma Immersion Ion Implantation for Semiconductor Processing" by N.W. Cheung, 1996, published in Materials Chemistry and Physics, Vol. 46, pages 132-139.

It is apparent to those skilled in the art that the order of masking and ion implanting the first and second device active regions 14, 16 is not defined and can be reversed. For example, an alternative method may first mask the first device active region 14 as shown in FIG. 4, implant the first type of ions into the second device active region 16, remove the mask and 3, masking the second device active region 16 and implanting a second type of ions into the first device active region 14. Other steps of the method of the present invention do not change.

Low energy ion implantation

Conventional low energy ion implantation results in a very small number of doped ions passing laterally. As described with reference to FIGS. 7-11, the process sequence of the preferred embodiment is modified to form sidewall insulators after the source and drain regions are formed.

Referring to FIG. 7, structure 70 includes a substrate 72, which may be single crystal silicon. State-of-the-art processes are performed to form p well 74 in the n channel region of structure 70 and n well 76 in the p channel region of structure 70. P well gate region 78 having a p well gate electrode 80 over the p well gate region by forming isolation region 77 and performing threshold voltage regulation, followed by gate oxidation, gate electrode formation, due to proper device isolation. ) And an n well gate region 82 having n well gate electrodes 84 over the n well gate region.

As shown in FIG. 7, a photoresist layer 86 is formed over an n channel region that is a first device active region 74 and a p channel region that is a second device active region 76. A portion of the photoresist across the n channel is etched to expose the p well 74, which is the first device active region. Ion implantation of low energy phosphorus or arsenic is performed in the range of about 0.5 keV to 10 keV to dope the surface of the p well 74. Preferred ion implantation ranges are generally about 1.0 × 10 ¹⁴ cm ⁻² to 1.0 × 10 ¹⁵ cm ⁻² . As a result, n + source region 90 and n + drain region 92 are formed. The ion surface concentration of ions in the n + source / drain region is 1.0 × 10 ¹⁹ cm ⁻³ to 1.0 × 10 ²² cm ⁻³ . Thereafter, the mask 86 is removed.

Referring to FIG. 8, a photoresist mask 94 is deposited over n channel region 74, which is the first device active region. Low energy boron ions or BF ₂ implantation is again performed in the range of about 0.5 keV to 10 keV to dope the surface of the second device active region 76. Preferred ion implantation ranges are generally about 1.0 × 10 ¹⁴ cm ⁻² to 1.0 × 10 ¹⁵ cm ⁻² . As a result, the p + drain region 98 and the p + source region 100 are formed. Ion surface concentrations in the p + source / drain regions range from 1.0 × 10 ¹⁹ cm ⁻³ to 1.0 × 10 ²² cm ⁻³ . Thereafter, the mask 94 is removed.

As shown in Fig. 9, a thin film insulating layer such as silicon oxide or silicon nitride is deposited by CVD and plasma anisotropic etching to form sidewall insulators 102 and 104 for the gate electrodes 80 and 84, respectively.

Referring to FIG. 10, after forming the sidewall insulators 102 and 104, the silicide layer in the p-channel region by selectively depositing silicide by CVD over the source region, the drain region, and the gate electrode 80, 84. A silicide layer 106 is formed in 108 and the n channel region. Preferred silicide films include titanium silicides, but the silicide films are not limited to such titanium silicides. Deposition may be performed in an RTCVD reactor using a gas mixture comprising TiCl ₄ , silane, dichlorosilane, and hydrogen. When selecting other silicide membranes such as cobalt silicide, nickel silicide, an appropriate precursor is used to replace TiCl ₄ .

As shown in FIG. 11, the oxide layer 110 is deposited by CVD, followed by passivation and metallization. Electrode 112 to CMOS nMOST source 90, electrode 114 to nMOST gate 80, electrode 116 to nMOST drain 92, electrode 118 to pMOST drain 98, electrode Connect 120 to pMOST gate 84 and electrode 122 to pMOST source 100.

A method of forming a CMOS transistor according to the present invention has been described. In addition, the present invention can produce a MOS device having the same conductivity in which all the devices are formed in the device active region of the substrate. In describing the formation of a MOS transistor according to the present invention, reference numerals are described only in the left half of FIGS. 1 to 11 where n-channel devices are formed. The present invention is equally applicable to forming a p-channel device using the same method, but the ions implanted at this time and the conductivity of the substrate are reversed.

With reference to the left half of FIGS. 1 to 6, a method of forming a MOS device on the silicon substrate 12 will be described. In this embodiment, the substrate having the first device active region 14 of P type conductivity is formed. A gate electrode structure is formed on the first device active region 14, which includes an electrode 18 and an insulating sidewall 22. The substrate, gate and sidewalls are formed as described above in the previous embodiments.

Referring to FIG. 3, ions having conductivity opposite to that of the first device active region 14 are implanted into the exposed portion of the substrate to form source and drain regions on opposite sides of the gate structure. In this embodiment, n type ions are implanted into the p well 14. In this embodiment, plasma immersion ion implantation is performed to implant n-type ions into the exposed portion of the first device active region 14. To dope the surface of the p well 14, arsenic or phosphorus ions are implanted by plasma immersion ion implantation with implantation energy ranging from about 0.5 keV to 2 keV. Preferred ion implantation ranges are generally about 1.0 × 10 ¹⁴ cm ⁻² to 1.0 × 10 ¹⁵ cm ⁻² . As a result, n + source region 30 and n + drain region 32 are formed. The surface ion concentration in the n + source / drain region is 1.0 × 10 ¹⁹ cm ⁻³ to 1.0 × 10 ²² cm ⁻³ .

Referring to FIG. 5, a silicide layer is deposited over the source and drain regions 30 and 32, resulting in the silicide layer 42 in the n channel region. Silicide is deposited by CVD onto the conductive region of the substrate including the source, gate electrode, and drain regions.

Finally, as shown in FIG. 6, an oxide layer 46 is deposited by CVD, followed by metallization. The electrode 48 is connected to the nMOST source 30, the electrode 50 to the nMOST gate 18, and the electrode 52 to the nMOST drain 32.

With reference to the left half of FIGS. 7 to 11, a method of forming a MOS device on a silicon substrate 72 using low energy ion implantation instead of plasma immersion ion implantation will be described. Referring to Fig. 7, a substrate having a first device active region 74 of p type conductivity in this embodiment is formed. A gate electrode structure is formed on the first device active region 74, which includes the electrode 80, but does not include insulating sidewalls. The substrate, gate, and sidewalls are formed as described above in previous embodiments.

Referring to FIG. 8, to form source and drain regions on opposite surfaces of the gate structure, ions of conductivity opposite to those of the first device active region 74 are implanted into the exposed portion of the substrate. In this embodiment, p type ions are implanted into the p well 74. In this embodiment, low energy ion implantation is performed to implant n type ions into the exposed portion of the first device active region 74. To dope the surface of the p well 74, arsenic or phosphorus ions are implanted with implantation energy in the range of about 0.5 keV to 10 keV by low energy ion implantation. Preferred ion implantation ranges are generally about 1.0 × 10 ¹⁴ cm ⁻² to 1.0 × 10 ¹⁵ cm ⁻² . As a result, n + source region 90 and n + drain region 92 are formed. The surface ion concentration in the n + source / drain region is 1.0 × 10 ¹⁹ cm ⁻³ to 1.0 × 10 ²² cm ⁻³ .

As shown in the left half of FIG. 9, an insulating side wall 102 is formed around the gate electrode 80.

Thereafter, a silicide layer is deposited over the source and drain regions 90 and 92, and the gate electrode 80, and as a result, the silicide layer 108 is formed as shown in FIG. Silicide is deposited by CVD onto the conductive region of the substrate including the source, gate electrode, and drain regions.

Finally, as shown in FIG. 11, the oxide layer 110 is deposited by CVD, followed by metallization. The electrode 112 is connected to the nMOST source 90, the electrode 114 is connected to the nMOST gate 80, and the electrode 116 is connected to the nMOST drain 92.

As described above, a CMOS source / drain with deep sub-micron MOS and MDD, and a method for producing selective CVD silicide have been described.

The invention can be variously modified or modified within the scope of the claims.

According to the present invention, the throughput of plasma immersion ion implantation is many times higher than that of conventional ion implantation. The processing time increases in proportion to the wafer area when using conventional ion implantation while being constant for plasma immersion ion implantation, thus increasing the benefits as the substrate size increases. Therefore, the plasma immersion ion method is preferable when compared with the conventional ion implantation method.

1-6 show steps of the method of the present invention for plasma immersion ion implantation.

7-11 illustrate steps of a method of the present invention for low energy ion implantation.

Explanation of symbols on the main parts of the drawings

12 substrate 14 first device active region

16: second device active region 17: gate region

21: isolation region 22, 24: gate electrode sidewall insulating layer

26 photoresist layer 46 oxide layer

Claims (22)

A method of forming a MOS device on a silicon substrate, (a) preparing a substrate comprising a conductive region of a first conductivity type having a first device active region; (b) forming a gate electrode structure on the first device active region, the gate electrode structure having a gate electrode and an insulating sidewall; (c) a plasma immersion to form a source region comprising an LDD source region below the insulating sidewall and an drain region including an LDD drain region below the insulating sidewall on an opposite side of the gate electrode structure; Implanting ions of a type opposite to the conductivity type of the first device active region into an exposed portion of the conductive region using ion implantation; And (d) depositing a silicide layer by selective CVD over the source region, the drain region and the gate electrode. The method of claim 1, And wherein the plasma immersion ion implantation is performed at an energy in the range of 0.5 keV to 2 keV. The method of claim 1, And implanting the ions comprises implanting ions in an implantation amount ranging from about 1.0 × 10 ¹⁴ cm ⁻² to 1.0 × 10 ¹⁵ cm ⁻² . The method of claim 1, The implanting of the ions may include implanting ions so as to obtain a surface ion concentration in the source region and the drain region in the range of about 1.0 × 10 ¹⁹ cm ⁻³ to 1.0 × 10 ²² cm ⁻³ . Forming a MOS device. The method of claim 1, After said step (d) depositing a silicide layer by said selective CVD, depositing said insulating layer over the structure formed by said steps (a) to (d) and metallizing said structure. A method of forming a MOS device. delete delete delete delete delete A method of forming a CMOS device on a silicon substrate, (a) preparing a substrate to include a first type of conductive region having a first device active region therein and a second type of conductive region having a second device active region therein; (b) forming a plurality of gate electrodes in the first and second device active regions; (c) depositing and forming a gate electrode sidewall insulating layer on each of the gate electrodes; (d) masking the first device active region; (e) plasma to form a source region including an LDD source region below the sidewall insulating layer and a drain region including an LDD drain region below the sidewall insulating layer in the second device active region; Implanting ions of a first type into an exposed portion of the second device active region using immersion ion implantation; (f) removing the mask; (g) masking the second device active region; (h) a plasma is formed in the first device active region, a source region including an LDD source region below the sidewall insulating layer and a drain region including an LDD drain region below the sidewall insulating layer Implanting a second type of ions into an exposed portion of the first device active region using immersion ion implantation; (i) removing the mask; And (j) depositing a silicide layer over the gate electrode, the source region and the drain region in the first and second device active regions. delete The method of claim 11, The implantation steps (e) and (h) comprise implanting ions at an implantation amount in the range of about 1.0 x 10 ¹⁴ cm ^-2 to 1.0 x 10 ¹⁵ cm ^-2 at an energy level in the range of about 0.5 keV to 2 keV. A method of forming a MOS device, characterized in that. The method of claim 11, In the implantation step (e) and (h), the step of implanting ions to obtain a surface ion concentration in the source region and the drain region in the range of about 1.0 x 10 ¹⁹ cm ^-3 to 1.0 x 10 ²² cm ^-3 Method comprising a. The method of claim 11, Depositing the silicide (j) comprises depositing a silicide layer by selective CVD of the silicide. The method of claim 11, After (j) depositing the silicide layer, depositing an insulating layer over the structure formed by steps (a) to (j) and metallizing the structure. delete delete delete delete delete delete