KR100492901B1 - Manufacturing Method of Dielectric Capacitor of Semiconductor Device - Google Patents

Manufacturing Method of Dielectric Capacitor of Semiconductor Device Download PDF

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KR100492901B1
KR100492901B1 KR1019970075113A KR19970075113A KR100492901B1 KR 100492901 B1 KR100492901 B1 KR 100492901B1 KR 1019970075113 A KR1019970075113 A KR 1019970075113A KR 19970075113 A KR19970075113 A KR 19970075113A KR 100492901 B1 KR100492901 B1 KR 100492901B1
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film
manufacturing
semiconductor device
forming
dielectric capacitor
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KR19990055201A (en
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김경민
임찬
박기선
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment

Abstract

본 발명은 반도체 장치의 고유전체 캐패시터 제조 공정에 관한 것으로, 통상적인 하부전극의 RTN(Rapid Thermal Nitrification) 처리시 고온(800℃ 이상)에 따른 접합 영역의 확산을 방지하기 위하여, 저온 공정(150℃～500℃)을 통해 하부 전극과 Ta2O5 유전체막의 경계면에 산화방지막을 형성할 수 있는 고유전체 캐패시터 제조방법을 제공하는데 그 목적이 있다. 이를 위하여 본 발명으로부터 제공되는 특징적인 반도체 장치의 고유전체 캐패시터 제조방법은 소정의 하부층 상부에 하부 전극 형성을 위한 전도막을 형성하는 제1 단계; 150℃ 내지 500℃의 온도에서 질소를 포함하는 가스를 사용하여 상기 전도막의 표면을 플라즈마 처리하는 제2 단계; 및 상기 전도막 상부에 유전체로서 Ta2O5막을 형성하는 제3 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a high dielectric capacitor of a semiconductor device. In order to prevent diffusion of a junction region due to high temperature (800 ° C. or more) during a rapid thermal nitrification (RTN) process of a conventional lower electrode, a low temperature process (150 ° C.) It is an object of the present invention to provide a method of manufacturing a high dielectric capacitor capable of forming an anti-oxidation film at the interface between a lower electrode and a Ta 2 O 5 dielectric film. To this end, a method of manufacturing a high-k dielectric capacitor of a characteristic semiconductor device provided by the present invention includes a first step of forming a conductive film for forming a lower electrode on a predetermined lower layer; Plasma treating the surface of the conductive film using a gas containing nitrogen at a temperature of 150 ° C to 500 ° C; And a third step of forming a Ta 2 O 5 film as a dielectric over the conductive film.

Description

반도체 장치의 고유전체 캐패시터 제조방법Manufacturing method of high dielectric capacitor of semiconductor device

본 발명은 반도체 제조 분야에 관한 것으로, 특히 반도체 장치의 고유전체 캐패시터 제조 공정에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor manufacturing, and more particularly, to a process for manufacturing a high dielectric capacitor of a semiconductor device.

DRAM을 비롯한 반도체 장치의 고집적화에 따라 반도체 장치의 리프레시(refresh) 특성 등의 동작 특성이 큰 문제로 부각되었으며, 이를 해결하는 하나의 방안으로서 캐패시터의 하부 전극인 전하저장 전극의 표면적을 증가시키는 기술에 대한 많은 연구·개발이 진행되어 왔다. 그러나, 역시 고집적화에 따른 공정 마진의 확보를 위해서 전하저장 전극의 표면적을 증가시키는데는 한계가 있다.Due to the high integration of semiconductor devices including DRAM, operating characteristics such as refresh characteristics of semiconductor devices have emerged as a big problem. As a solution to this problem, a technique for increasing the surface area of a charge storage electrode, which is a lower electrode of a capacitor, is used. Many researches and developments have been conducted. However, there is also a limit to increase the surface area of the charge storage electrode in order to secure a process margin due to high integration.

이러한 한계를 고려하여, Ta2O5 등의 고유전체를 사용하는 캐패시터에 대한 관심이 증대되고 있는데, 이는 캐패시터의 정전용량이 유전율(ε)에 비례하는 원리를 적용한 것이다.Considering these limitations, interest in capacitors using a high dielectric constant such as Ta 2 O 5 is increasing, which applies a principle in which the capacitance of the capacitor is proportional to the dielectric constant (ε).

일반적으로, Ta2O5 캐패시터는 폴리실리콘 하부 전극 상에 유전체로서 Ta2O5 막을 증착하고, TiN막 또는 TiN/폴리실리콘막 구조의 상부 전극을 사용한다.Generally, Ta 2 O 5 capacitors deposit a Ta 2 O 5 film as a dielectric on a polysilicon bottom electrode and use a top electrode of a TiN film or a TiN / polysilicon film structure.

통상적으로, 폴리실리콘막 증착후, 후속 산소 분위기에서의 열처리시 폴리실리콘 하부 전극과 Ta2O5막의 경계면에서 산화막이 형성되는 것을 억제하기 위하여, RTN(Rapid Thermal Nitrification) 처리를 실시하게 된다.In general, a rapid thermal nitrification (RTN) treatment is performed to suppress the formation of an oxide film at the interface between the polysilicon lower electrode and the Ta 2 O 5 film during the subsequent heat treatment in an oxygen atmosphere after polysilicon film deposition.

그러나, 이러한 RTN 처리시 온도를 800℃ 이상으로 올려주어야 하므로 하부에 형성된 접합 영역(junction region)에서 확산이 일어나 접합 깊이에 변화를 가져오는 문제점이 있었다.However, since the temperature must be raised to 800 ° C. or higher during the RTN treatment, diffusion occurs in the junction region formed at the bottom, thereby causing a change in the junction depth.

본 발명은 저온 공정(150℃～500℃)을 통해 하부 전극과 Ta2O5 유전체막의 경계면에 산화방지막을 형성할 수 있는 고유전체 캐패시터 제조방법을 제공하는데 그 목적이 있다.It is an object of the present invention to provide a method of manufacturing a high dielectric capacitor capable of forming an anti-oxidation film on the interface between a lower electrode and a Ta 2 O 5 dielectric film through a low temperature process (150 ° C. to 500 ° C.).

본 발명으로부터 제공되는 특징적인 반도체 장치의 고유전체 캐패시터 제조 방법은 소정의 하부층 상부에 하부 전극 형성을 위한 전도막을 형성하는 제1 단계; 150℃ 내지 500℃의 온도에서 질소를 포함하는 가스를 사용하여 상기 전도막의 표면을 플라즈마 처리하는 제2 단계; 및 상기 전도막 상부에 유전체로서 Ta2O5막을 형성하는 제3 단계를 포함하여 이루어진다.A method of manufacturing a high dielectric capacitor of a characteristic semiconductor device provided from the present invention includes a first step of forming a conductive film for forming a lower electrode on a predetermined lower layer; Plasma treating the surface of the conductive film using a gas containing nitrogen at a temperature of 150 ° C to 500 ° C; And a third step of forming a Ta 2 O 5 film as a dielectric over the conductive film.

이하, 본 발명을 상술한다.Hereinafter, the present invention will be described in detail.

우선, 소정의 하부층 공정을 마친 기판 상에 캐패시터의 하부 전극 형성을 위한 폴리실리콘막을 증착한다. 이때, 폴리실리콘막의 전도성 확보를 위해 인-시츄(in-situ) 또는 이온주입 방식의 전도성 불순물 도핑을 실시한다.First, a polysilicon film for forming a lower electrode of a capacitor is deposited on a substrate having a predetermined lower layer process. At this time, in order to secure the conductivity of the polysilicon film, an in-situ or ion implantation conductive impurity doping is performed.

계속하여, 150℃～500℃의 온도를 유지하면서 NH3 가스 또는 N2 가스에 플라즈마를 여기시켜 폴리실리콘막 표면을 질화시킨다.Subsequently, plasma is excited to NH 3 gas or N 2 gas while maintaining the temperature of 150 ° C to 500 ° C to nitride the polysilicon film surface.

여기서, 상기 플라즈마 처리시 압력은 10mtorr～9torr 범위로 조절하며, NH3 가스 또는 N2 가스의 유량을 1slm～5slm로 하고, 100W～500W의 고주파(RF) 전원을 사용하여 0.5분～5분간 실시한다. 또한, RF 전극과 기판과의 거리를 0.5cm～5cm로 조절하며, RF 전원 인가시 기판을 접지로 처리하여 플라즈마에 의한 기판 손상을 줄일 수 있으며, RF 플라즈마 소오스 이외에 원격 ECR 플라즈마 소오스를 사용할 수 있다.Here, the pressure during the plasma treatment is adjusted in the range of 10 mtorr to 9 torr, and the flow rate of NH 3 gas or N 2 gas is set to 1 slm to 5 slm, and is performed for 0.5 to 5 minutes using a high frequency (RF) power source of 100 W to 500 W. do. In addition, the distance between the RF electrode and the substrate is controlled to 0.5 cm to 5 cm, and the substrate is grounded when RF power is applied to reduce substrate damage by the plasma. In addition to the RF plasma source, a remote ECR plasma source can be used. .

다음으로, 그 표면이 질화된 폴리실리콘막 상부에 유전체막인 Ta2O5막을 소정 두께로 형성한다. 이때, Ta2O5막의 형성은 다음과 같은 통상적인 방법을 사용할 수 있다. 즉, Ta2O5막을 증착하고, 300℃～450℃ 범위의 온도에서 O2 플라즈마 또는 N2O 플라즈마 처리를 실시하여 Ta2O5 내의 결함을 제거한다. 계속하여, 800℃ 이상의 고온에서 O2 또는 N2O 가스 분위기에서 열처리를 실시하여 Ta2O5막의 결정화를 이룬다.Next, a Ta 2 O 5 film, which is a dielectric film, is formed on the polysilicon film whose surface is nitrided to a predetermined thickness. At this time, the formation of the Ta 2 O 5 film can be used the following conventional method. That is, a Ta 2 O 5 film is deposited and an O 2 plasma or N 2 O plasma treatment is performed at a temperature in the range of 300 ° C. to 450 ° C. to remove defects in Ta 2 O 5 . Subsequently, heat treatment is performed in an O 2 or N 2 O gas atmosphere at a high temperature of 800 ° C. or higher to achieve crystallization of the Ta 2 O 5 film.

이후, 캐패시터의 상부 전극 형성 등의 후속 공정을 진행한다.Thereafter, a subsequent process such as forming an upper electrode of the capacitor is performed.

아래의 표 1은 동일한 증착 조건하에서 각각 RTN 처리 없이 증착한 경우(A), RTN 처리한 경우(B) 및 N2 가스를 사용한 플라즈마 처리한 경우(C), Si 기판상에 증착되는 Ta2O5막의 두께(다시 말해, Ta2O5막 및 형성된 산화막의 두께)를 측정한 실험 데이터를 나타낸 것이다.Table 1 below shows Ta 2 O deposited on Si substrates under the same deposition conditions (A), RTN treatment (B) and plasma treatment using N 2 gas (C) under the same deposition conditions. Experimental data showing the thickness of the five films (that is, the thicknesses of the Ta 2 O 5 film and the formed oxide film) are shown.

[표 1]TABLE 1

Figure pat00001
Figure pat00001

상기한 표 1에 도시된 바와 같이 RTN 처리한 경우(B)와 N2 가스를 사용한 플라즈마 처리한 경우(C)를 비교하면 6Å 정도의 Ta2O5막 증착 두께 차이는 있지만, 즉 산화막 억제 효과가 RTN 처리시보다는 다소 떨어지지만, RTN 처리를 실시하지 않은 경우(A)에 비해서는 월등한 산화막 형성 억제 효과가 있다.Compared with RTN treatment (B) and plasma treatment using N 2 gas (C) as shown in Table 1 above, there is a difference in deposition thickness of Ta 2 O 5 film of about 6 Å, that is, oxide film suppression effect. Is slightly lower than that of the RTN treatment, but has an excellent effect of suppressing oxide film formation compared to the case where the RTN treatment is not performed (A).

상기한 일실시예에서는 폴리실리콘막을 하부 전극으로 사용하는 단순 스택형 캐패시터를 일례로 하여 설명하였으나, 본 발명은 실린더형, 핀형, 반구형 폴리실리콘 캐패시터 등 캐패시터의 하부 전극의 형상 및 재질에 관계없이 적용할 수 있다.In the above embodiment, a simple stacked capacitor using a polysilicon film as the lower electrode has been described as an example. However, the present invention is applied regardless of the shape and material of the lower electrode of the capacitor, such as a cylindrical, pin-type, and hemispherical polysilicon capacitor. can do.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

이상에서와 같이 본 발명은 고유전체 캐패시터의 유전체막인 Ta2O5막 형성전, 하부 전극 표면에 상대적으로 저온(150～500℃)에서 NH3 또는 N2 플라즈마 처리함으로써 고온(800℃ 이상)의 열처리에 따른 접합 깊이의 변화를 감소시킬 수 있으며, 이로 인하여 반도체 장치의 신뢰성 향상을 기대할 수 있다.As described above, according to the present invention, before the formation of the Ta 2 O 5 film, which is a dielectric film of the high-k dielectric capacitor, NH 3 or N 2 plasma is treated at a low temperature (150 to 500 ° C.) relative to the lower electrode surface to obtain a high temperature (more than 800 ° C.) It is possible to reduce the change in the junction depth due to the heat treatment of, thereby improving the reliability of the semiconductor device can be expected.

Claims (3)

소정의 하부층 상부에 하부 전극용 폴리실리콘막을 형성하는 단계;Forming a polysilicon film for a lower electrode on a predetermined lower layer; 150℃ 내지 500℃의 온도에서 질소를 포함하는 가스를 사용하여 상기 전도막의 표면을 플라즈마 처리하는 단계; 및Plasma treating the surface of the conductive film using a gas containing nitrogen at a temperature of 150 ° C. to 500 ° C .; And 상기 전도막 상부에 유전체로서 Ta2O5막을 형성하는 단계를 포함하며,Forming a Ta 2 O 5 film as a dielectric over the conductive film, 상기 플라즈마 처리는 질소를 포함하는 가스의 유량비 1slm 내지 5slm, 10mtorr 내지 9torr의 압력, 100W 내지 500W의 고주파(RF) 전원 조건으로 수행하는 것을 특징으로 하는 반도체 장치의 고유전체 캐패시터 제조방법.The plasma treatment method is a high-k dielectric capacitor manufacturing method of a semiconductor device, characterized in that performed in a flow rate ratio 1slm to 5slm, a pressure of 10mtorr to 9torr, a high frequency (RF) power supply of 100W to 500W of a gas containing nitrogen. 제1항에 있어서,The method of claim 1, 상기 플라즈마 처리는 0.5분 내지 5분간 수행하는 것을 특징으로 하는 반도체 장치의 고유전체 캐패시터 제조방법.The plasma treatment is a high dielectric capacitor manufacturing method of a semiconductor device, characterized in that performed for 0.5 to 5 minutes. 제1항에 있어서,The method of claim 1, 상기 플라즈마 처리는 상기 고주파 전원 인가시 기판을 접지로 처리하는 것을 특징으로 하는 반도체 장치의 고유전체 캐패시터 제조방법.The plasma processing method of manufacturing a high dielectric capacitor of a semiconductor device, characterized in that for processing the substrate to ground when the high-frequency power is applied.
KR1019970075113A 1997-12-27 1997-12-27 Manufacturing Method of Dielectric Capacitor of Semiconductor Device KR100492901B1 (en)

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JPH0677433A (en) * 1992-08-25 1994-03-18 Miyazaki Oki Electric Co Ltd Manufacture of semiconductor device
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KR19990050864A (en) * 1997-12-17 1999-07-05 구본준 Capacitor Manufacturing Method

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