KR100482363B1 - Semiconductor device with protective diode and manufacturing method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a protection diode for protecting a gate oxide film from charge applied during a plasma process, and more particularly, to a gate electrode having an insulating film on an upper surface of a first conductivity type well of a semiconductor substrate, A transistor having a source / drain implanted with a second conductivity type impurity near the well surface under the edge; A first diode implanted with a second conductivity type impurity near a surface in the first conductivity type well; And a second diode in which the first conductivity type impurity is implanted in the substrate in the vicinity of the surface of the second conductivity type well adjacent to the first conductivity type well, and the gate electrode, the first diode, and the second diode of the transistor are the same. It is characterized in that connected to the wiring layer.

Description

Semiconductor device having protective diode and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high reliability semiconductor device, and more particularly, to a semiconductor device having a protection diode capable of preventing an electrical effect of charge trapped in a gate oxide film by a plasma process used in a manufacturing process of a MOS transistor, and a manufacturing method thereof. It is about.

Most semiconductor processes are very sensitive to the reliability of the gate oxide film. Among them, the process of damaging the gate oxide film includes etching, ashing, and deposition processes using plasma. However, recent semiconductor devices have tended to use more plasma processes by many back end processes due to multilayer wiring.

Accordingly, in the process of fabricating a high density integrated circuit using MOS technology having multiple metal layers, electrical charge may be trapped in the gate oxide of the device during the plasma process. That is, the charge is accumulated on the gate oxide film electrically connected to the floating polysilicon layer and the metal layer. As a result, interconnected metal layers acting as antennas increase the charge effect and lead to charges trapped in the gate oxide.

Therefore, the semiconductor device further includes a protection diode that can solve the charge trapped in the gate oxide film.

1 is a circuit diagram of a semiconductor device according to an embodiment having a protection diode according to the related art, in which the semiconductor device has an N-MOS having a drain 24, a source 25, and gate electrodes 18 and 20. And an N / P diode 26 connected to the gate electrodes 18 and 20 of the N-MOS transistor.

FIG. 2 is a layout diagram of a semiconductor device having the protection diode shown in FIG. 1, wherein the gate electrode pattern 17 of the N-MOS transistor formed on the P-type well 12 is spaced apart from the pattern 17 by a predetermined distance. The N / P diodes 26 into which the N-type impurities are injected into the P-type well 12 are connected to the same metal wiring layer 30.

3 is a vertical cross-sectional view taken along line AA ′ of FIG. 2, and FIG. 4 is a vertical cross-sectional view taken along line B-B ′ of FIG. 2, and FIG. 5 is a cross-sectional view taken along line C- of FIG. 2. It is a vertical cross section which cut | disconnected the semiconductor device by the C 'line. The semiconductor device may include a gate oxide layer 16 formed on the surface of the P-type well 12 into which the P-type impurity is implanted in the silicon substrate 10, a polysilicon layer 18 on the upper surface of the gate oxide layer 16, A gate electrode having the salicide layer 20 stacked thereon, a spacer 22 formed on the sidewall of the gate electrode, and a drain 24 in which N-type impurities are implanted into a surface of the P-type well 12 near the edge of the spacer 22. And the NMOS transistor having a source and a source 25 and a field oxide film 14 for isolation between devices, and the N-MOS transistor, and a surface of the P-type well 12 between the field oxide film 14. An N / P diode 26 implanted with N-type impurities is formed. At this time, the NMOS transistor and the N / P diode are connected to each other through the metal wiring layer 30 filled in the contact hole in the interlayer insulating film 28 formed for inter-device insulation.

The NMOS transistor having the above structure has the N / P diode 26 as a protective element, so that the charges trapped in the gate oxide film 16 are emitted by the N / P diode 26. However, in the actual process, the charging of the antenna is mainly performed by the plasma etching process, and the electric charge generated at this time is a positive charge. This positive charge is emitted through the N / P diode 26, but the effect of the charge trap is reduced when the ratio of the edge antenna, which is the product of the peripheral length of the metal wiring layer divided by the thickness of the gate oxide film, is increased. Accordingly, the NMOS transistor does not solve 100% of the positive charge through the N / P diode 26.

On the other hand, since the PMOS transistor uses a P / N diode as a protection element, the bad positive charge of the plasma trapped in the gate oxide film is solved 100% by the P / N diode. However, when negative charge is applied to the P-MOS transistor during the plasma process, the P / N diode alone cannot sufficiently solve the negative charge.

Therefore, the charges that are not emitted by the protection diode and trapped in the gate oxide film cause a loss of yield and reliability defects such as the destruction of the thin dielectric film or the change of the threshold voltage of the device. According to the ratio of the antenna area to the oxide film area, there is a problem of worsening the electrical effect of the transistor.

Disclosure of Invention An object of the present invention is to provide a semiconductor device having a protection diode capable of increasing the reliability of a gate oxide film by quickly exiting charge trapped in the gate oxide film due to a plasma process in order to solve the problems of the prior art as described above. It is to provide a manufacturing method.

In order to achieve the above object, an apparatus of the present invention includes a gate electrode formed by embedding an insulating film on an upper portion of a first conductive well in which a first conductivity type ion is ion-implanted into a predetermined region of a semiconductor substrate, and the first electrode below the gate electrode edge. A transistor having a source / drain formed by ion implantation of a second conductivity type impurity having conductivity opposite to the first conductivity type impurity in the vicinity of a conductive well surface; A first diode spaced apart from the transistor by a field oxide film and implanted with the second conductivity type impurity near a surface in the first conductivity type well; And a second diode in which a first conductivity type impurity is implanted near the surface of the second conductivity type well formed on the semiconductor substrate so as to be adjacent to the first conductivity type well on the semiconductor substrate by the field oxide layer. And the gate electrode, the first diode, and the second diode of the transistor are connected by the same wiring layer.

In order to achieve the above object, the manufacturing method of the present invention includes a first conductivity type well and a first conductivity type impurity having a conductivity opposite to each other in an adjacent region of the semiconductor substrate to a predetermined depth. Forming a second conductivity well; Forming an isolation region for isolation between devices in the semiconductor substrate on which the first conductivity well and the second conductivity well are formed; Forming an insulating film on the first conductivity type well in a region where a gate electrode is to be formed; Forming a gate electrode formed of a conductive layer on the insulating film; The second conductivity type impurities are implanted at a high concentration near the surface of the first conductivity type well to self-align the gate electrode edges to form a source / drain, and at the same time, the first distance is spaced apart from the gate electrode. Forming a transistor and a first diode in the first conductivity type well separated by the device isolation region by ion implantation of a second conductivity type impurity near the surface in the conductivity type well; Forming a second diode by ion implanting the first conductivity type impurity at a high concentration near the surface of the second conductivity type well; Forming a contact hole for selectively removing and exposing the interlayer insulating layer formed on the gate electrode, the first diode, and the second diode after forming the interlayer insulating layer on the entire surface of the resultant; And forming a conductive metal layer on the resultant to connect the gate electrode, the first diode, and the second diode to the conductive metal layer.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 6 is a circuit diagram of an embodiment of a semiconductor device having a protection diode according to the present invention, wherein the semiconductor device includes an NMOS transistor having a drain 116, a source 118, and gate electrodes 110 and 112. And an N / P diode 120 connected to the gate electrodes 110 and 112 of the N-MOS transistor, and a P / N diode 122 connected to the gate electrodes 110 and 112 of the N-MOS transistor.

FIG. 7 is a layout diagram of a semiconductor device having the protection diode shown in FIG. 6. The gate electrode pattern 109 of the NMOS transistor formed on the P-type well 102 is spaced apart from the pattern 109 by a predetermined distance. P-type in N / P diode 120 in which N-type impurity is implanted into P-type well 102 and N (eg, second conductivity) well 104 in proximity to P-type well 102 The impurity-injected P / N diodes 122 are all connected to the same metal wiring layer 126.

FIG. 8 is a vertical cross-sectional view taken along line AA ′ of FIG. 7, and FIG. 9 is a vertical cross-sectional view taken along line B-B ′ of FIG. 7, and FIG. It is a vertical cross section which cut | disconnected the semiconductor device by the C 'line. The semiconductor device may include a gate oxide film 108 formed on a surface of a P-type well 102 into which a P-type impurity (first conductivity type impurity) is implanted into a silicon substrate 100, and an upper surface of the gate oxide film 108. A gate electrode in which a conductive layer, that is, a polysilicon layer 110 and a salicide layer 112 are stacked, a spacer 114 formed on sidewalls of the gate electrode, and a P-type well 102 near an edge of the spacer 114. An N-MOS transistor having a drain 116 and a source 118 implanted with an N-type impurity (eg, a second conductivity type impurity) having conductivity opposite to the P-type impurity on a surface thereof, and for isolation between devices N / P diodes 120 (eg, first diodes) separated from other elements by the field oxide film 106 and implanted with N-type impurities near the surface of the P-type well 102 between the field oxide films 106. ) And an N-type formed in proximity to the P-type well 102 in the substrate 100. 104, the field oxide film 106 on the P-type impurity of P / N diodes (122, for example, the second diode) is injected between the surface it consists of a. In this case, the NMOS transistor, the N / P diode 120, and the P / N diode 122 are connected to each other through the metal wiring layer 126 filled in the contact hole in the interlayer insulating layer 124 formed for inter-device insulation. It is. Here, although the P-type impurity and the N-type impurity are exemplified as the first conductivity type impurity and the second conductivity type impurity, respectively, the N-type impurity may be the first impurity, and the P-type impurity is the second impurity. It could be

The NMOS transistor having the structure as described above has the N / P diode 120 and the P / N diode 122 as a protection element, and thus the gate oxide film 108 due to a plasma process frequently performed in a multilayer metal wiring process. Positive or negative charges trapped at them rapidly release through the diodes 120 and 122.

In addition, the present invention uses P / N diodes and N / P diodes as protection elements in the case of PMOS transistors. Therefore, the P-MOS transistor can be quickly released by the N / P diode even if the charge of the plasma trapped in the gate oxide film is negatively charged.

Meanwhile, the NMOS transistor is formed according to the following manufacturing process sequence.

As shown in FIG. 11, the P-type wells 102 and the N-type wells 104 are formed to be close to each other on the silicon substrate 100, and the P-type wells 102 and the N are formed using a conventional locus process. A field oxide film 106 is formed on the substrate 100 on which the type well 104 is formed for separation between devices. Subsequently, a gate oxide film 108 is formed as a thin insulating film in a region where the gate electrode G is to be formed.

Next, as shown in FIG. 12, polysilicon 110 is formed on the entire surface of the resultant as a conductive layer, and thallium is deposited thereon to form a salicide layer 12.

As shown in FIG. 13, a photolithography process is performed according to a gate mask to form a first photoresist pattern 113a on the upper surface of the salicide layer 12.

Subsequently, as illustrated in FIG. 14, the salicide layer 112 and the polysilicon layer 110 are sequentially etched to form a gate electrode G by an etching process.

After removing the first photoresist pattern 113a formed on the resultant, a photo process of opening a predetermined region where the NMOS transistor is to be formed is performed to apply a second photoresist pattern 113b to the upper part of the resultant. Subsequently, an oxidation process is performed on the entire surface of the resultant, and the oxide film formed by the process is etched by a dry etching process to form spacers 114 on the sidewalls of the gate electrode G as shown in FIG. 15. After removing the second photoresist pattern 113b, as shown in FIG. 16, a photolithography process is performed to open a region in which NMOS transistors and N / P diodes are to be formed, thereby forming a third photoresist pattern 115 on the resultant. ). Subsequently, a high concentration of N-type impurities are implanted into the resultant. As a result, sources / drains 118 and 116 in which N-type impurities are injected at a high concentration are formed near the surface of the P-type well 102 at the edge of the gate electrode G, and the P-type spaced apart from the gate electrode G by a predetermined distance. Near the surface of the well 102, that is, between the field oxide film 106, a first diode 120 in which N-type impurities are injected at a high concentration is formed.

Next, as shown in FIG. 17, the third photoresist pattern 115 applied to the resultant is removed, and a photo process is performed to open only a region where a P / N diode is to be formed. The resist pattern 121 is formed. Subsequently, a high concentration of P-type impurities are implanted into the resultant. As a result, a second diode 122 in which P-type impurities are injected at a high concentration is formed near the surface of the N-type well 104, that is, between the field oxide films 106.

Next, an interlayer insulating layer 124 is formed on the entire surface of the resultant material, and the photolithography process is performed to selectively expose a portion of the interlayer insulating layer 124 on the gate electrode, the first diode, and the second diode. Forming a contact hole by forming a pattern (not shown), removing the interlayer insulating layer 124 using the fifth photoresist pattern as an etching mask, and forming a conductive metal layer on the entire surface of the semiconductor substrate on which the contact hole is formed. The conductive metal layer is patterned to connect the gate electrode G, the first diode 120, and the second diode 122 with the same metal wiring layer 126 to complete the present invention.

According to the present invention according to the manufacturing process sequence as described above, even if the edge antenna ratio is increased due to the multi-layer metal wiring process, the effects of the charge trap generated in the gate oxide film of the NMOS transistor can be effectively coped by the diodes 120 and 122.

The present invention further includes a diode having an opposite polarity so that the charge of the plasma trapped in the gate oxide film can be quickly passed by the protection diode of the prior art during the plasma process. Therefore, the present invention has an effect that the yield and reliability of the device can be greatly improved because the applied charges are discharged at high speed even if any component of positive or negative charge is applied during the plasma process.

1 is a circuit diagram showing a semiconductor device of an embodiment having a protection diode according to the prior art;

FIG. 2 is a layout diagram of a semiconductor device having the protection diode shown in FIG.

3 is a vertical cross-sectional view taken along line AA ′ of FIG. 2.

4 is a vertical cross-sectional view taken along line B-B 'of FIG. 2;

FIG. 5 is a vertical cross-sectional view of the semiconductor device taken along the line CC ′ in FIG. 2. FIG.

FIG. 6 is a circuit diagram of an embodiment of a semiconductor device having a protection diode according to the present invention; FIG.

FIG. 7 is a layout diagram of a semiconductor device having the protection diode shown in FIG. 6. FIG.

FIG. 8 is a vertical cross-sectional view of the semiconductor device taken along the line AA ′ of FIG. 7; FIG.

FIG. 9 is a vertical cross-sectional view taken along line B-B ′ of FIG. 7.

FIG. 10 is a vertical cross-sectional view taken along the line CC ′ in FIG. 7. FIG.

* Description of the symbols for the main parts of the drawings *

100: silicon substrate 102: P-type well

104: N type well 106: field oxide film

108: gate oxide film 110: polysilicon layer

112: salicide layer 114: spacer

116: drain 118: source

120: N / P diode 122: P / N diode

124: interlayer insulating film 126: metal wiring layer

Claims (4)

A gate electrode formed by embedding an insulating film in an upper portion of the first conductivity type well in which a first conductivity type impurity is ion-implanted into a predetermined region of the semiconductor substrate, and the first conductivity near the surface of the first conductivity type well below the gate electrode edge; A transistor having a source / drain formed by ion implantation of a second conductivity type impurity having conductivity opposite to the type impurity; A first diode spaced apart from the transistor by a field oxide film and implanted with the second conductivity type impurity near a surface in the first conductivity type well; And A second diode in which a first conductivity type impurity is implanted in the vicinity of a surface of the second conductivity type well formed on the semiconductor substrate so as to be adjacent to the first conductivity type well on the semiconductor substrate by the field oxide film; And the gate electrode of the transistor, the first diode, and the second diode are connected by the same wiring layer. The semiconductor device according to claim 1, wherein the first conductivity type is P type and the second conductivity type is N type. The semiconductor device according to claim 1, wherein the first conductivity type is N type and the second conductivity type is P type. Ion-implanting a first conductivity type impurity and a second conductivity type impurity having conductivity opposite to each other in a region adjacent to the semiconductor substrate to a predetermined depth to form a first conductivity type well and a second conductivity type well, respectively; Forming an isolation region for isolation between devices in the semiconductor substrate on which the first conductivity well and the second conductivity well are formed; Forming an insulating film on the first conductivity type well in a region where a gate electrode is to be formed; Forming a gate electrode formed of a conductive layer on the insulating film; The second conductivity type impurities are implanted at a high concentration near the surface of the first conductivity type well to self-align the gate electrode edges to form a source / drain, and at the same time, the first distance is spaced apart from the gate electrode. Forming a transistor and a first diode in the first conductivity type well separated by the device isolation region by implanting a second conductivity type impurity in a high concentration near the surface of the conductivity type well; Forming a second diode by ion implanting the first conductivity type impurity at a high concentration near the surface of the second conductivity type well; Forming a contact hole for selectively removing and exposing the interlayer insulating layer formed on the gate electrode, the first diode, and the second diode after forming the interlayer insulating layer on the entire surface of the resultant; And And forming and patterning a conductive metal layer on the resultant to connect the gate electrode, the first diode, and the second diode to a metal wiring layer.

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