KR100473220B1 - Rom-based finite impulse response filter for use in mobile telephone - Google Patents

Abstract

A finite impulse response (FIR) filter 20 is implemented in the table 104 using ROM. The FIR filter table stores precomputed output filter values for each possible combination of input values 102 to be filtered. The stream of input values is continuously shifted in to the table using the shift register 106 and the corresponding output values are successively output. The phone uses a data burst randomizer 18 to provide a data signal consisting of a sequence of null or zero values and a sequence of opposite polarities (+1 and -1). Accordingly, an acceptable combination of inputs for the FIR filter includes either a signal of all opposite polarities, all null signals, a preceding opposite polarity signal followed by a trailing null signal or a preceding null signal followed by a trailing opposite polarity signal. Only patterns that are included. The FIR filter lookup table is configured to use this constraint on the input stream to form a lookup table with a relatively small entry.

Description

ROM-Based FINITE IMPULSE RESPONSE FILTER FOR USE IN MOBILE TELEPHONE}

FIELD OF THE INVENTION The present invention relates to mobile phones, and more particularly to finite impulse response (FIR) filters for use in cellular telephones using code division multiple access (CDMA) transmission techniques.

1 illustrates a block diagram of a variable rate CDMA transmission system disclosed in the Telecommunications Industry Association's Interim Standard (TIA / EIA / IS-95-A) Mobile Station-Base Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellular System. . Data for transmission by the transmission system 10 is provided by a data source 12 of variable speed. In an embodiment, the variable rate data source is a variable rate vocoder used for variable encoding of speech signals as disclosed in US Pat. No. 5,414,796, which is incorporated herein by reference.

In an embodiment, the variable rate transmission system 10 transmits data in frames in accordance with TIA / EIA IS-95-A. Variable rate data source 12 receives a digitized sample of the input speech and encodes the speech to provide a packet of encoded speech as shown in FIGS. 3A-3D. The output of the variable speed data source 12 is an information bit as shown in FIGS. 3A-3D. In an embodiment, the variable speed data source 12 transmits at four possible speeds (9600 bps, 4800 bps, 2400 bps, and 1200 bps), referred to herein as full, 1/2, 1/4, and 1/8 speeds. Provides a variable rate data packet for Speech samples encoded at full speed contain 172 information bits, samples encoded at half speed have 80 information bits, samples encoded at 1/4 speed have 40 information bits, and 1/8 speed The sample encoded by contains 16 information bits.

Referring to FIG. 1, in an embodiment, a variable rate packet is provided to a packetizer 13 that optionally adds cyclic redundancy check (CRC) bits and tail bits in an embodiment. As shown in FIG. 3A, when a frame is encoded at full speed by a variable rate data source 12, the packetizer 13 generates and adds 12 CRC bits and 8 tail bits. Similarly, as shown in FIG. 3B, when a frame is encoded by a variable speed data source 12 at half speed, the packetizer 13 generates and appends eight CRC bits and eight tail bits. do. As shown in FIG. 3C, when a frame is encoded at a quarter rate by a variable rate data source 12, the packetizer 13 generates and adds eight tail bits. As shown in FIG. 3D, when a frame is encoded at a rate of 1/8 by a variable rate data source 12, the packetizer 13 generates and adds 8 tail bits.

Variable speed packets from the packetizer 13 are provided to the encoder 14. Encoder 14 encodes the bits of the variable rate packet for error detection and error correction purposes. In an embodiment, the encoder 14 is a convolutional encoder of 1/3 speed. Convolutional encoded symbols are applied to the iteration generator 17.

In an embodiment the iteration generator 17 receives a packet. For packets below the full rate, the iteration generator 17 duplicates the symbols in the packet to provide packets of a constant data rate. When the packet of variable rate is half speed, the repetition generator 17 introduces twice the redundancy, ie each symbol is repeated twice in the output packet. When the packet of variable rate is quarter rate, the repetition generator 17 introduces four times the redundancy. When the variable packet is at 1/8 speed, the repetition generator 17 introduces eight times redundancy.

In an embodiment, encoded symbols are provided to a CDMA spreader 16, the implementation of which is described in detail in US Pat. Nos. 5,103,459 and 4,901,307, which are incorporated herein by reference. In an embodiment, the CDMA spreader 16 maps six encoded symbols to 64-bit Walsh symbols and spreads Walsh symbols according to a pseudo noise (PN) code.

In an embodiment, the iteration generator 17 provides redundancy by dividing the data packet into small subpackets called " power control groups. &Quot; In an embodiment, each power control group consists of six Walsh symbols. Frames of a constant rate are generated by successively repeating each power group as many times as necessary to fill the frame as described above.

The packet is then data that removes redundancy from the packet in accordance with a pseudorandom process, as disclosed in co-pending US patent application Ser. No. 08 / 291,231, filed August 16, 1994, which is incorporated herein by reference. To a burst randomizer 18. The data burst randomizer 18 selects one of the power control groups for transmission according to the pseudo random number selection process and gates another redundant copy of the power control group.

Thus, the output of the data burst randomizer 18 consists of a sequence of gated values with zero values enclosing an ungated antipodal data sequence with values of +1 and -1. . 4 shows a representative transmission signal portion having a long null portion of zero value surrounded by portions of opposite polarities at +1 and -1.

The packet is provided to the finite impulse response (FIR) filter 20 by the spreader 16. The operation of the FIR filter can be generally expressed by Equation 1 below.

In a preferred embodiment, the FIR filter 20 is a four-fold oversampled 48-tap FIR filter 20 shown in FIG. As shown in Figure 2, each sample is delayed by about a quarter of the input sequence period. Thus, there is four times redundancy in the data stream.

The filtered signal is provided to a digital-to-analog converter 22 (DA converter) and converted into an analog signal. The analog signal is provided to a transmitter 24 that upconverts and amplifies the signal for transmission through the antenna 26.

In general, the FIR filter 20 is implemented with a digital signal processor or specially designed hardware programmed to perform the numerical calculation of equation (1). However, for portable cellular phones, the power required to drive a processor or specialized hardware is unacceptably high. Thus, a more efficient means of implementing FIR filters is needed.

1 is a block diagram of a transmitter of a digital cellular telephone including a FIR filter, which is an object of the present invention.

2 is a block diagram for a 4-fold oversampled FIR of 48 taps.

3A-3D show the frame format of an embodiment.

4 is a timing diagram illustrating a digital signal including both a null portion and a portion of opposite polarity filtered by the FIR filter of FIG. 1.

FIG. 5 is a block diagram illustrating the arrangement of the FIR filter of FIG. 1.

6 is a block diagram of an embodiment for use in a digital cellular telephone using CDMA transmission technology, in accordance with the present invention.

A more efficient way to implement the FIR filter 20 is to use a ROM based lookup in which the data value of the delay element is used to select a precalculated output value. Although the operation has been described using a ROM, it should be noted that other logical combination elements may be used to generate the output as described in the embodiment using the ROM element. To implement a 4-fold oversampled 48-tap FIR filter into a lookup table, one method is to map all possible combinations of 0, +1, and -1 chips to 48 tap positions. This requires a ROM table with 3 ⁴⁸ values. By taking advantage of the fact that only 12 values contribute to the determination of the output value, using four times oversampling (four samples are output for each chip input), the table is a table with 3 ¹² different entries. Although it may be reduced, this is still not practical for many applications, although it represents a clear improvement.

The first way to reduce the size of the lookup table is to implement the lookup table in two parts. Finding the output from the 12 values of x (n) through x (n-11) first finds the contribution from x (n) to x (n-5) and then at x (n-6) This can be achieved by finding the contribution up to x (n-11). FIR filtering is a linear operation. Accordingly, the output of the filter can be found simply by adding two contributions.

In an embodiment, the FIR filter is symmetrical. Accordingly, filter coefficients for determining contributions to x (n) through x (n-5) can also be used to determine contributions to x (n-6) through x (n-11). This can also reduce the number of required elements in the lookup table by 3 ⁶ .

Another way to reduce the size of the lookup table is to take advantage of the fact that there are only a limited number of cases where zero is generated in the data stream as a result of the data burst randomizer operation. As mentioned above, the data burst randomizer is operative to produce a signal having a sequence of bits (+1 and -1) of opposite polarities all surrounded by a sequence of zeros. Thus, if there is zero in the data stream input to the filter, then all bits in the filter will be zero or the stream of zeros will be entered or live (fetched or fetched). No other combination of values of opposite polarity and zero is allowed. All possible allowable input bit patterns are shown in Table 1.

Table 1

The first row of the table represents 64 possible combinations of ungated power control groups, i.e. the power control group consists only of +1 and -1 of opposite polarities. The seventh row of the table represents just one entry required for a fully gated power control group masked to provide all zeros. The remaining rows of the table represent chip patterns associated with a stream of chips having gated power control groups that are shifted in (shifted input) or shifted out (shifted output).

The total number of entries required to implement Table 1 as determined by adding the number of outputs written to Table 1 is only 189. This is considerably smaller than the 3 ¹² entries required if the lookup table does not use the constraints provided by the FIR filter linearity or data burst randomizer.

According to one aspect of the invention, an FIR filter arrangement is provided for use in filtering an input signal stream consisting of a signal sequence of opposite polarity surrounded by a sequence of null signals. The filter device comprises means for storing a lookup table comprising FIR filter output values for each of a predetermined set of allowable unique input bit stream patterns and a sequence of output values corresponding to the filtered version of the input stream. Means for continuously providing a portion of the input digital signal stream to means for storing the table for output. As a result of the input signal stream configuration, a set of allowable input patterns may be a leading antipodal signal or trailing, followed by a signal of all opposite polarities, all null signals, trailing null signals, or both. Contains only a pattern comprising one of the preceding null signals followed by a trailing antipodal signal.

In a particular implementation, the apparatus is used in digital cellular telephones configured for encoding and transmitting signals in accordance with the CDMA protocol. The means for storing the filter response table is a ROM. Input to the filter forms an address for the ROM. The output of the ROM thus provides a partial FIR filter response to the input. In an embodiment, the individual in-phase and FIR values of the 90 degree phase difference are stored.

In an embodiment, the FIR filter is oversampled four times. When a data value is introduced into the FIR filter, the data is applied to the first tap. The input value then proceeds to be applied four times to tap values with different phase coefficients. Applying each data value to the first tap of the filter may be referred to as the filter phase. In an embodiment, the ROM filter table is subdivided into four separate sub-tables corresponding to each of four possible filter phases. The output value of the FIR filter table is predetermined to emulate a FIR filter oversampled 4 times 48 taps. In this regard, the output value is precomputed from a set of 48 coefficient values, each set of 12 coefficient values being used to generate an output value of the corresponding four phases of the table.

In a possible implementation, each of the four sub tables for each in-phase and 90 degree phase difference table stores 189 entries for a total of 756 entries per table. However, for the described implementation, the total number of entries per table is only 378. This additional reduction in table size is achieved by using the linearity of the filter. In another implementation, the table size may be reduced to 128 entries. A wide variety of other embodiments may be provided without contradicting the principles of the invention.

The above techniques of the present invention can be easily understood in view of the following detailed description with reference to the drawings.

With reference to the other figures, embodiments of the present invention are described. Embodiments are first described with reference to block diagrams illustrating elements of the apparatus. Depending on the embodiment, each device element and part thereof is composed of hardware, software, firmware or a combination thereof. Not all the elements necessary to fully implement the actual system are shown and are not described in detail. Only the parts necessary for understanding the present invention are illustrated and described.

The FIR filter table of the present invention is generally described with reference to FIG. Particular implementations of the invention will be described with reference to FIG. 6.

5 illustrates a FIR filter ROM 100 for use as the filter 20 of the transmission system of FIG. 1 or for use in other predetermined filtering applications consistent with the principles of the present invention. FIR filter ROM 100 stores a single FIR filter output value for each allowable unique input pattern. As noted above, in an embodiment the FIR filter has a preceding opposite polarity where the input string received by the filter is all followed by values of opposite polarity (+1 and -1), both null values (0) and trailing null signals. A string of null values (0) and a string of opposite polarities (+1 and -1) such that the signal of or the trailing opposite polarity signal is confined to the stream containing one of the preceding null signals. Process the signal. Thus, if all possible combinations of the value of the opposite polarity and the null value are allowed, then the number of allowable combinations of the input string will be significantly smaller than what would otherwise be required.

Some contents of the ROM 100a of FIG. 6 are shown in Tables 3 and 4. FIG. "+" In the table corresponds to +1. "-" In the table corresponds to -1. 0 in the table represents a gated input value of zero. ROM 100a and ROM 100b are shown in detail as ROM 100 in FIG. ROM 100a stores the information provided in Tables 3 and 4. Tables 3 and 4 provide output information for the first filter phase of the four filter phases. In addition, ROM 100a stores the required information for the remaining three phases not provided in Tables 3 and 4. The information needed to fill the ROM 100a for the remaining three phases can be calculated from the information provided in Table 2. Similarly, all four phases for ROM 100b can be calculated from the information provided in Table 2.

The FIR filter of the present invention operates using a system clock operating at eight times the PN chip speed.

In FIG. 5, the allowable streams of +1 and -1 in the table are the same as the address or tag values 102, and the corresponding FIR filter output values are identified by quotation marks 104. In order to allow the table to distinguish ungated input streams from partially or fully gated input streams, separate sub-tables (not shown in FIG. 5) are provided. An implementation with separate subtables is described with reference to FIG. 6.

The shift register 106 is used to incrementally shift the input sample stream of the FIR filter ROM 100 so that a value corresponding to the input stream provided in substantially parallel to the address tag value identifies the corresponding output filter value. Do it. Since the FIR filter table contains a combination of all allowable input streams, the corresponding filtered output values can thus be included and read out somewhat in the table. By simply reading the precalculated output filter values rather than directly calculating the output values commonly used in conventional FIR filters, significant power consumption can be saved. In addition, the filter value can be easily modified, for example, to provide different FIR filter coefficients.

The FIR filter outputs one output value per stream position and increments the stream position every one stream point. Accordingly, the output value is generated at the same frequency as the sample value of the input signal. Thus, if the input signal is sampled at 4 samples per chip, the output signal of the FIR filter will similarly have 4 samples per chip filtered. In general, the input signal may be sampled as often as required to generate a predetermined selected number of output samples per chip. In some implementations, the input signal is sampled only twice per chip.

In order to allow the output signal to have multiple samples per chip to provide a similar analog representation of the filtered chip suitable for processing by the DA converter (of FIG. 1), the FIR filter ROM 100 provides four per input stream. Generate an output value. This is accomplished by subdividing the FIR filter ROM 100 into four separate tables corresponding to four separate phases of the filter. To provide a clear idea of the operation of the present invention, the FIR filter ROM 100 of FIG. 5 is only one output value per stream of input sample values shifted by the shift register 106 to the FIR filter ROM 100. Only shown as a single phase filter providing.

The sequence of sample stream chips is applied to various sequences of address value bits until matching is achieved, with the corresponding filter output values read out for subsequent processing. Thus, one value is output corresponding to the entire stream of input values. The stream of input values is defined by a sliding window and the window is incrementally transformed with respect to the input signal such that incrementally different streams are applied to the table to form a correspondingly filtered sequence of different output values. do. Accordingly, if the window initially selects samples (N through N + 11) to generate a first filter output value, the window selects samples (N + 1 through N + 12) to generate a second output value. Is repeated.

In this way, the entire input signal is incrementally filtered to produce an output value sequence with one output value per window position. At the beginning or end of the input stream where the window exceeds the input stream, a zero sample value or some default value may be padded to the actual sample value to provide a complete stream.

The output value is represented digitally with a certain desired degree of accuracy, using a plurality of bit representations. For example, the output value can be represented using 8 bits, 11 bits, and the like. The accuracy required for the output value to be expressed may be limited in part by the nature of the input signal and the number of samples per stream. In an exemplary implementation, an 11 bit representation of the output filter value is used.

With reference to FIG. 6, an embodiment of a particular implementation of the FIR filter used in the system of FIG. 1 is described. First, an overview of the operation of the FIR filter can be provided with reference to the basic components of the filter. Various internal components of the filter will be provided below in more detail.

The FIR filter of FIG. 6 provides a separate in-phase filtering component 402 and a 90 degree phase filtering component 404. Each component produces four output values for each stream of twelve input chips. As such, the two components represent a four-phase filter. Two separate FIR filter ROM tables 100a and 100b are shown. Each table contains four sub-tables (not shown separately) corresponding to each of the four phases. The output values stored in the table are generated to emulate 48 coefficient filters with 12 coefficients associated with each phase. During the odd clock cycle, the input streams of the first six chips are applied to the FIR filter ROM tables 100a and 100b to produce four output values, with one output value per phase of the four phase clock period. During the even clock cycle, the remaining six chips are applied in reverse order to the FIR filter ROM tables 100a and 100b to produce the other four output values, with one output value per phase of the clock signal. Thus, for every two clock cycles, two output values per input cycle are generated by the ROMs 100a and 100b. The two output values are added to produce a single output value of the FIR filter per phase every two clock cycles for output on output line 406.

The in-phase (I) filter ROM 100a and the 90 degree phase difference (Q) filter ROM 100b are implemented slightly differently. The I-filter is an even symmetric 48 tap filter that causes the peak of the resulting impulse response to fall between h (23) and h (24) for the coefficients h (0) to h (47). However, the Q-filter is an odd symmetric 47-tap filter in which the peak of the impulse response drops at h (23) for a filter having coefficients h (0) to h (46). Therefore, the Q filter has 47 coefficient values rather than only 48 coefficient values, and cannot be divided equally into 4 like the I filter. Considering this difference, for a Q filter, the phase 0 output is the sum of 11 coefficients, while the other three phase outputs are each the sum of 12 coefficients.

In order to handle this exception and take advantage of the symmetry feature, the ROM filter's ROM values are stored up to half the weight-center tap contribution h (23). In phase 0, Q filter ROM 100b uses input chip 6:11 as the address for the first access rather than using input chip 5: 0 in the first access and input chip 6: 1 in the second access. It is read using chip 6:11 at 2 access. In practice, this counts the half weighted center tap coefficient twice and applies the center coefficient to its entire weighting. The odd symmetric Q filter ROM 100b also requires simple page mapping to track additional details; One coefficient of phase of the first half is symmetrical with respect to three coefficients of phase of the second half, and vice versa.

Coefficients according to the TIA / EIA / IS95-A Mobile station-Base Station Compatibility Standard for Dual-Mode Wideband Spread Spectrum Cellular System for in-phase and 90-degree phase filter coefficients are provided in Table 2.

Table 2

Since the FIR filter is a linear system, this is expressed by the following equation.

y (-x) =-y (x)

Where y (x) is the output of the filter given to input (x).

64 entries for the in-phase ROM 100a are developed in Table 3. In an embodiment, only half of the entries in Table 3 set forth below are ROM 100 since the output value for the "negative" input is derived by appending a negative sign to the output value from the corresponding "positive" input. Are stored in). The 64 entries correspond to an ungated input chip strip, i.e. the chip stream only has values of opposite polarity. Within the table, the values of the opposite polarities of the ungated signals are represented as + and-.

Table 4 provides entries for partially gated chip streams and fully gated chip streams. Within the table, gated inputs that are shifted in are provided in the two columns on the left. The gated value shifted out is provided in the two columns on the right. Also within the table, "0" represents a gated or null value. As shown, the gated value becomes either a preceding value or a trailing value depending on whether the gated value is shifted in or out of the FIR filter. The last entry in the table, all with "0", represents a fully gated chip stream. Referring to Table 1, there are a total of 189 possible combinations that may occupy a filter of the first six taps or the second six taps. If four possible phase filters are provided, then 756 possible combinations are required. However, as mentioned above, this number of entries can be halved by using the linearity of the FIR filter so that only output values for "positive" input values need to be provided. Thus, the total number of entries in the FIR filter ROM tables 100a and 100b is reduced to 378. In the filter, + and-can be represented digitally by any suitable symbol.

Table 3

Table 4

The output values shown in Tables 3 and 4 are derived from the coefficient values in Table 2. For example, consider an input chip having a first six chips (+1, -1, +1, -1, +1, -1 or +-+-+-). For phase 0 this is h (0) -h (4) + h (8) -h (12) _h (16) -h (20) or (-12)-(+ 10) + (17)-(+ 4) + (-6)-(+ 44) or -59, the value corresponds to the "+-+-+-" input address combination in Table 3. Note that the output for the complementary input "-+-+-+" is +59. Thus only one value is required to be stored for each pair of complementary input values. The MSB (most significant bit) of each stream of six input values is used to determine whether the input stream should be inverted. If MSB is -1, the input address is inverted and the output value is inverted. If the MSB is +1 no inversion is required. Although shown separately here, each table is also provided for a 90 degree phase difference. The value for use in the table of 90 degree phase difference is derived from the 90 degree phase value of Table 2.

The manner in which the above-described features are implemented will be described with reference to the block diagram of FIG. 6. 6 shows a FIR filter unit 400 having an in-phase portion 402 and a 90 degree phase portion 404. The outputs of the two parts are combined on a single output signal path by multiplexer 408 for continuous conversion into an analog signal for transmission. A power control group consisting entirely of +1 and -1 is received along input line 410. The DBR gating value of G or NG is input along DBR line 412. DBR gating values are received for each chip in the input power control group. If the gating value is G then the power control group is gated and the corresponding chip is considered to be zero. If the DBR gating value is NG, the chip value is not gated and maintains its input value of +1 or -1.

In-phase components are described. The stream of input chip received along line 410 is first combined with the I-PN and U-PN signals for performing spreading, so that the resulting spreading signal is shifted in using shift register 411.

Shift register 411 outputs 12 bits in parallel along respective lines 414 and 416. Line 414 accepts bit 5: 0 while line 416 transmits bit 6:11. As a result, the first six bits are reversed. This helps to use the symmetry of the filters summarized above. The multiplexer 418 selects among the lower six bits or the upper six bits depending on the value of the radix clock signal received along line 420. If the clock is odd, the lower bit is selected; if the clock is good, the upper bit is selected. The MSB of the selected bit is divided on line 422 for use in controlling XOR gate pairs 424 and 426.

The lower five LSBs are routed directly to the XOR gate 424. If the MSB is zero, the remaining 5 bits are inverted to form its complement to use the linear feature summarized above. The resulting 5 bits are routed to DBR gate address mask unit 426, which also receives the G or NG bits from the 12 tap DBR shift register connected to input line 412. The DBR gate address mask matches the G and NG signals from shift register 428 with the corresponding bits of the input chip signal received from gate 424. The DBR gate address mask also receives a filter phase signal along input line 432 to select a suitable phase.

Although not individually shown in FIG. 6, I-FIR ROM 100a is comprised of four separate table parts corresponding to four separate phases. To generate the bonded address from the I-FIR ROM 100a to select the correct corresponding filter value, the DBR gate address mask adds +1 and -1 chip signals for each phase to the corresponding G and NG of the DBR signal. To a value. The actual format of the address depends on how data is stored in ROM 100a. Suitable addresses are described with reference to Table 4.

Thus, the address generated by the DBR gate address mask uniquely identifies an entry in ROM 100. In order to uniquely address each entry, a total of nine address bits are used. The nine bit address is generated from the six ternary input values of the filter.

A 9 bit address is applied to the ROM table 100a to produce one unique output value that is represented digitally using 11 bits. Eleven bits of the output value are applied to the second XOR gate 426 for inversion when the original MSB is zero. The resulting value is stored in latch 428 for subsequent combination with the output value corresponding to the upper six bits of the input chip stream. During the next 11 consecutive clock cycles, the upper six bits are processed in the same manner as the lower six bits to produce a second output value. The first output value stored in the latch 428 is combined by the addition gate 434 with the second output value to generate a digital signal for the output. After the two least significant bits of the digital signal are truncated, the signal is applied to multiplexer 408 for continuous output on line 406 with the output value from the 90 degree phase difference portion of the filter.

Thus, to briefly summarize the operation of the in-phase portion, during each odd clock in the chip, four values are output from I-ROM 100a corresponding to four filter phases. Four output values are stored in latch 433, respectively. During the next 11 clocks, four additional values are output from I-ROM 100a corresponding to four phases. The first set of values generated during the odd clock is based on the lower six bits of the input chip stream. The second value generated during the even clock is based on the upper six bits of the input chip stream. The first and second pairs of values are added to produce a total of four output values per clock signal pair. For other implementations, it is also desirable to generate all four output values within each clock period. This is achieved, for example, by doubling the size of I-ROM 100a, thus eliminating the need to calculate the upper and lower output values separately.

The operation for the portion of the 90 degree phase difference is similar to that of the in-phase portion, and only relevant differences are described. The 90 degree phase difference portion includes a shift register 462 that outputs the bits in parallel along the three separate lines 464, 465, 466 to the multiplexer 468. Thus, unlike the multiplexer 418 of the in-phase portion that receives only two inputs corresponding to the 5: 0 and 6:11 input bits, the multiplexer 468 corresponds to the 5: 0, 6: 1, 6:11 bits. Receive three different inputs. This is provided to accommodate some asymmetry in the filter coefficients of the 90 degree phases summarized above. The multiplexer 468 selects a signal from one of three input lines based on the odd clock signal 420 and the filter phase signal 432. For the first filter phase, bit 6: 1 is selected during the odd clock and bit 6: 11 is selected during the even clock. For the other three phases, it is selected between 5: 0 and 6:11 bits as described above with reference to the in-phase portion.

Six bits selected by the multiplexer are routed to the XOR gate 474 and the MSB is routed along line 472. The XOR gate inverts the bits depending on the MSB and routes the resulting bits to a DBR gate address mask 475 that operates in the same manner as the mask 426 in phase. A 9-bit address is applied to the Q-FIR ROM 100b, the output of which 100b is routed to the latch 482 via the second XOR gate 476. The value latched during the odd clock is combined with the output value from ROM 100b during the even clock to produce the final output signal for transmission on output line 406 through multiplexer 408.

In an alternative arrangement, instead of storing both DBR gated and ungated output values in ROM tables 100a and 100b, only ungated output values are stored. The output value for the DBR gated input value is calculated from the output value corresponding to the ungated input value by adding two consecutive accesses to the ROM tables 100a and 100b. The first access uses an ungated or " unmasked " filter input as an address and the second access uses an input having an inverted DBR gated chip compared to the address of the first access. Adding the resulting two output values from each other has the final effect of eliminating the DBR gated chip input. The added output value is shifted by bit position, and reduced by half to cancel the inherently double scaling that occurs as a result of the addition of the two output values.

In this alternative implementation, the ROM word width is two result widths because two read values from the ROM 100 are required for each 1/2 filter output; Requires twice the bits accessed per requested output. The two phases are added in parallel to maintain the same FIR filter output rate. As such, the ROM 100 is somewhat more complicated than the ROM of the embodiment described above. However, the ROM 100 of an alternative embodiment stores only 128 unmasked values, arranged at twice 64 words wide of the words of FIG. 6, and about 1 of the ROM 100 including the DBR gated values. Make it / 3 size.

The above are implementations of FIR filters configured as tables. A particular implementation is described with reference to a digital cellular telephone using CDMA transmission technology in accordance with the IS-95-A protocol, in which the number of entries required in the FIR table is defined using the unique characteristics of the filtered signal.

It should be noted that additional power savings can be achieved by not accessing the ROM 100 when the input sequence is all zero. When using variable speed data, this saves considerable time.

The foregoing description of the embodiments has been disclosed to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and it will also be apparent that the general principles defined herein may be applied to other embodiments without using technical capabilities. Thus, the present invention is not limited to the embodiments set forth in the specification but is intended to be broad in scope consistent with the disclosed principles and novel features.

Claims (39)

A finite impulse response (FIR) filter device, Means for receiving an input signal stream having a group of consecutive null signals bracketed by a group of consecutive null signals; Means for storing FIR filter output values, said storage means storing only FIR filter output values for each predetermined set of unique allowable input stream patterns, the set of allowable input stream patterns being preceded by a trailing null signal Means for storing FIR filter output values including only patterns comprising one of signals, preceding null signals followed by trailing null signals, signals that are all null signals, or signals that are all null signals; And Means for continuously applying a series of continuous signals from the input stream to the storage means for reading a series of output values corresponding to the filtered state of at least a portion of the input stream. The FIR filter apparatus of claim 1, wherein the channel signals are signals of opposite polarities. The FIR filter device of claim 1, wherein the storage means comprises a ROM. The FIR filter apparatus according to claim 1, wherein said storage means stores a filter value corresponding to a symmetric FIR filter. 2. The apparatus of claim 1, wherein the allowable input stream patterns each include N signals, and wherein each of the consecutive group of channel signals includes at least N signals; And The series of N signals sequences is applied to the storage means, where N is greater than two. A finite impulse response (FIR) filter device for use in filtering an input signal stream, A receiver for receiving an input signal stream having groups of continuous null signals surrounded by a group of consecutive null signals; A memory unit comprising FIR filter output values, the memory unit storing FIR filter output values for each of a predetermined set of unique allowable input stream patterns, the set of allowable input stream patterns being followed by preceding null signals. A memory unit including only patterns including one of the signal signals, the preceding null signals followed by the trailing signal signals, the signals that are all the null signals, or the signals that are all the null signals; And And an input control unit for continuously applying a series of continuous signals from the input signal stream to a memory unit to read a series of output values corresponding to the filtered state of at least a portion of the input stream. The FIR filter of claim 6, wherein the channel signals are signals of opposite polarities. The FIR filter of claim 6, wherein the memory unit comprises a ROM. The FIR filter of claim 6, wherein the memory unit stores filter values corresponding to a symmetric FIR filter. The method of claim 6, Each of the allowable input stream patterns includes N signals, and the groups of consecutive channel signals each include at least N signals; And A series of N consecutive signals is applied to the memory unit, where N is a number greater than two. A method of filtering an input signal stream, Receiving an input signal stream to be filtered, the input stream having a group of channel signals surrounded by a group of consecutive null signals; And Successively applying a series of consecutive signals from the input signal stream to a memory unit comprising the FIR filter outputs to output a series of output values corresponding to the filtered state of at least one portion of the input stream. The memory unit stores only FIR filter output values for each of the unique permissible input stream patterns, wherein the set of permissible input stream patterns comprises a leading null signal followed by trailing null signals and a leading null signal followed by trailing null signals. And an applying step comprising only patterns comprising one of signals, signals that are all null signals, or signals that are all null signals. 12. The apparatus of claim 11, wherein each of the allowable input stream patterns comprises N signals, and wherein each of the consecutive group of channel signals comprises at least N signals; And A series of N consecutive signals are applied to the memory unit, where N is a number greater than two. A device for converting a digital signal into an analog signal, Means for receiving an input digital signal stream having groups of successive null signals surrounded by successive null signals; Means for storing digital FIR filter output values, said storage means storing only FIR filter output values for each predetermined set of unique allowable input stream patterns, said set of allowable input stream patterns being preceded by trailing null signals. Storage means including only patterns including one of the signal signals, the preceding null signals followed by the trailing signal signals, all of the signal being the null signal, or all of the signals being null signal; Means for continuously applying a series of consecutive signals from the input digital signal stream to the storage means to read a series of digital FIR filter values corresponding to the input stream patterns; And And digital-to-analog conversion means for converting the digital FIR filter values into an analog signal. 14. The apparatus of claim 13, further comprising means for transmitting the analog signal. 15. The apparatus of claim 14, wherein said transmitting means comprises a transmitting unit of a cellular telephone. 14. The apparatus of claim 13, wherein the input digital signal stream is formatted according to a CDMA format. The digital-to-analog converter of claim 13, wherein the storage means comprises a ROM. The method of claim 14, wherein the transmission means, Means for transmitting an in-phase analog signal; And A digital-to-analog converter comprising means for transmitting a quadrature analog signal. 19. The apparatus of claim 18, wherein the input digital signal stream receiving means is Means for receiving a stream corresponding to an in-phase signal; And And means for receiving a stream corresponding to a quadrature signal. The method of claim 19, wherein the storage means, An in-phase memory unit for storing a set of digital values corresponding to an allowable in-phase stream; And And an orthogonal phase memory unit for storing sets of digital values corresponding to an acceptable orthogonal phase stream. The method of claim 13, Means for replicating a portion of the input digital signal stream; And And means for selectively deleting said duplicated portion within a predetermined time period. 22. The apparatus of claim 21, wherein each replica portion of the input digital signal stream comprises a power control group. 22. The apparatus of claim 21, wherein the means for selectively deleting the duplicated portion of the input digital signal stream comprises a data-burst-randomizer (DBR). 15. The apparatus of claim 13, wherein the channel signals are antipodal signals. 15. The apparatus of claim 13, wherein the digital FIR filter output values stored in the storage means are linear, symmetric finite impulse response representations for acceptable input stream patterns. The digital-to-analog converter of claim 13 implemented in an integrated circuit chip. 14. An apparatus as claimed in claim 13, wherein said storage means stores independent values for four independent filter phases. 28. The apparatus of claim 27, wherein the storage means stores a subtotal representing a 12-tap FIR filter using 48 coefficients, wherein each value for each phase is a sum of a product of six binary input values and six coefficients. Digital-to-analog converter. As a method of converting a digital signal into an analog signal, Receiving an input digital signal stream having a group of continuous null signals surrounded by a group of consecutive null signals; Applying a series of consecutive signals from the input digital signal stream to a memory unit comprising digital FIR filter output values to read a series of digital FIR filters corresponding to the input stream patterns, wherein the memory unit is configured to: Including only FIR filter output values for each of a predetermined set of unique allowable input stream patterns, wherein the set of allowable input stream patterns comprises: leading null signals followed by trailing null signals, leading null signals followed by trailing null signals, An applying step including only patterns including one of signals that are all null signals or signals that are all null signals; And Converting the series of digital values into an analog signal. 30. The method of claim 29, further comprising transmitting the analog signal. 30. The method of claim 29 wherein the received digital signals are formatted in accordance with a CDMA format. The method of claim 29, Duplicating a portion of the input digital signal stream; And Selectively deleting some of the duplicated portions within a predetermined time period before successively applying a series of consecutive signals to the memory unit. 33. The method of claim 32 wherein each replicated portion of the input digital signal stream comprises a power control group. 30. The method of claim 29, wherein the channel signals are signals of opposite polarities. A device for converting a digital signal into an analog signal, A receiving unit connected to the input line providing an input digital signal stream having a group of continuous null signals surrounded by a group of consecutive null signals; A memory unit for storing a table comprising digital filter output values, the memory unit storing only FIR filter output values for each predetermined set of unique allowable input stream patterns, the set of allowable input stream patterns being trailing null A memory unit including only patterns including one of preceding null signals followed by signals, leading null signals followed by trailing signal signals, signals that are mode channel signals, or signals that are all null signals; A shift register coupled between the receiving unit and the memory unit, such that the memory unit reads a series of digital FIR filter values corresponding to the input stream patterns, the series of consecutive signals from the input digital signal stream A shift register for applying them to the memory unit; And A digital-to-analog converter coupled to the memory unit, the digital-to-analog converter operative to convert the series of digital FIR filter values into an analog signal. 36. The apparatus of claim 35, wherein the channel signals are signals of opposite polarities. 36. The apparatus of claim 35, wherein the memory unit stores one independent value in four independent filter phases. 38. The digital-analog of claim 37, wherein the memory unit stores a subtotal representing a 12-tap FIR filter using 48 coefficients, wherein each value for each phase represents a product of six binary values and six coefficients. Converter. 36. The method of claim 35 wherein Each of the allowable input stream patterns includes N signals, and a group of consecutive channel signals includes at least N signals; And N series of consecutive signals are applied to said storage means, where N is a number greater than two.