KR100467368B1 - Semiconductor memory device for reducing package test time - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a package and test technology for a semiconductor memory device, and an object thereof is to provide a semiconductor memory device and a package test method thereof capable of reducing package test time. The present invention can reduce package test time by implementing the remaining product family as an internal option in addition to the product family determined by wire bonding. For this purpose, a buffer control signal is used to control the output of the buffer buffering the signal applied to the package option pad. The buffer control signal can be generated by the mode register set control circuit. The buffer controlled by the buffer control signal outputs a signal corresponding to the bonding state of the package option pad in the normal mode, and a signal from the package option pad in the test mode. Blocks the path of and outputs the signal corresponding to the higher bandwidth package option.

Description

Semiconductor memory device for reducing package test time

TECHNICAL FIELD The present invention relates to semiconductor memories, and more particularly, to packaging and testing techniques for semiconductor memory devices.

The main issue in the recent semiconductor memory field is changing from integration to operating speed. As a result, high-speed synchronous memories such as double data rate syncghronous DRAM (DDR SDRAM) and RAMBUS DRAM are emerging as a new topic in the semiconductor memory field.

Synchronous memory refers to a memory that operates in synchronization with an external system clock. Among the DRAMs, SDRAM is the mainstream of the mass production memory market. The SDRAM performs one data access every clock by synchronizing input / output operations to the rising edge of the clock. In contrast, a high-speed synchronous memory such as DDR SDRAM has a feature in which input / output operations are synchronized not only on the rising edge of the clock but also on the falling edge, so that two data accesses are possible every clock.

Currently produced DRAM products have a bandwidth of X4 / X8 / X16. That is, the bandwidth of the product is determined according to the request of the orderer, and each has a unique pin arrangement and wiring according to the bandwidth.

Figure 1 shows the pinout of a typical X4 and X16 SDRAM (54 pins).

Referring to FIG. 1, in the case of the X16 SDRAM, the data input / output pins DQ0 to DQ15, the address pins A0 to A12, the bank address pins BA0 and BA1, and the power supply pins VDD, VSS, VDDQ, VSSQ), data mask pins (LDQM, UDQM), command pins (/ WE, / CAS, / RAS, / CS), clock pins (CK), clock enable pins (CKE), and the like. Each of these is wire bonded with a pad PAD in a die through a lead frame. In the case of X16 SDRAM, all 16 DQ pins are used, and only one of the 54 pins remains unconnected (NC).

On the other hand, since X4 SDRAM uses only four DQ pins (DQ0, DQ1, DQ2, and DQ3), 12 DQ pins that are wire-bonded in X16 SDRAM remain unconnected (NC), and data mask pins. Among the (LDQM and UDQM), the lower data mask pin LDQM remains in the non-connected state (NC), and thus 14 pins out of 54 pins remain in the non-connected state (NC).

For reference, since the data mask signal is controlled in units of bytes, one data mask pin DQM is used in X4 or X8, and two data mask pins LDQM and UDQM are used in X16.

Figure 2 shows the pinout of a typical X4, X8 and X16 DDR SDRAM (66 pins).

Referring to FIG. 2, in DDR SDRAM, data strobe pins (LDQS, UDQS, and DQS), reference voltage pins (VREF), and sub clock pins (/ CK), which are not used in the SDRAM, are larger than the SDRAM. No different. In other words, 16 DQ pins are used for X16 DDR SDRAM, eight for X8 DDR SDRAM, and four DQ pins for X4 DDR SDRAM.

For reference, two data mask pins (LDM and UDM) are bonded and used in X16 DDR SDRAM, but the lower data mask pin (LDM) is not used in X4 and X8 DDR SDRAM and is in an unconnected state (NC). Only one data mask pin DM is used. In addition, two data strobe pins (LDQS and UDQS) are bonded and used in the X16 DDR SDRAM, but the lower strobe pin (LDQS) is not used in the X4 and X8 DDR SDRAM, and the data is disconnected (NC). Only the strobe pin (DQS) is used.

As described above, as shown in FIGS. 1 and 2, all semiconductor memory products have unique pinouts and wirings according to their bandwidths.

On the other hand, as the integration degree of semiconductor memory is rapidly increasing, tens of millions of cells are integrated in one memory chip. As the number of memory cells increases, it takes a long time to test whether they are normal or defective. In these package tests, it is important to consider the accuracy of the test results as well as how quickly the test is performed.

In order to meet the demands in terms of such test time, a parallel test capable of multi-bit access at the same time has been proposed. However, such a parallel test method inevitably degrades the screen ability due to compressing and testing data, and has a disadvantage in that it does not properly reflect relativity due to data path difference or power noise.

Therefore, in order to understand the product characteristics more accurately, it is inevitable to use a non-compression method that takes a long time to test. Hereinafter, a description will be given on the premise of an uncompressed test method.

3 is a wire bonding diagram for each package option according to the prior art.

Referring to FIG. 3, in the case of the X4 product 100, the package option pad PAD X4 101 is wire-bonded with the VDD pin and the other package option pad PAD X8 102 with the VSS pin. The pads that are dark in the figure are wire bonded with the package leads, and the pads that are bright are in the floating state. Meanwhile, in the case of the X8 product 110, the package option pad PAD X4 111 is wire-bonded with the VSS pin and the other package option pad PAD X8 112 is VDD pin. In addition, for the X16 product 120, the package option pads PAD X4 121 and PAD X8 122 are wire bonded with the VSS pins, respectively.

4 is a circuit diagram of a package option signal generation block according to the prior art.

Referring to FIG. 4, VDD or VSS applied to the package option pads PAD X4 and PAD X8 are buffered through the buffer units 130 and 140 formed of two inverters and output as the package option signals sX4 and sX8.

Table 1 below is a package option table showing the operating bandwidth according to the wire bonding.

X4 X8 X16 PAD X4 VDD VSS VSS PAD X8 VSS VDD VSS sX4 H L L sX8 L H L

Referring to Table 1, if the package option signals sX4 and sX8 are logic level high (H) and low (L), respectively, the chip operates as X4, and the package option signals sX4 and sX8 are logic level low (L), respectively. And if the chip is high (H), the chip operates at X8. If the package option signals sX4 and sX8 are both logic level low (L), the chip is operating at X16.

Table 2 below shows the address scramble of a general SDRAM (DDR SDRAM).

Address A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A12 X4 package Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y11 Y12 X8 package Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y11 unused X16 package Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 unused unused

Referring to Table 2, in the case of the X16 package, 10 Y addresses Y0 to A9 are sequentially counted for one word line, and the entire screen may be performed by performing 1024 tests. At this time, 16 data are input / output through the bonded pad. In addition, in the case of the X8 package, 11 Y addresses Y0 to A11 are sequentially counted for one word line, and 2048 tests must be performed to screen the entire screen. Eight data is input and output through the bonded pads, which takes twice the test time of the X16 package. In addition, in the case of the X4 package, 12 Y addresses Y0 to A12 are sequentially counted for one word line, and the entire screen must be performed 4096 times. At this time, four data are inputted / outputted through the bonded pad, which takes four times the test time compared to the X16 package.

In conclusion, depending on the package option, the wiring is taken differently. The smaller the number of bonded DQ pads used for the number of physical DQ pads, the less data is input / output at a time, and thus the overall test time is increased. Different test programs should be configured for each package option.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor memory device and a package test method thereof, which can reduce a package test time.

1 is a pinout diagram of a typical X4 and X16 SDRAM (54 pins).

2 is a pinout diagram of a typical X4, X8 and X16 DDR SDRAM (66 pins).

3 is a wire bonding diagram for each package option according to the prior art.

4 is a circuit diagram of a package option signal generation block according to the prior art.

Figure 5 is an illustration of a wire bonding structure for each package option applied to the present invention.

6 is a block diagram of a package option signal generation circuit in accordance with an embodiment of the present invention.

FIG. 7 is a first exemplary diagram of the package option signal generation circuit of FIG. 6. FIG.

FIG. 8 is a second exemplary diagram of the package option signal generation circuit of FIG. 6. FIG.

9 is a third exemplary diagram of the package option signal generation circuit of FIG. 6.

FIG. 10 is a fourth exemplary diagram of the package option signal generation circuit of FIG. 6. FIG.

FIG. 11 is a fifth exemplary diagram of the package option signal generation circuit of FIG. 6. FIG.

12 is a sixth exemplary diagram of the package option signal generation circuit of FIG. 6.

* Explanation of symbols for the main parts of the drawings

60: Package Option Pad

62: buffer unit

According to an aspect of the present invention for achieving the above technical problem, at least one package option pad bonded to the default package option; Buffer control signal generating means for generating a buffer control signal; And in response to the buffer control signal, buffer a signal applied to the package option pad in a normal mode and output the buffered signal as a package option signal, block a signal applied to the package option pad in a test mode, and remove a signal other than the default package option. There is provided a semiconductor memory device having buffering means for outputting a signal corresponding to a package option as the package option signal.

And, according to another aspect of the invention, the first and second package option pad bonded to the default package option; Buffer control signal generating means for generating a buffer control signal; In response to the buffer control signal, a signal applied to the first package option pad is buffered in the normal mode and output as a first package option signal, and a signal applied to the first package option pad is cut off in the test mode. First buffering means for outputting a signal corresponding to a package option other than a default package option as the first package option signal; And in response to the buffer control signal, buffer a signal applied to the second package option pad in a normal mode and output the buffered signal as a second package option signal, and block a signal applied to the second package option pad in a test mode. There is provided a semiconductor memory device having second buffering means for outputting a signal corresponding to a package option other than the default package option as the second package option signal.

The present invention can reduce package test time by implementing the remaining product family as an internal option in addition to the product family determined by wire bonding. For this purpose, a buffer control signal is used to control the output of the buffer buffering the signal applied to the package option pad. The buffer control signal can be generated by the mode register set control circuit. The buffer controlled by the buffer control signal outputs a signal corresponding to the bonding state of the package option pad in the normal mode, and a signal from the package option pad in the test mode. Blocks the path of and outputs the signal corresponding to the higher bandwidth package option.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

5 is an exemplary view of a wire bonding structure for each package option applied to the present invention.

Referring to FIG. 5, in the case of the X4 product 200, the package option pad PAD X4 201 is wire bonded to the VDD pin and the other package option pad PAD X8 202 is connected to the VSS pin. Meanwhile, in the case of the X8 product 210, the package option pad PAD X4 211 is wire bonded to the VSS pin, and the other package option pad PAD X8 212 is wired to the VDD pin. In addition, for the X16 product 220, the package option pads PAD X4 221 and PAD X8 222 are wire bonded with the VSS pins, respectively.

That is, the configuration and application signal of the package option pad in the wire bonding structure applied to the present invention is not different from the prior art (see FIG. 3). However, in the present invention, whether the X4 product 200 or the X8 product 210 is the same, the wire bonding structure of the X16 product 220 having the maximum bandwidth and the DQ pin is the same. That is, whatever the package option, all DQ pins are wire bonded.

6 is a block diagram of a package option signal generation circuit according to an embodiment of the present invention.

Referring to FIG. 6, the package option signal generation circuit according to the present embodiment may include at least one package option pad 60 bonded with a default package option and a package option pad 60 applied in response to a buffer control signal. A buffer unit 62 is provided to buffer and output a signal, or to block a signal applied to the package option pad 60 and output a signal corresponding to a package option other than the default package option as a package option signal. Here, a package option other than the default package option means a higher bandwidth than the bandwidth of the default package option, and it is preferable to use the maximum bandwidth among the upper bandwidths.

FIG. 7 is a first exemplary diagram of the package option signal generation circuit of FIG. 6.

Referring to FIG. 7, the package option signal generation circuit is applied to the package option pads PAD X4 in normal mode in response to the buffer control signal enX16 and the package option pads PAD X4 and PAD X8 wire-bonded according to the default package options. The first buffer unit 230 for buffering the output signal as a package option signal sX4 and outputting the PAD X4 option signal corresponding to the X16 package having the maximum bandwidth as the package option signal sX4 in the test mode, and the buffer control signal ( In response to enX16), the signal applied to the package option pad PAD X8 is buffered in the normal mode and output as the package option signal sX8, and the PAD X8 option signal corresponding to the X16 package having the maximum bandwidth in the test mode is used as the package option signal sX8. A second buffer unit 240 for outputting is provided. Here, the buffer control signal enX16 is a signal output from the mode register set (MRS) control unit 250, and assumes a high active signal.

Meanwhile, the first buffer unit 230 includes an inverter INV1 for inputting the buffer control signal enX16 and a NAND gate NAND1 for inputting a signal applied to the output of the inverter INV1 and the package option pad PAD X4. And an inverter INV2 for outputting the package option signal sX4 with the output of the NAND gate NAND1 as an input. The second buffer unit 240 is an inverter INV3 that receives the buffer control signal enX16 and a NAND gate NAND2 that receives an output of the inverter INV3 and a signal applied to the package option pad PAD X8. And an inverter INV4 for outputting the package option signal sX8 with the output of the NAND gate NAND2 as an input.

Hereinafter, the operation of the semiconductor memory device having the package option signal generation circuit of FIG. 7 will be described.

First, when the package option pads PAD X4 and PAD X8 are bonded to the VDD pin and the VSS pin, respectively, and packaged as the default X4, in the normal mode, the buffer control signal enX16 is logic level low (L). NAND2) behaves like an inverter for signals applied to package option pads PAD X4 and PAD X8 so that package option signals sX4 and sX8 represent logic level high (H) and low (L), respectively, and eventually the chip is X4. Will work. On the other hand, in the test mode, since the buffer control signal enX16 is enabled at the logic level high (H), the NAND gates NAND1 and NAND2 block the signals applied to the package option pads PAD X4 and PAD X8, and always the logic level high value. Will print Therefore, in the test mode, the package option signals sX4 and sX8 both represent a logic level low (L), so that the chip operates at X16.

Next, when the package option pads PAD X4 and PAD X8 are bonded to the VSS pin and the VDD pin, respectively, and packaged as the default X8, in the normal mode, since the buffer control signal enX16 is a logic level low (L), the NAND gate NAND1 is used. , NAND2) behaves like an inverter for signals applied to package option pads PAD X4 and PAD X8 so that package option signals sX4 and sX8 represent logic level low (L) and high (H), respectively. It will work with X8. On the other hand, in the test mode, since the buffer control signal enX16 is enabled at the logic level high (H), the NAND gates NAND1 and NAND2 block the signals applied to the package option pads PAD X4 and PAD X8, and always the logic level high value. Will print Therefore, in the test mode, the package option signals sX4 and sX8 both represent a logic level low (L), so that the chip operates at X16.

Next, when the package option pads PAD X4 and PAD X8 are both bonded to the VSS pin and packaged as the default X16, the NAND gates NAND1 and NAND2 because the buffer control signal enX16 is logic level low in normal mode. Is operated like an inverter to the signals applied to the package option pads PAD X4 and PAD X8 so that the package option signals sX4 and sX8 both represent a logic level low (L), and the corresponding chip is operated at X16. On the other hand, in the test mode, since the buffer control signal enX16 is enabled at the logic level high (H), the NAND gates NAND1 and NAND2 block the signals applied to the package option pads PAD X4 and PAD X8, and always the logic level high value. Will print Therefore, in the test mode, the package option signals sX4 and sX8 both represent a logic level low (L), so that the chip operates at X16.

Table 3 below is an operation table showing the operating bandwidth in the normal mode and the test mode according to the package option (when using enX16).

Package options X4 X8 X16 X4 X8 X16 Normal mode Test mode (enX16 "H") PAD X4 VDD VSS VSS VDD VSS VSS PAD X8 VSS VDD VSS VSS VDD VSS sX4 H L L L sX8 L H L L Operation bandwidth X4 X8 X16 X16 X16 X16

Referring to Table 3, in the normal mode, the operating bandwidth of the chip is determined according to the bonding states of the package option pads PAD X4 and PAD X8, but in the test mode, the bonding states of the package option pads PAD X4 and PAD X8 are determined. You can see that it works with X16.

Table 4 below shows the address scramble of the SDRAM (DDR SDRAM) in the test mode according to the package option signal generation circuit of FIG.

Address A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A12 X4 package Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 unused unused X8 package Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 unused unused X16 package Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 unused unused

Address scramble in normal mode is shown in Table 2 above.

However, as shown in Table 4, in the test mode, 16 data are input / output through pads bonded to both X4 / X4X16 packages, so that 10 Y addresses Y0 to A9 are sequentially counted for one word line and 1024 Once you run the test, you can screen it all. As a result, the X16, which is currently the largest bandwidth, is no different from the previous test time. However, in the case of the X8 product, it is possible to screen the whole screen with 1024 tests for one word line, which reduces the test time by 1/2 compared to the existing one, and in the case of the X4 product, the test time is 1 compared to the existing one. Can be reduced to / 4.

FIG. 8 is a second exemplary diagram of the package option signal generation circuit of FIG. 6.

Referring to FIG. 8, the illustrated package option signal generation circuit has different configurations of the first and second buffer units 430 and 440 when compared to the circuit of FIG. 7. The first buffer unit 430 inputs an inverter INV5 that receives a signal applied to the package option pad PAD X4, and an output of the buffer control signal enX16 and the inverter INV5 output from the MRS controller 450. A NOR gate NOR1 for outputting the package option signal sX4 is provided. In addition, the second buffer unit 440 outputs the inverter INV6 to which the signal applied to the package option pad PAD X8 is input, the buffer control signal enX16 and the inverter INV6 output from the MRS controller 450. A NOR gate NOR2 for outputting the package option signal sX8 as an input is provided.

As described above, even when the first and second buffer units 430 and 440 are implemented using the Noah gate, the operation table is the same as the circuit of FIG. That is, in the normal mode, since the buffer control signal enX16 is a logic level low L, the NOR gates NOR1 and NOR2 act as inverters, so that the package option signals sX4 and the package option pads PAD X4 and PAD X8 are bonded. sX8 is determined, and in test mode, the buffer control signal enX16 is enabled at logic level high (H) to block the path of the signal applied to the package option pads PAD X4 and PAD X8, and the package option signals sX4 and sX8 are All indicate a logic level low (L), which eventually causes the chip to operate at X16.

9 is a third exemplary diagram of the package option signal generation circuit of FIG. 6.

Referring to FIG. 8, the illustrated package option signal generation circuit illustrates a case in which the MRS controller 550 outputs a buffer control signal enX8 for selecting an X8 option in a test mode. First, the first buffer unit 530 is an inverter INV7 for inputting the buffer control signal enX8 and a NAND gate NAND3 for inputting a signal applied to the output of the inverter INV7 and the package option pad PAD X4. And an inverter INV8 for outputting the package option signal sX4 with the output of the NAND gate NAND3 as an input. The second buffer unit 540 includes an inverter INV9 for inputting a signal applied to the package option pad PAD X8, an inverter INV10 for inputting a buffer control signal enX8, and two inverters INV9, A NAND gate NAND4 for outputting the package option signal sX8 as an input of the output of INV10 is provided.

Assuming that the VDD and VSS pins are bonded to the package option pads PAD X4 and PAD X8, respectively, so that the chip operates at the default X4, in the normal mode, the buffer control signal (enX8) is a logic level low (L). The signals sX4 and sX8 become logic level high (H) and low (L), respectively, so that the chip operates in the X4 package.In the test mode, the buffer control signal (enX8) is logic level high (H), so the package option signal sX4 And sX8 become logic level low (L) and high (H), respectively, so that the chip operates in the X8 package.

Table 5 below is an operation table showing the operating bandwidth in the normal mode and the test mode according to the package option (when using enX8).

Package options X4 X8 X4 X8 Normal mode Test mode (enX8 "H") PAD X4 VDD VSS VDD VSS PAD X8 VSS VDD VSS VDD sX4 H L L sX8 L H H Operation bandwidth X4 X8 X8 X8

Referring to Table 5, in the case of the X4 product, since the entire screen can be screened with 2048 tests for one word line, the test time can be reduced by 1/2 compared to the conventional method. On the other hand, when the buffer control signal enX8 is used as described above, the X16 product is not considered in Table 5 because there is no profit when applied to the X16 product.

FIG. 10 is a fourth exemplary diagram of the package option signal generation circuit of FIG. 6.

Referring to FIG. 8, the illustrated package option signal generation circuit has different configurations of the first and second buffer units 630 and 640 when compared to the circuit of FIG. 9. The first buffer unit 430 inputs an inverter INV11 for inputting a signal applied to the package option pad PAD X4, and an output of the buffer control signal enX8 and the inverter INV11 output from the MRS controller 650. A NOR gate NOR3 for outputting the package option signal sX4 is provided. In addition, the second buffer unit 640 may include a NOR gate NOR4 and a NOR gate NOR4 that receive a signal applied to the package option pad PAD X8 and a buffer control signal enX16 output from the MRS controller 450. An inverter INV12 for outputting the package option signal sX8 as an input of the output is provided.

As described above, even when the first and second buffer units 630 and 640 are implemented using the NOA gate, the operation table is the same as that of the circuit of FIG. 9. That is, in the normal mode, since the buffer control signal enX8 is a logic level low L, the NOR gates NOR1 and NOR2 act as inverters, so that the package option signals sX4 and the package option pads PAD X4 and PAD X8 are bonded. sX8 is determined, and in test mode, the buffer control signal enX8 is enabled at logic level high (H) to block the path of the signal applied to the package option pads PAD X4 and PAD X8, and the package option signals sX4 and sX8 are Representing logic level low (L) and high (L), respectively, the chip eventually operates at X8.

FIG. 11 is a fifth exemplary diagram of the package option signal generation circuit of FIG. 6 and illustrates a case where two buffer control signals enX16 and enX8 are used using the first and second MRS controllers 750 and 760. It is.

Referring to FIG. 11, the first buffer unit 730 may include a NOR gate NOR5 that receives the first and second buffer control signals enX16 and enX8, an output of the NOR gate NOR5, and a package option pad PAD. And a NAND gate NAND5 for inputting a signal applied to X4 and an inverter INV13 for outputting a package option signal sX4 with an output of the NAND gate NAND5. The second buffer unit 740 receives an inverter INV14 for inputting the first buffer control signal enX16, an inverter INV15 for inputting the second buffer control signal enX8, and an inverter INV14. Outputs the package option signal sX8 by inputting the NAND gate NAND6 to which the signal applied to the output and the package option pad PAD X8 is input, and the output of the NAND gate NAND6 and the output of the inverter INV15. And a NAND gate NAND7.

Hereinafter, an operation of the semiconductor memory device having the package option signal generation circuit of FIG. 11 will be described.

First, in the normal mode, since both the first buffer control signal enX16 and the second buffer control signal enX8 are logic level low L, the NAND gates NAND5, NAND6, and NAND7 all operate like an inverter, and thus package options. The signals sX4 and sX8 represent signal levels corresponding to the default bandwidths according to the bonding states of the package option pads PAD X4 and PAD X8, so that the chip operates at the default bandwidth.

Next, in the test mode, the first and second buffer control signals enX16 and enX8 are selectively enabled.

First, when the first buffer control signal enX16 is enabled, since the first buffer control signal enX16 is at logic level high (H) and the second buffer control signal enX8 is at logic level low (L). The NOR gate NOR5 of the first buffer unit 730 outputs a logic level low value, and the NAND gate NAND5 blocks a signal applied to the package option pad PAD X4 and outputs a logic level high value. The value is inverted in the inverter INV13 to output the package option signal sX4 of the logic level low L. Meanwhile, the NAND gate NAND6 of the second buffer unit 740 blocks a signal applied to the package option pad PAD X8 and outputs a logic level high value, and the NAND gate NAND7 inverts the value to the logic level. The package option signal sX4 of row L is output. Thus, the chip will operate at X16 in test mode.

Second, when the second buffer control signal enX8 is enabled, since the first buffer control signal enX16 is a logic level low L and the second buffer control signal enX8 is a logic level high H, The NOR gate NOR5 of the first buffer unit 730 outputs a logic level low value, and the NAND gate NAND5 blocks a signal applied to the package option pad PAD X4 and outputs a logic level high value. The value is inverted in the inverter INV13 to output the package option signal sX4 of the logic level low L. Meanwhile, the NAND gate NAND7 receives a logic level low value through the inverter INV15 and outputs a package option signal sX8 having a logic level high H regardless of another input. Thus, the chip will operate at X8 in test mode.

Table 6 below is an operation table showing the operating bandwidth in the normal mode and the test mode according to the package option (when using enX16 and enX8).

Package options X4 X8 X16 X4 X8 X4 X8 X16 Normal mode (enX8 "L", enX16 "L") Test mode (enX8 "H", enX16 "L") Test mode (enX8 "L", enX16 "H") PAD X4 VDD VSS VSS VDD VSS VDD VSS VSS PAD X8 VSS VDD VSS VSS VDD VSS VDD VSS sX4 H L L L L sX8 L H L H L Operation bandwidth X4 X8 X16 X8 X8 X16 X16 X16

Referring to Table 6 above, in case of the product packaged with the default X4, the test time can be reduced to 1/2 when the package option signal enX8 is enabled, and the test time can be reduced when the package option signal enX16 is enabled. You can see that it can be reduced to 1/4.

FIG. 12 is a sixth exemplary diagram of the package option signal generation circuit of FIG. 6, illustrating a case where two buffer control signals enX16 and enX8 are used using the first and second MRS controllers 850 and 860. It is.

Referring to FIG. 12, the first buffer unit 830 includes an inverter INV16 that receives a signal applied to the package option pad PAD X4, an output of the inverter INV16, and first and second buffer control signals enX16. and a three-input NOR gate NOR6 having an input of enX8. The second buffer unit 840 is an inverter INV17 for inputting a signal applied to the package option pad PAD X8, an output of the inverter INV17, and a NOR gate for inputting the first buffer control signal enX16. The package option signal sX8 is inputted to the NOR7, the output of the NOR gate NOR7, and the output of the NOR gate NOR8 which inputs the second buffer control signal enX8, and the output of the Noah gate NOR8. An inverter INV18 for outputting is provided.

Since the circuit configured as described above operates in the same manner as the circuit illustrated in FIG. 11, a detailed description thereof will be omitted. The operation table is also the same as in Table 6 above.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, in the above-described embodiment, the case in which the X4 / X8 / X16 package option is determined using the X4 PAD and the X8 PAD as the package option pad has been described as an example, but the present invention uses the X4 PAD and X16 PAD as the package option pad. This also applies to X8 PAD and X16 PAD as a package option pad. In this case, the combination of logic gates constituting the buffer unit may vary.

Meanwhile, the NAND gate used in the above-described embodiment may be implemented as an AND gate and an inverter, and the NOA gate may be implemented as an OR gate and an inverter.

The present invention can also be applied to the case where the number of package option pads is added or subtracted according to the number of operating bandwidths.

The present invention described above has the effect of significantly reducing the test time by enabling the test to a bandwidth higher than the bandwidth of the default package, and performs a defect detection using one test program (for maximum bandwidth) regardless of the package option What you can do is a big advantage in terms of test technology.

Claims (20)

At least one package option pad bonded to a default package option; Buffer control signal generating means for generating a buffer control signal; And In response to the buffer control signal, a signal applied to the package option pad in the normal mode is buffered and output as a package option signal, a signal applied to the package option pad in the test mode is blocked, and a package other than the default package option Buffering means for outputting a signal corresponding to an option as said package option signal A semiconductor memory device having a. The method of claim 1, Multiple data input / output pins, And a plurality of wires bonded to each of the data input / output pins. The method according to claim 1 or 2, And a package option other than the default package option uses a bandwidth higher than that of the default package option. The method of claim 3, And package options other than the default package options use a maximum bandwidth. First and second package option pads bonded with default package options; Buffer control signal generating means for generating a buffer control signal; In response to the buffer control signal, a signal applied to the first package option pad is buffered in the normal mode and output as a first package option signal, and a signal applied to the first package option pad is cut off in the test mode. First buffering means for outputting a signal corresponding to a package option other than a default package option as the first package option signal; And In response to the buffer control signal, a signal applied to the second package option pad is buffered in the normal mode and output as a second package option signal, and a signal applied to the second package option pad is cut off in the test mode. Second buffering means for outputting a signal corresponding to a package option other than a default package option as the second package option signal A semiconductor memory device having a. The method of claim 5, Multiple data input / output pins, And a plurality of wires bonded to each of the data input / output pins. The method of claim 6, The first buffering means, First inverting means for inverting the buffer control signal; First negative AND means for negative ANDing the signal applied to the first package option pad and the output of the first inverting means; And And second inversion means for inverting the output of the first negative AND product to output the first package option signal. The method of claim 7, wherein The second buffering means, Third inverting means for inverting the buffer control signal; Second negative AND means for negative ANDing the signal applied to the second package option pad and the output of the third inverting means; And And fourth inversion means for inverting the second negative AND product to output the second package option signal. The method of claim 7, wherein The second buffering means, Third inverting means for inverting a signal applied to the second package option pad; Fourth inverting means for inverting the buffer control signal; And And a second negative AND product for negative ANDing the outputs of the third and fourth inverting means. The method of claim 6, The first buffering means, First inverting means for inverting a signal applied to the first package option pad; And a first negation means for negating the output of the first inversion means and the buffer control signal to output the first package option signal. The method of claim 10, The second buffering means, Second inverting means for inverting a signal applied to the second package option pad; And second negative OR means for negatively ORing the output of the second inverting means and the buffer control signal to output the second package option signal. The method of claim 10, The second buffering means, Second negative AND means for negative ANDing the signal applied to the second package option pad and the buffer control signal; And second inverting means for inverting the output of said second negative AND means to output said second package option signal. The method of claim 6, The first buffering means, First negative OR means for negating the first and second buffer control signals; First negative AND means for negative ANDing the signal applied to said first package option pad and the output of said first negative AND means; And And first inverting means for inverting the output of the first negative AND product and outputting the first package option signal. The method of claim 13, The second buffering means, Second inverting means for inverting the first buffer control signal; Third inverting means for inverting the second buffer control signal; Second negative AND means for negative ANDing the signal applied to the second package option pad and the output of the second inverting means; And And third negated AND means for negatively ANDing the output of the third inverting means and the output of the second negative AND product to output the second package option signal. The method of claim 6, The first buffering means, First inverting means for inverting a signal applied to the first package option pad; And a first negation means for negating the first and second buffer control signals and the output of the first inversion means. The method of claim 15, Second inverting means for inverting a signal applied to the second package option pad; Second negative ANDing means for negative ANDing the output of said second inverting means and said first buffer control signal; Third negative AND means for negative ANDing the output of said second negative AND means and said second buffer control signal; And And third inverting means for inverting the output of the third negative logic sum means to output the second package option signal. The method according to any one of claims 5 to 16, The first and second package option pads are X4 pads and X8 pads. The method according to any one of claims 5 to 16, The first and second package option pads are X4 pads and X16 pads. The method according to any one of claims 5 to 16, The first and second package option pads are X8 pads and X16 pads. The method according to any one of claims 13 to 16, And the first and second buffer control signals are signals for selecting X16 and X8 package options in the test mode.